| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | tcg/riscv: Support ANDN, ORN, XNOR from Zbb | Richard Henderson | 2023-05-25 | 1 | -0/+1 |
| | | | | | | | Acked-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||||
| * | tcg/riscv: Simplify constraints on qemu_ld/st | Richard Henderson | 2023-05-11 | 1 | -1/+0 |
| | | | | | | | | | | | The softmmu tlb uses TCG_REG_TMP[0-2], not any of the normally available registers. Now that we handle overlap betwen inputs and helper arguments, we can allow any allocatable reg. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||||
| * | tcg/riscv: Split out target constraints to tcg-target-con-str.h | Richard Henderson | 2021-02-02 | 1 | -0/+21 |
| Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | |||||