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* tcg: Merge INDEX_op_orc_{i32,i64}Richard Henderson2025-04-281-4/+2
| | | | | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg: Convert orc to TCGOutOpBinaryRichard Henderson2025-04-281-4/+4
| | | | | | | | At the same time, drop all backend support for immediate operands, as we now transform orc to or during optimize. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg: Merge INDEX_op_or_{i32,i64}Richard Henderson2025-04-281-6/+3
| | | | | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg: Convert or to TCGOutOpBinaryRichard Henderson2025-04-281-0/+4
| | | | | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg: Merge INDEX_op_andc_{i32,i64}Richard Henderson2025-04-281-4/+2
| | | | | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg: Convert andc to TCGOutOpBinaryRichard Henderson2025-04-281-4/+4
| | | | | | | | At the same time, drop all backend support for immediate operands, as we now transform andc to and during optimize. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg: Merge INDEX_op_and_{i32,i64}Richard Henderson2025-04-281-6/+3
| | | | | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg: Convert and to TCGOutOpBinaryRichard Henderson2025-04-281-0/+4
| | | | | | | | | Drop all backend support for an immediate as the first operand. This should never happen in any case, as we swap commutative operands to place immediates as the second operand. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg: Merge INDEX_op_add_{i32,i64}Richard Henderson2025-04-281-10/+5
| | | | | | | Rely on TCGOP_TYPE instead of opcodes specific to each type. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg: Convert add to TCGOutOpBinaryRichard Henderson2025-04-281-2/+39
| | | | | | | | | Drop all backend support for an immediate as the first operand. This should never happen in any case, as we swap commutative operands to place immediates as the second operand. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg: Merge INDEX_op_mov_{i32,i64}Richard Henderson2025-04-281-14/+18
| | | | | | | | | Begin to rely on TCGOp.type to discriminate operations, rather than two different opcodes. Convert mov first. Introduce TCG_OPF_INT in order to keep opcode dumps the same. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg: Remove INDEX_op_ext{8,16,32}*Richard Henderson2025-04-281-46/+0
| | | | | | | Use the fully general extract opcodes instead. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg: Add all_outop[]Richard Henderson2025-04-281-8/+68
| | | | | | | | | | | Add infrastructure for more consolidated output of opcodes. The base structure allows for constraints to be either static or dynamic, and for the existence of those constraints to replace TCG_TARGET_HAS_* and the bulk of tcg_op_supported. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg: Add TCGType to tcg_op_insert_{after,before}Richard Henderson2025-04-281-7/+10
| | | | | | | | | | We cannot rely on the value copied from TCGOP_TYPE(op), because the relevant op could be typeless, such as INDEX_op_call. Fixes: fb744ece3a78 ("tcg: Copy TCGOP_TYPE in tcg_op_insert_{after,before}") Suggested-by: Nicholas Piggin <npiggin@gmail.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg: Pass max_threads not max_cpus to tcg_initRichard Henderson2025-04-231-7/+7
| | | | | | | | | In effect, hoist the check for mttcg from tcg_n_regions() to tcg_init_machine(). Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg: Allocate TEMP_VAL_MEM frame in temp_load()Philippe Mathieu-Daudé2025-04-031-0/+3
| | | | | | | | | | | | | | | | | | Be sure to allocate the temp frame if it wasn't. In the resolved issues, incomplete dead code elimination left a load at the top of an unreachable loop. We simply need to allocate the stack slot to avoid crashing. Fixes: c896fe29d6c ("TCG code generator") Reported-by: Michael Tokarev <mjt@tls.msk.ru> Reported-by: Helge Konetzka <hk@zapateado.de> Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2891 Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2899 Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-ID: <20250401144332.41615-1-philmd@linaro.org>
* tcg: Introduce the 'z' constraint for a hardware zero registerRichard Henderson2025-02-181-7/+22
| | | | | | | | | | | | | | | For loongarch, mips, riscv and sparc, a zero register is available all the time. For aarch64, register index 31 depends on context: sometimes it is the stack pointer, and sometimes it is the zero register. Introduce a new general-purpose constraint which maps 0 to TCG_REG_ZERO, if defined. This differs from existing constant constraints in that const_arg[*] is recorded as false, indicating that the value is in a register. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg: Replace addr{lo,hi}_reg with addr_reg in TCGLabelQemuLdstRichard Henderson2025-02-181-9/+9
| | | | | | | There is now always only one guest address register. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg: Merge INDEX_op_qemu_*_{a32,a64}_*Richard Henderson2025-02-181-28/+14
| | | | | | | | Since 64-on-32 is now unsupported, guest addresses always fit in one host register. Drop the replication of opcodes. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg: Drop support for two address registers in gen_ldstRichard Henderson2025-02-181-3/+1
| | | | | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg: Remove last traces of TCG_TARGET_NEED_POOL_LABELSRichard Henderson2025-02-181-4/+0
| | | | | | | | | | These should have been removed with the rest. There are a couple of hosts which can emit guest_base into the constant pool: aarch64, mips64, ppc64, riscv64. Fixes: a417ef835058 ("tcg: Remove TCG_TARGET_NEED_LDST_LABELS and TCG_TARGET_NEED_POOL_LABELS") Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
* tcg: Remove TCG_TARGET_HAS_deposit_{i32,i64}Richard Henderson2025-01-161-20/+11
| | | | | | | | | Make deposit "unconditional" in the sense that the opcode is always present. Rely instead on TCG_TARGET_deposit_valid, now always defined. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg: Remove TCG_TARGET_HAS_{s}extract_{i32,i64}Richard Henderson2025-01-161-8/+4
| | | | | | | | | Make extract and sextract "unconditional" in the sense that the opcodes are always present. Rely instead on TCG_TARGET_HAS_{s}extract_valid, now always defined. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg: Add TCGType argument to tcg_out_opRichard Henderson2025-01-161-2/+2
| | | | | | | | | | Pass TCGOp.type to the output function. For aarch64 and tci, use this instead of testing TCG_OPF_64BIT. For s390x, use this instead of testing INDEX_op_deposit_i64. For i386, use this to initialize rexw. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg: Pass type and flags to tcg_target_op_defRichard Henderson2025-01-161-2/+2
| | | | | | | Allow the backend to make constraint choices based on more parameters. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg: Add TCG_OPF_NOT_PRESENT to opcodes without inputs or outputsRichard Henderson2025-01-161-3/+0
| | | | | | | | | | The br, mb, goto_tb and exit_tb opcodes do not have register operands, only constants, flags, or labels. Remove the special case in opcode_args_ct by including TCG_OPF_NOT_PRESENT in the flags for these opcodes. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg: Validate op supported in opcode_args_ctRichard Henderson2025-01-161-0/+4
| | | | | | | | | We should have checked that the op is supported before emitting it. The backend cannot be expected to have a constraint set for unsupported ops. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg: Constify tcg_op_defsRichard Henderson2025-01-161-1/+1
| | | | | | | | Now that we're no longer assigning to TCGOpDef.args_ct, we can make the array constant. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg: Remove args_ct from TCGOpDefRichard Henderson2025-01-161-41/+37
| | | | | | | | | | | | | Introduce a new function, opcode_args_ct, to look up the argument set for an opcode. We lose the ability to assert the correctness of the map from TCGOpcode to constraint sets at startup, but we can still validate at runtime upon lookup. Rename process_op_defs to process_constraint_sets, as it now does nothing to TCGOpDef. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg: Reorg process_op_defsRichard Henderson2025-01-161-141/+139
| | | | | | | | | Process each TCGConstraintSetIndex first. Allocate TCGArgConstraint arrays based on those. Only afterward process the TCGOpcodes and share those TCGArgConstraint arrays. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg: Change have_vec to has_type in tcg_op_supportedRichard Henderson2025-01-161-23/+43
| | | | | | | | Test each vector type, not just lumping them all together. Add tests for I32 (always true) and I64 (64-bit hosts). Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg: Use C_NotImplemented in tcg_target_op_defRichard Henderson2025-01-161-4/+6
| | | | | | | | | Return C_NotImplemented instead of asserting for opcodes not implemented by the backend. For now, the assertion moves to process_op_defs. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg: Only include 'tcg-has.h' when necessaryRichard Henderson2025-01-161-0/+1
| | | | | | | | | TCG_TARGET_HAS_* definitions don't need to be exposed by "tcg/tcg.h". Only include 'tcg-has.h' when necessary. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <20250108215156.8731-15-philmd@linaro.org>
* tcg: Move fallback tcg_can_emit_vec_op out of lineRichard Henderson2025-01-161-0/+4
| | | | | | | Don't reference TCG_TARGET_MAYBE_vec in a public header. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg: Remove TCG_TARGET_NEED_LDST_LABELS and TCG_TARGET_NEED_POOL_LABELSRichard Henderson2025-01-161-13/+198
| | | | | | | | | | Make these features unconditional, as they're used by most tcg backends anyway. Merge tcg-ldst.c.inc and tcg-pool.c.inc into tcg.c and mark some of the functions unused, so that when the features are not used we won't get Werrors. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg: Add tcg_op_deposit_validRichard Henderson2025-01-161-0/+21
| | | | | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg: Add type and flags arguments to tcg_op_supportedRichard Henderson2025-01-161-4/+7
| | | | | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg: Copy TCGOP_TYPE in tcg_op_insert_{after,before}Richard Henderson2025-01-161-0/+4
| | | | | | | | Simplify use within the optimizers by defaulting the new opcode to the same type as the old opcode. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg: Replace TCGOP_VECL with TCGOP_TYPERichard Henderson2025-01-161-5/+6
| | | | | | | | | In the replacement, drop the TCGType - TCG_TYPE_V64 adjustment, except for the call to tcg_out_vec_op. Pass type to tcg_gen_op[1-6], so that all integer opcodes gain the type. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg: Reset free_temps before tcg_optimizeRichard Henderson2024-12-121-1/+4
| | | | | | | | | | | | | | | | | | When allocating new temps during tcg_optmize, do not re-use any EBB temps that were used within the TB. We do not have any idea what span of the TB in which the temp was live. Introduce tcg_temp_ebb_reset_freed and use before tcg_optimize, as well as replacing the equivalent in plugin_gen_inject and tcg_func_start. Cc: qemu-stable@nongnu.org Fixes: fb04ab7ddd8 ("tcg/optimize: Lower TCG_COND_TST{EQ,NE} if unsupported") Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2711 Reported-by: wannacu <wannacu2049@gmail.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
* tcg: Reset data_gen_ptr correctlyRichard Henderson2024-10-221-1/+1
| | | | | | | | | | | | This pointer needs to be reset after overflow just like code_buf and code_ptr. Cc: qemu-stable@nongnu.org Fixes: 57a269469db ("tcg: Infrastructure for managing constant pools") Acked-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* include/exec/memop: Rename get_alignment_bitsRichard Henderson2024-10-131-1/+1
| | | | | | | | | | Rename to use "memop_" prefix, like other functions that operate on MemOp. Reviewed-by: Helge Deller <deller@gmx.de> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* plugins: Merge alloc_tcg_plugin_context into plugin_gen_tb_startRichard Henderson2024-05-151-11/+0
| | | | | | | | We don't need to allocate plugin context at startup, we can wait until we actually use it. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* plugins: Use translator_st for qemu_plugin_insn_dataRichard Henderson2024-05-151-2/+1
| | | | | | | | | | Use the bytes that we record for the entire TB, rather than a per-insn GByteArray. Record the length of the insn in plugin_gen_insn_end rather than infering from the length of the array. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* plugins: Replace pr_ops with a proper debug dump flagRichard Henderson2024-04-301-1/+28
| | | | | | | | The DEBUG_PLUGIN_GEN_OPS ifdef is replaced with "-d op_plugin". The second pr_ops call can be obtained with "-d op". Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg: Remove TCG_CALL_PLUGINRichard Henderson2024-04-301-3/+1
| | | | | | | | Since we no longer emit plugin helpers during the initial code translation phase, we don't need to specially mark plugin helpers. Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg: Pass function pointer to tcg_gen_call*Richard Henderson2024-04-301-21/+24
| | | | | | | | | | For normal helpers, read the function pointer from the structure earlier. For plugins, this will allow the function pointer to come from elsewhere. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* exec: Rename 'exec/user/guest-base.h' as 'user/guest-base.h'Philippe Mathieu-Daudé2024-04-261-1/+1
| | | | | | | | | The include/user/ directory contains the user-emulation specific headers. Move guest-base.h there too. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Anton Johansson <anjo@rev.ng> Message-Id: <20240418192525.97451-15-philmd@linaro.org>
* tcg: Add TCGContext.emit_before_opRichard Henderson2024-04-091-2/+12
| | | | | | | | | | Allow operations to be emitted via normal expanders into the middle of the opcode stream. Tested-by: Jørgen Hansen <Jorgen.Hansen@wdc.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg: Add TCGConst argument to tcg_target_const_matchRichard Henderson2024-02-031-2/+32
| | | | | | | | Fill the new argument from any condition within the opcode. Not yet used within any backend. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>