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* tcg/s390x: Fix encoding of VRIc, VRSa, VRSc insnsRichard Henderson2024-01-231-3/+3
| | | | | | | | | | | | | | | | | | | | While the format names the second vector register 'v3', it is still in the second position (bits 12-15) and the argument to RXB must match. Example error: - e7 00 00 10 2a 33 verllf %v16,%v0,16 + e7 00 00 10 2c 33 verllf %v16,%v16,16 Cc: qemu-stable@nongnu.org Reported-by: Michael Tokarev <mjt@tls.msk.ru> Fixes: 22cb37b4172 ("tcg/s390x: Implement vector shift operations") Fixes: 79cada8693d ("tcg/s390x: Implement tcg_out_dup*_vec") Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2054 Reviewed-by: Thomas Huth <thuth@redhat.com> Tested-by: Michael Tokarev <mjt@tls.msk.ru> Message-Id: <20240117213646.159697-2-richard.henderson@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg: Make the cleanup-on-error path uniqueSamuel Tardieu2024-01-231-3/+3
| | | | | | | | | | By calling `error_setg_errno()` before jumping to the cleanup-on-error path at the `fail` label, the cleanup path is clearer. Signed-off-by: Samuel Tardieu <sam@rfc1149.net> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-Id: <20231219182212.455952-3-sam@rfc1149.net> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg: Remove unreachable codeSamuel Tardieu2024-01-231-3/+1
| | | | | | | | | | | | The `fail_rx`/`fail` block is only entered while `buf_rx` is equal to its initial value `MAP_FAILED`. The `munmap(buf_rx, size);` was never executed. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2030 Signed-off-by: Samuel Tardieu <sam@rfc1149.net> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-Id: <20231219182212.455952-2-sam@rfc1149.net> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg/ppc: Use new registers for LQ destinationRichard Henderson2024-01-113-7/+19
| | | | | | | | | | | | | | LQ has a constraint that RTp != RA, else SIGILL. Therefore, force the destination of INDEX_op_qemu_*_ld128 to be a new register pair, so that it cannot overlap the input address. This requires new support in process_op_defs and tcg_reg_alloc_op. Cc: qemu-stable@nongnu.org Fixes: 526cd4ec01f ("tcg/ppc: Support 128-bit load/store") Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20240102013456.131846-1-richard.henderson@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg/i386: use 8-bit OR or XOR for unsigned 8-bit immediatesPaolo Bonzini2024-01-111-0/+11
| | | | | | | | | | | In the case where OR or XOR has an 8-bit immediate between 128 and 255, we can operate on a low-byte register and shorten the output by two or three bytes (two if a prefix byte is needed for REX.B). Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Message-Id: <20231228120524.70239-1-pbonzini@redhat.com> [rth: Incorporate into switch.] Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg/i386: convert add/sub of 128 to sub/add of -128Paolo Bonzini2024-01-111-15/+34
| | | | | | | | | | | Extend the existing conditional that generates INC/DEC, to also swap an ADD for a SUB and vice versa when the immediate is 128. This facilitates using OPC_ARITH_EvIb instead of OPC_ARITH_EvIz. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Message-Id: <20231228120514.70205-1-pbonzini@redhat.com> [rth: Use a switch on C] Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* meson: remove config_targetosPaolo Bonzini2023-12-311-1/+1
| | | | | | | | | | | | | | config_targetos is now empty and can be removed; its use in sourcesets that do not involve target-specific files can be replaced with an empty dictionary. In fact, at this point *all* sourcesets that do not involve target-specific files are just glorified mutable arrays. Enforce that they never test for symbols in "when:" by computing the set of files without "strict: false". Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* tcg: Reduce serial context atomicity earlierRichard Henderson2023-12-122-12/+25
| | | | | | | | | | | Reduce atomicity while emitting opcodes, instead of later during code generation. This ensures that any helper called also sees the reduced atomicity requirement. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2034 Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Tested-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20231212193542.149117-1-richard.henderson@linaro.org>
* tcg/loongarch64: Fix tcg_out_mov() AbortedSong Gao2023-11-211-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On LoongArch host, we got an Aborted from tcg_out_mov(). qemu-x86_64 configure with '--enable-debug'. > (gdb) b /home1/gaosong/code/qemu/tcg/loongarch64/tcg-target.c.inc:312 > Breakpoint 1 at 0x2576f0: file /home1/gaosong/code/qemu/tcg/loongarch64/tcg-target.c.inc, line 312. > (gdb) run hello [...] > Thread 1 "qemu-x86_64" hit Breakpoint 1, tcg_out_mov (s=0xaaaae91760 <tcg_init_ctx>, type=TCG_TYPE_V128, ret=TCG_REG_V2, > arg=TCG_REG_V0) at /home1/gaosong/code/qemu/tcg/loongarch64/tcg-target.c.inc:312 > 312 g_assert_not_reached(); > (gdb) bt > #0 tcg_out_mov (s=0xaaaae91760 <tcg_init_ctx>, type=TCG_TYPE_V128, ret=TCG_REG_V2, arg=TCG_REG_V0) > at /home1/gaosong/code/qemu/tcg/loongarch64/tcg-target.c.inc:312 > #1 0x000000aaaad0fee0 in tcg_reg_alloc_mov (s=0xaaaae91760 <tcg_init_ctx>, op=0xaaaaf67c20) at ../tcg/tcg.c:4632 > #2 0x000000aaaad142f4 in tcg_gen_code (s=0xaaaae91760 <tcg_init_ctx>, tb=0xffe8030340 <code_gen_buffer+197328>, > pc_start=4346094) at ../tcg/tcg.c:6135 [...] > (gdb) c > Continuing. > ** > ERROR:/home1/gaosong/code/qemu/tcg/loongarch64/tcg-target.c.inc:312:tcg_out_mov: code should not be reached > Bail out! ERROR:/home1/gaosong/code/qemu/tcg/loongarch64/tcg-target.c.inc:312:tcg_out_mov: code should not be reached > > Thread 1 "qemu-x86_64" received signal SIGABRT, Aborted. > 0x000000fff7b1c390 in raise () from /lib64/libc.so.6 > (gdb) q Fixes: 16288ded94 ("tcg/loongarch64: Lower basic tcg vec ops to LSX") Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Song Gao <gaosong@loongson.cn> Message-Id: <20231120065916.374045-1-gaosong@loongson.cn>
* tcg/sparc64: Implement tcg_out_extrl_i64_i32Richard Henderson2023-11-061-0/+5
| | | | | | | | | Build fix for missing symbol. Cc: qemu-stable@nongnu.org Fixes: dad2f2f5af ("tcg/sparc64: Disable TCG_TARGET_HAS_extr_i64_i32") Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg/optimize: Canonicalize sub2 with constants to add2Richard Henderson2023-11-061-2/+19
| | | | | | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20231026013945.1152174-4-richard.henderson@linaro.org>
* tcg/optimize: Canonicalize subi to addi during optimizationRichard Henderson2023-11-061-1/+13
| | | | | | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20231026013945.1152174-3-richard.henderson@linaro.org>
* tcg: Canonicalize subi to addi during opcode generationRichard Henderson2023-11-061-16/+2
| | | | | | | Suggested-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20231026013945.1152174-2-richard.henderson@linaro.org>
* tcg/optimize: Split out arg_new_constantRichard Henderson2023-11-061-11/+18
| | | | | | | | Fixes a bug wherein raw uses of tcg_constant_internal do not have their TempOptInfo initialized. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg: Eliminate duplicate env store operationsRichard Henderson2023-11-061-0/+13
| | | | | | | Notice when a constant is stored to the same location twice. Reviewed-by: Song Gao <gaosong@loongson.cn> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg/optimize: Optimize env memory operationsRichard Henderson2023-11-061-21/+243
| | | | | | | Propagate stores to loads, loads to loads. Reviewed-by: Song Gao <gaosong@loongson.cn> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg/optimize: Split out cmp_better_copyRichard Henderson2023-11-061-18/+11
| | | | | | | | Compare two temps for "better", split out from finding the best from a whole list. Use TCGKind, which already gives the proper priority. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg/optimize: Pipe OptContext into reset_tsRichard Henderson2023-11-061-7/+7
| | | | | | | | Will be needed in the next patch. Reviewed-by: Song Gao <gaosong@loongson.cn> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg: Don't free vector resultsRichard Henderson2023-11-061-74/+38
| | | | | | | | Avoid reusing vector temporaries so that we may re-use them when propagating stores to loads. Reviewed-by: Song Gao <gaosong@loongson.cn> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg: Remove TCG_TARGET_HAS_neg_{i32,i64}Richard Henderson2023-11-0614-40/+13
| | | | | | | The movcond opcode is now mandatory for backends to implement. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20231026041404.1229328-7-richard.henderson@linaro.org>
* tcg/loongarch64: Implement neg opcodesRichard Henderson2023-11-062-2/+11
| | | | | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20231026041404.1229328-6-richard.henderson@linaro.org>
* tcg/mips: Implement neg opcodesRichard Henderson2023-11-062-2/+10
| | | | | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20231026041404.1229328-5-richard.henderson@linaro.org>
* tcg: Remove TCG_TARGET_HAS_movcond_{i32,i64}Richard Henderson2023-11-0612-63/+12
| | | | | | | The movcond opcode is now mandatory for backends to implement. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20231026041404.1229328-4-richard.henderson@linaro.org>
* tcg/mips: Always implement movcondRichard Henderson2023-11-062-7/+16
| | | | | | | Expand as branch over move if not supported in the ISA. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20231026041404.1229328-3-richard.henderson@linaro.org>
* tcg/mips: Split out tcg_out_setcond_intRichard Henderson2023-11-061-172/+106
| | | | | | | | Return the temp and a set of flags, to be used as a primitive for setcond, brcond, movcond. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20231026041404.1229328-2-richard.henderson@linaro.org>
* tcg: Move tcg_temp_free_* out of lineRichard Henderson2023-11-061-0/+25
| | | | | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20231029210848.78234-12-richard.henderson@linaro.org>
* tcg: Move tcg_temp_new_*, tcg_global_mem_new_* out of lineRichard Henderson2023-11-061-3/+61
| | | | | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20231029210848.78234-11-richard.henderson@linaro.org>
* tcg: Move tcg_constant_* out of lineRichard Henderson2023-11-062-0/+22
| | | | | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20231029210848.78234-10-richard.henderson@linaro.org>
* tcg: Unexport tcg_gen_op*_{i32,i64}Richard Henderson2023-11-061-79/+52
| | | | | | | | These functions are no longer used outside tcg-op.c. There are several that are completely unused, so remove them. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20231029210848.78234-9-richard.henderson@linaro.org>
* tcg: Move tcg_gen_opN declarations to tcg-internal.hRichard Henderson2023-11-061-0/+7
| | | | | | | | These are used within tcg-op.c and tcg-op-ldst.c. There are no uses outside tcg/. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20231029210848.78234-8-richard.henderson@linaro.org>
* tcg: Move vec_gen_* declarations to tcg-internal.hRichard Henderson2023-11-061-0/+4
| | | | | | | | These are used within tcg-op-vec.c and tcg/host/tcg-target.c.inc. There are no uses outside tcg/. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20231029210848.78234-7-richard.henderson@linaro.org>
* tcg: Move 64-bit expanders out of lineRichard Henderson2023-11-061-67/+164
| | | | | | | | This one is more complicated, combining 32-bit and 64-bit expansion with C if instead of preprocessor #if. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20231029210848.78234-6-richard.henderson@linaro.org>
* tcg: Move 32-bit expanders out of lineRichard Henderson2023-11-061-0/+116
| | | | | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20231029210848.78234-5-richard.henderson@linaro.org>
* tcg: Move generic expanders out of lineRichard Henderson2023-11-061-0/+16
| | | | | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20231029210848.78234-4-richard.henderson@linaro.org>
* tcg: Move tcg_gen_op* out of lineRichard Henderson2023-11-061-0/+208
| | | | | | | | In addition to moving out of line, with CONFIG_DEBUG_TCG mark them all noinline. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20231029210848.78234-3-richard.henderson@linaro.org>
* tcg: Mark tcg_gen_op* as noinlineRichard Henderson2023-11-061-8/+14
| | | | | | | | Encourage the compiler to tail-call rather than inline across the dozens of opcode expanders. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20231029210848.78234-2-richard.henderson@linaro.org>
* tcg/loongarch64: Use cpuinfo.hRichard Henderson2023-11-062-11/+5
| | | | | | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Jiajie Chen <c@jia.je> Message-Id: <20230916220151.526140-5-richard.henderson@linaro.org>
* tcg/loongarch64: Use C_N2_I1 for INDEX_op_qemu_ld_a*_i128Richard Henderson2023-11-062-7/+12
| | | | | | | | | | Use new registers for the output, so that we never overlap the input address, which could happen for user-only. This avoids a "tmp = addr + 0" in that case. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Jiajie Chen <c@jia.je> Message-Id: <20230916220151.526140-3-richard.henderson@linaro.org>
* tcg: Add C_N2_I1Richard Henderson2023-11-061-0/+5
| | | | | | | | Constraint with two outputs, both in new registers. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Jiajie Chen <c@jia.je> Message-Id: <20230916220151.526140-2-richard.henderson@linaro.org>
* accel/tcg: Move HMP info jit and info opcount codeRichard Henderson2023-11-061-10/+0
| | | | | | | | | | Move all of it into accel/tcg/monitor.c. This puts everything about tcg that is only used by the monitor in the same place. Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg: Export tcg_gen_ext_{i32,i64,tl}Richard Henderson2023-10-221-4/+10
| | | | | | | | The two concrete type functions already existed, merely needing a bit of hardening to invalid inputs. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg: add negsetcondiPaolo Bonzini2023-10-221-0/+12
| | | | | | | | | This can be useful to write a shift bit extraction that does not depend on TARGET_LONG_BITS. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Message-Id: <20231019104648.389942-15-pbonzini@redhat.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg: Add tcg_gen_{ld,st}_i128Richard Henderson2023-10-221-0/+22
| | | | | | | | | | Do not require the translators to jump through concat and extract of i64 in order to move values to and from env. Tested-by: Song Gao <gaosong@loongson.cn> Reviewed-by: Song Gao <gaosong@loongson.cn> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg: Optimize past conditional branchesRichard Henderson2023-10-221-3/+5
| | | | | | | We already register allocate through extended basic blocks, optimize through extended basic blocks as well. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg: Use constant zero when expanding with divu2Richard Henderson2023-10-221-8/+8
| | | | Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg/s390x: Use tcg_use_softmmuRichard Henderson2023-10-221-80/+77
| | | | | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg/riscv: Use tcg_use_softmmuRichard Henderson2023-10-221-87/+90
| | | | Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg/riscv: Do not reserve TCG_GUEST_BASE_REG for guest_base zeroRichard Henderson2023-10-221-2/+4
| | | | | Fixes: 92c041c59b ("tcg/riscv: Add the prologue generation and register the JIT") Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg/ppc: Use tcg_use_softmmuRichard Henderson2023-10-221-127/+129
| | | | | | | Fix TCG_GUEST_BASE_REG to use 'TCG_REG_R30' instead of '30'. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg/mips: Use tcg_use_softmmuRichard Henderson2023-10-221-110/+105
| | | | | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>