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* Merge tag 'pull-tcg-20250711' of https://gitlab.com/rth7680/qemu into stagingStefan Hajnoczi2025-07-132-0/+38
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | fpu: Process float_muladd_negate_result after rounding tcg: Use uintptr_t in tcg_malloc implementation linux-user: Hold the fd-trans lock across fork linux-user: Implement fchmodat2 syscall linux-user: Check for EFAULT failure in nanosleep linux-user: Use qemu_set_cloexec() to mark pidfd as FD_CLOEXEC linux-user/gen-vdso: Handle fseek() failure linux-user/gen-vdso: Don't read off the end of buf[] # -----BEGIN PGP SIGNATURE----- # # iQFRBAABCgA7FiEEekgeeIaLTbaoWgXAZN846K9+IV8FAmhxSAkdHHJpY2hhcmQu # aGVuZGVyc29uQGxpbmFyby5vcmcACgkQZN846K9+IV9wiQf+PrXwKj+FusE0YU1y # Lnx6+S0M/lDRCNhbgBrw7JK5WUwIfnZQuepf0vjuhoHH1rUdT1EUYdJ7Quwj9fgG # 0YcKRD8OAVKNU8I3ydtzSaJ3TZ02nbbDbwGMoD/eNXGKx0Gt5907vD4PrjT+mByG # 6QTLwuql3ahkl/Tiskk2LwbmHRe0CXiezVuzgprbNiyxrgDT8ArqCq+VJzv/wb2O # 4t6BqRDvBzRe7MUUs2B2W+hs0HW4Rfqcye/3rRnYe7HA4CTiVNqY9rwgrQqGEO0P # 3Cf+VaF6CaLz+HuHfM8rz+xBhfo+UpZYOVMXk/7VEAG6geMKTcQG1tCJYhL+xklJ # 9r4ABw== # =rD+6 # -----END PGP SIGNATURE----- # gpg: Signature made Fri 11 Jul 2025 13:21:13 EDT # gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F # gpg: issuer "richard.henderson@linaro.org" # gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [full] # Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A 05C0 64DF 38E8 AF7E 215F * tag 'pull-tcg-20250711' of https://gitlab.com/rth7680/qemu: linux-user: Use qemu_set_cloexec() to mark pidfd as FD_CLOEXEC tcg: Use uintptr_t in tcg_malloc implementation linux-user: Hold the fd-trans lock across fork linux-user/mips/o32: Drop sa_restorer functionality linux-user/gen-vdso: Don't read off the end of buf[] linux-user/gen-vdso: Handle fseek() failure linux-user: Check for EFAULT failure in nanosleep linux-user: Implement fchmodat2 syscall fpu: Process float_muladd_negate_result after rounding Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
| * fpu: Process float_muladd_negate_result after roundingRichard Henderson2025-07-102-0/+38
| | | | | | | | | | | | | | | | | | Changing the sign before rounding affects the correctness of the asymmetric rouding modes: float_round_up and float_round_down. Reported-by: WANG Rui <wangrui@loongson.cn> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* | Merge tag 'migration-20250711-pull-request' of ↵Stefan Hajnoczi2025-07-131-0/+5
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | https://gitlab.com/farosas/qemu into staging Migration pull request - General cleanups around: postcopy, bg-snapshot, migration hooks, migration completion and formatting of 'info migrate'. - Overhaul of postcopy blocktime tracking. # -----BEGIN PGP SIGNATURE----- # # iQJEBAABCAAuFiEEqhtIsKIjJqWkw2TPx5jcdBvsMZ0FAmhxGdgQHGZhcm9zYXNA # c3VzZS5kZQAKCRDHmNx0G+wxnahoD/9uNXirlmRk3tDnhiJsiYx+HnXYPFEORSZq # zlpUyqvhQ1POp3Fa5pRf+bJ5mmPw8h8PdOR2StMpnW2Xa1OatAZj5m1uityAVWOl # EkVfZLl0j6j9HCCmE3c4dztOGIBsd9YY0GWizL05XHYZPrdX4zOpolMN4m53RwQY # HUVD6T2y9eFDnCO6MsoA9EfmkFYCRvqlS0VzTcYzQFN4H+QHlcpDfweqJpTLPa+1 # trahAN9PBuMjoewjDqwkNkf0CLaCXHszAfj6yv62Vi8Cbp9DDPywIYJKFnxspElW # Fjg1b4MdsbYZNmeKgIawzgTOL1RrojvKkoi7KWp3D7M+/ZZl9kBwQuUcBXKI7N0R # Y0GNfkkTycn18nM0JU/6QWSuVeiPbLArxQUGP1cLgvcHSSNgD9JxWbNBu5+1fFOG # Gg3qnyYatJ6xJDiCrdKqV8fwozNlm/G6b9BiCDeVq+4nA2OKQ0shiNA1GZHvVSQL # X4uAPexETdHfA/LeA2w5sgVBEw7BewBdjLntZDIFsyBnLrvqrDcU5Aav0wiHoI8U # QBC2aIpJfMLHiIQ93mVX96NltXC7KvJTIZVl3iwfiYEYCvQtTYgdJ09ELXFJYxFX # XpTTazqpmPSfuZpPRgx9YbDP/kS8Fg/PTOlPeD0T/frFgd1S6Thh6OW455PavMp8 # ht2lE4sxjA== # =vtRD # -----END PGP SIGNATURE----- # gpg: Signature made Fri 11 Jul 2025 10:04:08 EDT # gpg: using RSA key AA1B48B0A22326A5A4C364CFC798DC741BEC319D # gpg: issuer "farosas@suse.de" # gpg: Good signature from "Fabiano Rosas <farosas@suse.de>" [unknown] # gpg: aka "Fabiano Almeida Rosas <fabiano.rosas@suse.com>" [unknown] # gpg: WARNING: The key's User ID is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: AA1B 48B0 A223 26A5 A4C3 64CF C798 DC74 1BEC 319D * tag 'migration-20250711-pull-request' of https://gitlab.com/farosas/qemu: (26 commits) migration: Rename save_live_complete_precopy_thread to save_complete_precopy_thread migration/postcopy: Add latency distribution report for blocktime migration/postcopy: blocktime allows track / report non-vCPU faults migration/postcopy: Optimize blocktime fault tracking with hashtable migration/postcopy: Cleanup the total blocktime accounting migration/postcopy: Cache the tid->vcpu mapping for blocktime migration/postcopy: Initialize blocktime context only until listen migration/postcopy: Report fault latencies in blocktime migration/postcopy: Add blocktime fault counts per-vcpu migration/postcopy: Bring blocktime layer to ns level migration/postcopy: Drop PostcopyBlocktimeContext.start_time migration/postcopy: Make all blocktime vars 64bits migration/postcopy: Drop all atomic ops in blocktime feature migration/postcopy: Push blocktime start/end into page req mutex migration: Add option to set postcopy-blocktime migration/postcopy: Avoid clearing dirty bitmap for postcopy too migration: Rewrite the migration complete detect logic migration/ram: Add tracepoints for ram_save_complete() migration/ram: One less indent for ram_find_and_save_block() migration: qemu_savevm_complete*() helpers ... Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
| * | migration/postcopy: Add latency distribution report for blocktimePeter Xu2025-07-111-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add the latency distribution too for blocktime, using order-of-two buckets. It accounts for all the faults, from either vCPU or non-vCPU threads. With prior rework, it's very easy to achieve by adding an array to account for faults in each buckets. Sample output for HMP (while for QMP it's simply an array): Postcopy Latency Distribution: [ 1 us - 2 us ]: 0 [ 2 us - 4 us ]: 0 [ 4 us - 8 us ]: 1 [ 8 us - 16 us ]: 2 [ 16 us - 32 us ]: 2 [ 32 us - 64 us ]: 3 [ 64 us - 128 us ]: 10169 [ 128 us - 256 us ]: 50151 [ 256 us - 512 us ]: 12876 [ 512 us - 1 ms ]: 97 [ 1 ms - 2 ms ]: 42 [ 2 ms - 4 ms ]: 44 [ 4 ms - 8 ms ]: 93 [ 8 ms - 16 ms ]: 138 [ 16 ms - 32 ms ]: 0 [ 32 ms - 65 ms ]: 0 [ 65 ms - 131 ms ]: 0 [ 131 ms - 262 ms ]: 0 [ 262 ms - 524 ms ]: 0 [ 524 ms - 1 sec ]: 0 [ 1 sec - 2 sec ]: 0 [ 2 sec - 4 sec ]: 0 [ 4 sec - 8 sec ]: 0 [ 8 sec - 16 sec ]: 0 Cc: Markus Armbruster <armbru@redhat.com> Acked-by: Dr. David Alan Gilbert <dave@treblig.org> Reviewed-by: Fabiano Rosas <farosas@suse.de> Link: https://lore.kernel.org/r/20250613141217.474825-15-peterx@redhat.com Signed-off-by: Peter Xu <peterx@redhat.com> Signed-off-by: Fabiano Rosas <farosas@suse.de>
| * | migration/postcopy: blocktime allows track / report non-vCPU faultsPeter Xu2025-07-111-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When used to report page fault latencies, the blocktime feature can be almost useless when KVM async page fault is enabled, because in most cases such remote fault will kickoff async page faults, then it's not trackable from blocktime layer. After all these recent rewrites to blocktime layer, it's finally so easy to also support tracking non-vCPU faults. It'll be even faster if we could always index fault records with TIDs, unfortunately we need to maintain the blocktime API which report things in vCPU indexes. Of course this can work not only for kworkers, but also any guest accesses that may reach a missing page, for example, very likely when in the QEMU main thread too (and all other threads whenever applicable). In this case, we don't care about "how long the threads are blocked", but we only care about "how long the fault will be resolved". Cc: Markus Armbruster <armbru@redhat.com> Cc: Dr. David Alan Gilbert <dave@treblig.org> Reviewed-by: Fabiano Rosas <farosas@suse.de> Tested-by: Mario Casquero <mcasquer@redhat.com> Link: https://lore.kernel.org/r/20250613141217.474825-14-peterx@redhat.com Signed-off-by: Peter Xu <peterx@redhat.com> Signed-off-by: Fabiano Rosas <farosas@suse.de>
| * | migration/postcopy: Report fault latencies in blocktimePeter Xu2025-07-111-0/+3
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Blocktime so far only cares about the time one vcpu (or the whole system) got blocked. It would be also be helpful if it can also report the latency of page requests, which could be very sensitive during postcopy. Blocktime itself is sometimes not very important, especially when one thinks about KVM async PF support, which means vCPUs are literally almost not blocked at all because the guest OS is smart enough to switch to another task when a remote fault is needed. However, latency is still sensitive and important because even if the guest vCPU is running on threads that do not need a remote fault, the workload that accesses some missing page is still affected. Add two entries to the report, showing how long it takes to resolve a remote fault. Mention in the QAPI doc that this is not the real average fault latency, but only the ones that was requested for a remote fault. Unwrap get_vcpu_blocktime_list() so we don't need to walk the list twice, meanwhile add the entry checks in qtests for all postcopy tests. Cc: Markus Armbruster <armbru@redhat.com> Cc: Dr. David Alan Gilbert <dave@treblig.org> Reviewed-by: Fabiano Rosas <farosas@suse.de> Tested-by: Mario Casquero <mcasquer@redhat.com> Link: https://lore.kernel.org/r/20250613141217.474825-9-peterx@redhat.com Signed-off-by: Peter Xu <peterx@redhat.com> Signed-off-by: Fabiano Rosas <farosas@suse.de>
* | Merge tag 'pull-target-arm-20250711' of https://gitlab.com/pm215/qemu into ↵Stefan Hajnoczi2025-07-134-13/+95
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | staging target-arm queue: * New board type max78000fthr * Enable use of CXL on Arm 'virt' board * Some more tidyup of ID register handling * Refactor AT insns and PMU regs into separate source files * Don't enforce NSE,NS check for EL3->EL3 returns * hw/arm/fsl-imx8mp: Wire VIRQ and VFIQ * Allow nested-virtualization with KVM on the 'virt' board * system/qdev: Remove pointless NULL check in qdev_device_add_from_qdict * hw/arm/virt-acpi-build: Don't create ITS id mappings by default * target/arm: Remove unused helper_sme2_luti4_4b # -----BEGIN PGP SIGNATURE----- # # iQJNBAABCAA3FiEE4aXFk81BneKOgxXPPCUl7RQ2DN4FAmhxEcoZHHBldGVyLm1h # eWRlbGxAbGluYXJvLm9yZwAKCRA8JSXtFDYM3j5yEACWYnNeqo8Yph6/EJExE6eV # r0tC6FBb5ShPgA6kDxhpOc1lI6uXGh8+D7bL9BePEdz/brCf1QDfs2Z4q/hb5ysX # D0H6VI5Gr1j6MjkFRBo3+vvYz4Yh++XLn5Q9lZv8zaSEdraq/ay2kxnuhRCK+4Ar # +QoGtKrGMJ7UCpfiRlvNnd1UjgORZf10EE/bRImX13sxeDomP3CZhFzAyJyShOP9 # JA7bAd4rYJ4oj8R33y8Yaxjwm4FOndj740B0zwpO8mpjzFiE5zbqsaO+mEgYSflc # OQisCu/KRFpyIR+UqP+4gNaJLfKQW5Y4r61zEaiJWV/c4RdKNnbK1f7MX11fNhOk # k1paF3GIXp6f794Hb14vtsYnKHF2eeNSmRkAomXxLgUSYzLezL+yj7cdYmRJhgYU # thc1PSiEmHYhjRmOaMC9+dkMtvIexWyDNYNFTygoOE5/kTMSazeTFQpFmw+ZuTee # 9pjKsYRZJgTa64IkJy1L34jc2gds48Q20KpQsqZ22KQcjwt4PW4eQXkvMylawSut # mArHVH6AAxIK+defeEmnQCJ0OccyGCENjRDuWyWMMGoP/ggZpO47rGWmCUOK8xz8 # IfGdPeF/9xsKSKWvjpiHyyKa48wuO2bVC+5bISS6IPA2uGneS2DpmjkHU+gHBqpk # GNlvEnXZfavZOHejE7/L/Q== # =hJ4/ # -----END PGP SIGNATURE----- # gpg: Signature made Fri 11 Jul 2025 09:29:46 EDT # gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE # gpg: issuer "peter.maydell@linaro.org" # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [full] # gpg: aka "Peter Maydell <pmaydell@gmail.com>" [full] # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [full] # gpg: aka "Peter Maydell <peter@archaic.org.uk>" [unknown] # Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE * tag 'pull-target-arm-20250711' of https://gitlab.com/pm215/qemu: (36 commits) tests/functional: Add a test for the MAX78000 arm machine docs/system: arm: Add max78000 board description target/arm: Remove helper_sme2_luti4_4b hw/arm/virt-acpi-build: Don't create ITS id mappings by default system/qdev: Remove pointless NULL check in qdev_device_add_from_qdict hw/arm/virt: Allow virt extensions with KVM hw/arm/arm_gicv3_kvm: Add a migration blocker with kvm nested virt target/arm: Enable feature ARM_FEATURE_EL2 if EL2 is supported target/arm/kvm: Add helper to detect EL2 when using KVM hw/arm: Allow setting KVM vGIC maintenance IRQ hw/arm/fsl-imx8mp: Wire VIRQ and VFIQ target/arm: Don't enforce NSE,NS check for EL3->EL3 returns target/arm: Split out performance monitor regs to cpregs-pmu.c target/arm: Split out AT insns to tcg/cpregs-at.c target/arm: Drop stub for define_tlb_insn_regs arm/kvm: shorten one overly long line arm/cpu: store clidr into the idregs array arm/cpu: fix trailing ',' for SET_IDREG arm/cpu: store id_aa64afr{0,1} into the idregs array arm/cpu: store id_afr0 into the idregs array ... Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
| * | tests/functional: Add a test for the MAX78000 arm machineJackson Donaldson2025-07-112-0/+49
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Runs a binary from the max78000test repo used in developing the qemu implementation of the max78000 to verify that the machine and implemented devices generally still work. Signed-off-by: Jackson Donaldson <jcksn@duck.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Message-id: 20250711110626.624534-3-jcksn@duck.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * | qtest/cxl: Add aarch64 virt test for CXLJonathan Cameron2025-07-102-13/+46
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a single complex case for aarch64 virt machine. Given existing much more comprehensive tests for x86 cover the common functionality, a single test should be enough to verify that the aarch64 part continues to work. Tested-by: Itaru Kitayama <itaru.kitayama@fujitsu.com> Reviewed-by: Eric Auger <eric.auger@redhat.com> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Tested-by: Li Zhijian <lizhijian@fujitsu.com> Message-id: 20250703104110.992379-6-Jonathan.Cameron@huawei.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* | tests/functional/test_ppc_bamboo: Replace broken link with working assetsThomas Huth2025-07-111-15/+19
| | | | | | | | | | | | | | | | | | | | | | | | The old image that we used for testing the bamboo machine has disappeared from the internet. Fortunately there is another kernel + initrd provided by Cédric that can be used for testing this machine, too. Reported-by: Stefan Hajnoczi <stefanha@gmail.com> Suggested-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Cédric Le Goater <clg@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com> Message-ID: <20250707184736.88660-1-thuth@redhat.com>
* | tests/functional: Add dependency to the keymap_targetsThomas Huth2025-07-111-1/+1
| | | | | | | | | | | | | | | | | | | | | | When doing a "configure" in a an empty build directory, followed by a "make check" without a normal build in between, the vnc functional test currently fails since the keymaps have not been built yet. Thus add a dependency to the keymap_targets here to make sure that the keymaps are built before running the functional tests. Signed-off-by: Thomas Huth <thuth@redhat.com> Message-ID: <20250701104827.363904-1-thuth@redhat.com>
* | tests/functional: Add a test for s390x pxelinux.cfg network bootingThomas Huth2025-07-112-0/+120
|/ | | | | | | | | | | | Check the various ways of booting a kernel via pxelinux.cfg file, e.g. by specifying the config file name via the MAC address or the UUID of the guest. Also check whether we can successfully load an alternate kernel via the "loadparm" parameter here and whether the boot menu shows up with "-boot menu=on". Reviewed-by: Jared Rossi <jrossi@linux.ibm.com> Signed-off-by: Thomas Huth <thuth@redhat.com> Message-ID: <20250709083443.41574-6-thuth@redhat.com>
* Merge tag 'pull-riscv-to-apply-20250704' of ↵Stefan Hajnoczi2025-07-043-0/+77
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | https://github.com/alistair23/qemu into staging Second RISC-V PR for 10.1 * sstc extension fixes * Fix zama16b order in isa_edata_arr * Profile handling fixes * Extend PMP region up to 64 * Remove capital 'Z' CPU properties * Add missing named features * Support atomic instruction fetch (Ziccif) * Add max_satp_mode from host cpu * Extend and configure PMP region count * Fix PPN field of Translation-reponse register * Use qemu_chr_fe_write_all() in DBCN_CONSOLE_WRITE_BYTE * Fix fcvt.s.bf16 NaN box checking * Avoid infinite delay of async xmit function * Device tree reg cleanups * Add Kunminghu CPU and platform * Fix missing exit TB flow for ldff_trans * Fix migration failure when aia is configured as aplic-imsic * Fix MEPC/SEPC bit masking for IALIGN * Add a property to set vill bit on reserved usage of vsetvli instruction * Add Svrsw60t59b extension support # -----BEGIN PGP SIGNATURE----- # # iQIzBAABCgAdFiEEaukCtqfKh31tZZKWr3yVEwxTgBMFAmhntt4ACgkQr3yVEwxT # gBMaCQ/9E+LeRY59nz3K3XXUw6XLBfaDECXbKzIn0GM1yXeWTX4dB2h2hoGWdu3R # CRPxWHECN7CeJhd2J23eLfOi+fTUeppJBeR7TcGyoXVC+y0knZv/clQ3OvMFYcgV # xjzzu1yipQlXwY+kmDZ6qL5up/Q+faw7tRaePZaJheRGYpVRnjoKUZq5fe4Ug4RU # Xg6Di86eYyk+Jo0g2exvtzy1rX2eBp7Hz200wWiH5Z1B+3NzgMUHrHuJfNAz8zAt # n8uvruvaLGGtWcQJauRXlAELR6k9tmkfq1Mbqf3FK6muaQCtFD7PXXnjL/rU/z20 # hhxj0psOhBJLd0W5wQ3vLnDf6Wve9zmUdTR9kI0Kt3xUUdfeBuzKcU06F/G8wEsZ # 2sIYQqt0mxoJboY2lpje7TO4H9gvAf76WBOV10FV2gWsqWu2rZQ6herdq3YZYkHX # purUTgyjHn4jl2Y3Kzj0Gq1SHo0yaA/sD6xNR8X+JqljSruDxtOFU7wkKBbewoIg # OSfwemjRUVsPQZ958042ntwJt81v1604Oky8JSFr5eCFx/aoLJ1vDYh7BKZAogNH # uB/YigGq9+/MVzqJpZI+kZkd+1nzaizeL0FUPRTq0jFA2u+vc3J3svQ/jNXDH2c+ # 5nGuhbkvT0ptmVMBqFV2vjPh6+ScR8t03wHdQ4PmDoXC3o9zbbU= # =CfRy # -----END PGP SIGNATURE----- # gpg: Signature made Fri 04 Jul 2025 07:11:26 EDT # gpg: using RSA key 6AE902B6A7CA877D6D659296AF7C95130C538013 # gpg: Good signature from "Alistair Francis <alistair@alistair23.me>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 6AE9 02B6 A7CA 877D 6D65 9296 AF7C 9513 0C53 8013 * tag 'pull-riscv-to-apply-20250704' of https://github.com/alistair23/qemu: (40 commits) target: riscv: Add Svrsw60t59b extension support target/riscv: Add a property to set vill bit on reserved usage of vsetvli instruction tests/tcg/riscv64: Add test for MEPC bit masking target/riscv: Fix MEPC/SEPC bit masking for IALIGN migration: Fix migration failure when aia is configured as aplic-imsic target/riscv: rvv: Fix missing exit TB flow for ldff_trans hw/riscv: Initial support for BOSC's Xiangshan Kunminghu FPGA prototype target/riscv: Add BOSC's Xiangshan Kunminghu CPU hw/riscv/virt: Use setprop_sized_cells for pcie hw/riscv/virt: Use setprop_sized_cells for iommu hw/riscv/virt: Use setprop_sized_cells for rtc hw/riscv/virt: Use setprop_sized_cells for uart hw/riscv/virt: Use setprop_sized_cells for reset hw/riscv/virt: Use setprop_sized_cells for virtio hw/riscv/virt: Use setprop_sized_cells for plic hw/riscv/virt: Use setprop_sized_cells for aclint hw/riscv/virt: Use setprop_sized_cells for aplic hw/riscv/virt: Use setprop_sized_cells for memory hw/riscv/virt: Use setprop_sized_cells for clint hw/riscv/virt: Fix clint base address type ... Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
| * tests/tcg/riscv64: Add test for MEPC bit maskingCharalampos Mitrodimas2025-07-042-0/+77
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a regression test to verify that MEPC properly masks the lower bits when an address with mode bits is written to it, as required by the RISC-V Privileged Architecture specification. The test sets STVEC to an address with bit 0 set (vectored mode), triggers an illegal instruction exception, copies STVEC to MEPC in the trap handler, and verifies that MEPC masks bits [1:0] correctly for IALIGN=32. Without the fix, MEPC retains the mode bits (returns non-zero/FAIL). With the fix, MEPC clears bits [1:0] (returns 0/PASS). Signed-off-by: Charalampos Mitrodimas <charmitro@posteo.net> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Message-ID: <20250703182157.281320-3-charmitro@posteo.net> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
| * target/riscv/cpu.c: add 'ssstrict' to riscv, isaDaniel Henrique Barboza2025-07-041-0/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 'ssstrict' is a RVA23 profile-defined extension defined as follows: "No non-conforming extensions are present. Attempts to execute unimplemented opcodes or access unimplemented CSRs in the standard or reserved encoding spaces raises an illegal instruction exception that results in a contained trap to the supervisor-mode trap handler." In short, we need to throw an exception when accessing unimplemented CSRs or opcodes. We do that, so let's advertise it. Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Message-ID: <20250529202315.1684198-3-dbarboza@ventanamicro.com> Message-ID: <20250604174329.1147549-3-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
| * target/riscv/cpu.c: add 'sdtrig' in riscv,isaDaniel Henrique Barboza2025-07-041-0/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | We have support for sdtrig for awhile but we are not advertising it. It is enabled by default via the 'debug' flag. Use the same flag to also advertise sdtrig. Add an exception in disable_priv_spec_isa_exts() to avoid spamming warnings for 'sdtrig' for vendor CPUs like sifive_u. Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20250604174329.1147549-2-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
* | Merge tag 'accel-20250704' of https://github.com/philmd/qemu into stagingStefan Hajnoczi2025-07-041-1/+0
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Accelerators patches - Generic API consolidation, cleanups (dead code removal, documentation added) - Remove monitor TCG 'info opcount' and @x-query-opcount - Have HVF / NVMM / WHPX use generic CPUState::vcpu_dirty field - Expose nvmm_enabled() and whpx_enabled() to common code - Have hmp_info_registers() dump vector registers # -----BEGIN PGP SIGNATURE----- # # iQIzBAABCAAdFiEE+qvnXhKRciHc/Wuy4+MsLN6twN4FAmhnql4ACgkQ4+MsLN6t # wN6Lfg//R4h6dyAg02hyopwb/DSI97hAsD9kap15ro1qszYrIOkJcEPoE37HDi6d # O0Ls+8NPpJcnMwdghHvVaRGoIH2OY5ogXKo6UK1BbOn8iAGxRrT/IPVCyFbPmQoe # Bk78Z/wne/YgCXiW4HGHSJO5sL04AQqcFYnwjisHHf3Ox8RR85LbhWqthZluta4i # a/Y8W5UO7jfwhAl1/Zb2cU+Rv75I6xcaLQAfmbt4j+wHP52I2cjLpIYo4sCn+ULJ # AVX4q4MKrkDrr6CYPXxdGJzYEzVn9evynVcQoRzL6bLZFMpa284AzVd3kQg9NWAb # p1hvKJTA57q4XDoD50qVGLhP207VVSUcdm0r2ZJA2jag5ddoT+x2talz8/f6In1b # 7BrSM/pla8x9KvTne/ko0wSL0o2dOWyig8mBxARLZWPxk+LBVs1PBZfvn+3j1pYA # rWV25Ht4QJlUYMbe3NvEIomsVThKg8Fh3b4mEuyPM+LZ1brgmhrzJG1SF+G4fH8A # aig/RVqgNHtajSnG4A723k2/QzlvnAiT7E3dKB5FogjTcVzFRaWFKsUb4ORqsCAz # c/AheCJY4PP3pAnb0ODISSVviXwAXqCLbtZhDGhHNYl3C69EyGPPMiVxCaIxKDxU # bF7AIYhRTTMyNSbnkcRS3UDO/gZS7x5/K+/YAM9akQEYADIodYM= # =Vb39 # -----END PGP SIGNATURE----- # gpg: Signature made Fri 04 Jul 2025 06:18:06 EDT # gpg: using RSA key FAABE75E12917221DCFD6BB2E3E32C2CDEADC0DE # gpg: Good signature from "Philippe Mathieu-Daudé (F4BUG) <f4bug@amsat.org>" [full] # Primary key fingerprint: FAAB E75E 1291 7221 DCFD 6BB2 E3E3 2C2C DEAD C0DE * tag 'accel-20250704' of https://github.com/philmd/qemu: (31 commits) MAINTAINERS: Add me as reviewer of overall accelerators section monitor/hmp-cmds-target: add CPU_DUMP_VPU in hmp_info_registers() accel: Pass AccelState argument to gdbstub_supported_sstep_flags() accel: Remove unused MachineState argument of AccelClass::setup_post() accel: Directly pass AccelState argument to AccelClass::has_memory() accel/kvm: Directly pass KVMState argument to do_kvm_create_vm() accel/kvm: Prefer local AccelState over global MachineState::accel accel/tcg: Prefer local AccelState over global current_accel() accel: Propagate AccelState to AccelClass::init_machine() accel: Keep reference to AccelOpsClass in AccelClass accel: Expose and register generic_handle_interrupt() accel/dummy: Extract 'dummy-cpus.h' header from 'system/cpus.h' accel/whpx: Expose whpx_enabled() to common code accel/nvmm: Expose nvmm_enabled() to common code accel/system: Document cpu_synchronize_state_post_init/reset() accel/system: Document cpu_synchronize_state() accel/kvm: Remove kvm_cpu_synchronize_state() stub accel/whpx: Replace @dirty field by generic CPUState::vcpu_dirty field accel/nvmm: Replace @dirty field by generic CPUState::vcpu_dirty field accel/hvf: Replace @dirty field by generic CPUState::vcpu_dirty field ... Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
| * | accel/tcg: Remove 'info opcount' and @x-query-opcountPhilippe Mathieu-Daudé2025-07-041-1/+0
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Since commit 1b65b4f54c7 ("accel/tcg: remove CONFIG_PROFILER", released with QEMU v8.1.0) we get pointless output: (qemu) info opcount [TCG profiler not compiled] Remove that unstable and unuseful command. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Acked-by: Dr. David Alan Gilbert <dave@treblig.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Xiaoyao Li <xiaoyao.li@intel.com> Reviewed-by: Markus Armbruster <armbru@redhat.com> Reviewed-by: Zhao Liu <zhao1.liu@intel.com> Message-Id: <20250703173248.44995-8-philmd@linaro.org>
* | tests/functional: Add gb200 testsEd Tanous2025-07-033-2/+35
| | | | | | | | | | | | | | | | | | | | | | | | To support the newly added gb200 machine, add appropriate tests and extend do_test_arm_aspeed_openbmc() to support the hostname of this new system: "gb200nvl-obmc". Signed-off-by: Ed Tanous <etanous@nvidia.com> Reviewed-by: Cédric Le Goater <clg@redhat.com> Link: https://lore.kernel.org/qemu-devel/20250703144249.3348879-5-etanous@nvidia.com [ clg: Adjust commit log to document do_test_arm_aspeed_openbmc() change ] Signed-off-by: Cédric Le Goater <clg@redhat.com>
* | tests/qtest: Add test for ASPEED SCUTan Siewert2025-07-032-0/+232
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds basic tests for the ASPEED System Control Unit (SCU) and its protection mechanism on the AST2500 and AST2600 platforms. The tests verify: - That SCU protection registers can be unlocked and locked again - That modifying the primary protection register on AST2600 also affects the secondary one - That writes to protected SCU registers are blocked unless protection registers are unlocked explicitly These tests ensure proper emulation of hardware locking behaviour and help catch regressions in SCU access logic. Signed-off-by: Tan Siewert <tan@siewert.io> Reviewed-by: Cédric Le Goater <clg@redhat.com> Link: https://lore.kernel.org/qemu-devel/20250630112646.74944-1-tan@siewert.io [ clg: Reordered file list in meson.build ] Signed-off-by: Cédric Le Goater <clg@redhat.com>
* | hw/arm/aspeed: add Catalina machine typePatrick Williams2025-07-032-0/+27
|/ | | | | | | | | | | | | | | | | | | | | Add the 'catalina-bmc' machine type based on the kernel DTS[1] as of 6.16-rc2. The i2c model is as complete as the current QEMU models support, but in some cases I substituted devices that are close enough for present functionality. Strap registers are were verified with hardware. This has been tested with an openbmc image built from [2]. Add a functional test in line with Bletchley, pointing at an image obtained from the OpenBMC Jenkins server. [1]: https://github.com/torvalds/linux/blob/v6.16-rc2/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-catalina.dts [2]: https://github.com/openbmc/openbmc/commit/5bc73ec261f981d5e586bda5ac78eb0cbd5f92b0 Signed-off-by: Patrick Williams <patrick@stwcx.xyz> Reviewed-by: Cédric Le Goater <clg@redhat.com> Link: https://lore.kernel.org/qemu-devel/20250619151458.2831859-1-patrick@stwcx.xyz Signed-off-by: Cédric Le Goater <clg@redhat.com>
* Merge tag 'pull-request-2025-07-02' of https://gitlab.com/thuth/qemu into ↵Stefan Hajnoczi2025-07-032-5/+5
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | staging * Fix file names of renamed files in comments and MAINTAINERS * Fix the "deprecated props" in QOM on s390x * Fix URL of the aarch64_sbsaref_freebsd functional test * Fix some trouble with trible # -----BEGIN PGP SIGNATURE----- # # iQJFBAABCAAvFiEEJ7iIR+7gJQEY8+q5LtnXdP5wLbUFAmhlZckRHHRodXRoQHJl # ZGhhdC5jb20ACgkQLtnXdP5wLbVIZhAAltzQ9+lZYa0A5NcgbFlVSmL/E6qDIMXG # AJcNul3dgrIVcCrxN17dBmU4ftemjQCpcw7I4fL0G0CrAMdB9Yp991tis1SwycNX # HEDY8THEE7EiOEKxBHtUFo8JbsnT+lcCwNnpvu6RXwnTN4TjT386OwBSeKv4mhHt # LFoUnX5yZqJQD1bzcrUeo+OBoXrnMkeJRuOTFXval1AGBT4q0G5mMtAcj93gONNe # hKdXhYst4XYLZIe2TJAdsbKs5Ics5UZ9rkSIC8tw1drt+iueSSSHNoPsg2AP8Ueg # iqElX3tzzb/P7QF/LWIfu55WLMbP2C2l6Pb37sdZf8Y1QpRaA/6fxQrNRoVLYfdP # 2Gqtxd8Ynn74LUxOpW+gi90mmrZpIL+M06Al0bzpI+KmWOaZxpBd0E3r5BIO1Ghb # /7XIn9svlVpBXd5V3M7Myg1BKAlJJ6GtuMMDBv8Yym6bTD+bdjGk28k/uvt6BSpq # qiMVjKrmmAO4zBkj3OZUKYoqkktf6mjso0xjXxkI2GTQ44dgvXXluwHF8F5LzBPz # y2X+KGhf/vfXqP7cAGpmFH3SjDqngdqvuBT/pDO/VWRUhyz8lM6DyPsdVhS7KrXl # QByt4FkCzYS+o9kc2Hlobj+ujjEPG+1ffSDDweioYYygsZny+8GBgD5D31e5cPsP # 9/Uc75aJD88= # =SEr8 # -----END PGP SIGNATURE----- # gpg: Signature made Wed 02 Jul 2025 13:00:57 EDT # gpg: using RSA key 27B88847EEE0250118F3EAB92ED9D774FE702DB5 # gpg: issuer "thuth@redhat.com" # gpg: Good signature from "Thomas Huth <th.huth@gmx.de>" [full] # gpg: aka "Thomas Huth <thuth@redhat.com>" [full] # gpg: aka "Thomas Huth <huth@tuxfamily.org>" [full] # gpg: aka "Thomas Huth <th.huth@posteo.de>" [unknown] # Primary key fingerprint: 27B8 8847 EEE0 2501 18F3 EAB9 2ED9 D774 FE70 2DB5 * tag 'pull-request-2025-07-02' of https://gitlab.com/thuth/qemu: tests/functional/test_aarch64_sbsaref_freebsd: Fix the URL of the ISO image target/s390x: A fix for the trouble with tribles target/s390x: set has_deprecated_props flag MAINTAINERS: fix paths for relocated files treewide: fix paths for relocated files in comments treewide: update docs file extensions (.txt -> .rst) in comments MAINTAINERS: fix VMware filename typo (vwm -> vmw) MAINTAINERS: fix vendor capitalization (Vmware -> VMware) MAINTAINERS: update docs file extensions (.txt -> .rst) Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
| * tests/functional/test_aarch64_sbsaref_freebsd: Fix the URL of the ISO imageThomas Huth2025-07-021-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | The original image has been removed from the server, so the test currently fails if it has to fetch the asset, but we can still download the ISO from the archive server. While we're at it, prefer the XZ compressed image, it's much smaller and thus the download should be faster. Message-ID: <20250701105809.366180-1-thuth@redhat.com> Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
| * treewide: update docs file extensions (.txt -> .rst) in commentsSean Wei2025-07-021-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Several source comments still refer to docs with the old .txt extension that were previously converted to reStructuredText. Update these references to use the correct .rst extensions to maintain accurate in-tree documentation pointers. No functional changes. Related commits: 50f8174c5c1 (Jul 2021): docs/specs/acpi_nvdimm: Convert to rST f054eb1c920 (Jul 2021): docs/specs/acpi_pci_hotplug: Convert to rST 912fb3678b8 (Sep 2023): docs/specs/vmgenid: Convert to rST bb1cff6ee04 (Sep 2023): docs/specs/ivshmem-spec: Convert to rST 55ff468f781 (Jan 2022): docs: Rename ppc-spapr-hotplug.txt to .rst Signed-off-by: Sean Wei <me@sean.taipei> Message-ID: <20250616.qemu.relocated.05@sean.taipei> Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Harsh Prateek Bora <harshpb@linux.ibm.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
* | Merge tag 'pull-10.1-maintainer-june-2025-020725-1' of ↵Stefan Hajnoczi2025-07-038-9/+406
|\ \ | |/ |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | https://gitlab.com/stsquad/qemu into staging Maintainer updates for June (gitlab, semihosting, plugins, virtio-gpu) - mark s390x runner system tests as allow_fail - build semihosting once - add register write support to plugins - add virtual memory write support to plugins - add harder memory read/write support to plugins - add patcher plugin and tests - re-stock virtio-gpu MAINTAINERS - fix context init for Venus fences * tag 'pull-10.1-maintainer-june-2025-020725-1' of https://gitlab.com/stsquad/qemu: virtio-gpu: support context init multiple timeline MAINTAINERS: add Akihiko and Dmitry as reviewers MAINTAINERS: add myself to virtio-gpu for Odd Fixes plugins: Update plugin version and add notes plugins: Add patcher plugin and test tests/tcg: Remove copy-pasted notes and from i386 and add x86_64 system tests to tests plugins: Add memory hardware address read/write API plugins: Add memory virtual address write API plugins: Add enforcement of QEMU_PLUGIN_CB flags in register R/W callbacks plugins: Add register write API gdbstub: Expose gdb_write_register function to consumers of gdbstub semihosting/uaccess: Compile once semihosting/uaccess: Remove uses of target_ulong type tests/functional: Add PCI hotplug test for aarch64 gitlab: mark s390x-system to allow failures Conflicts: tests/functional/meson.build Context conflict with commit 7bc86ccbb59f ("tests/functional: test device passthrough on aarch64"), keep both changes to tests_aarch64_system_thorough[].
| * plugins: Add patcher plugin and testRowan Hart2025-07-026-2/+328
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds a plugin that exercises the virtual and hardware memory read-write API functions added in a previous patch. The plugin takes a target and patch byte sequence, and will overwrite any instruction matching the target byte sequence with the patch. Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Rowan Hart <rowanbhart@gmail.com> Message-ID: <20250624175351.440780-8-rowanbhart@gmail.com> [AJB: tweak Makefile, use uintptr_t for pointer stuffing] Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-ID: <20250627112512.1880708-12-alex.bennee@linaro.org>
| * tests/tcg: Remove copy-pasted notes and from i386 and add x86_64 system ↵Rowan Hart2025-07-021-7/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | tests to tests The x86_64-softmmu Makefile seems to have been copy-pasted from the i386 Makefile at some point in the past. Cleaning up a vestigial unused variable and removing some outdated comments. Signed-off-by: Rowan Hart <rowanbhart@gmail.com> Message-ID: <20250624175351.440780-7-rowanbhart@gmail.com> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-ID: <20250627112512.1880708-11-alex.bennee@linaro.org>
| * tests/functional: Add PCI hotplug test for aarch64Gustavo Romero2025-07-022-0/+73
| | | | | | | | | | | | | | | | | | | | | | | | | | Add a functional test, aarch64_hotplug_pci, to exercise PCI hotplug and hot-unplug on arm64. Signed-off-by: Gustavo Romero <gustavo.romero@linaro.org> Reviewed-by: Daniel P. Berrangé <berrange@redhat.com> Acked-by: Thomas Huth <thuth@redhat.com> Message-ID: <20250528203137.1654964-1-gustavo.romero@linaro.org> [AJB: trimmed boilerplate for checkpatch, simplified invocations] Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-ID: <20250627112512.1880708-3-alex.bennee@linaro.org>
* | tests/functional: test device passthrough on aarch64Pierrick Bouvier2025-07-012-0/+144
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This test allows to document and exercise device passthrough, using a nested virtual machine setup. Two disks are generated and passed to the VM, and their content is compared to original images. Guest and nested guests commands are executed through two scripts, and init used in both system is configured to trigger a kernel panic in case any command fails. This is more reliable and readable than executing all commands through prompt injection and trying to guess what failed. Initially, this test was supposed to test smmuv3 nested emulation (combining both stages of translation), but I could not find any setup (kernel + vmm) able to do the passthrough correctly, despite several tries. Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Message-id: 20250627200222.5172-1-pierrick.bouvier@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* | tests/functional: Expand Aarch64 SMMU tests to run on HVF acceleratorPhilippe Mathieu-Daudé2025-07-011-3/+9
| | | | | | | | | | | | | | | | Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-id: 20250623121845.7214-27-philmd@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* | tests/functional: Add hvf_available() helperPeter Maydell2025-07-011-2/+4
| | | | | | | | | | | | | | | | Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Message-id: 20250623121845.7214-26-philmd@linaro.org [PMM: tweaks to satisfy the python linter CI job] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* | tests/functional: Require TCG to run Aarch64 imx8mp-evk testPhilippe Mathieu-Daudé2025-07-011-0/+1
| | | | | | | | | | | | | | | | | | | | The imx8mp-evk machine can only run with the TCG accelerator. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Message-id: 20250623121845.7214-25-philmd@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* | tests/functional: Restrict nested Aarch64 Xen test to TCGPhilippe Mathieu-Daudé2025-07-011-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently QEMU only support accelerating EL0 and EL1, so features requiring EL2 (like virtualization) or EL3 must be emulated with TCG. On macOS this test fails: qemu-system-aarch64: mach-virt: HVF does not support providing Virtualization extensions to the guest CPU Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20250623121845.7214-24-philmd@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* | tests/functional: Set sbsa-ref machine type in each test functionPhilippe Mathieu-Daudé2025-07-013-4/+7
| | | | | | | | | | | | | | | | | | | | | | fetch_firmware() is only about fetching firmware. Set the machine type and its default console in test_sbsaref_edk2_firmware(). Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@oss.qualcomm.com> Message-id: 20250623121845.7214-23-philmd@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* | qtest/bios-tables-test: Update blobs for its=off test on aarch64Gustavo Romero2025-07-013-2/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Update blobs for the its=off test on aarch64 after fix. Basically, all structs related to ITS are gone in MADT and IORT tables after the fix (previously ITS was not properly disabled when "its=off" option was passed to the machine). MADT diff: [000h 0000 4] Signature : "APIC" [Multiple APIC Description Table (MADT)] -[004h 0004 4] Table Length : 000000B8 +[004h 0004 4] Table Length : 000000A4 [008h 0008 1] Revision : 04 -[009h 0009 1] Checksum : C1 +[009h 0009 1] Checksum : 08 [00Ah 0010 6] Oem ID : "BOCHS " [010h 0016 8] Oem Table ID : "BXPC " [018h 0024 4] Oem Revision : 00000001 [01Ch 0028 4] Asl Compiler ID : "BXPC" [020h 0032 4] Asl Compiler Revision : 00000001 [024h 0036 4] Local Apic Address : 00000000 [028h 0040 4] Flags (decoded below) : 00000000 PC-AT Compatibility : 0 [02Ch 0044 1] Subtable Type : 0C [Generic Interrupt Distributor] [02Dh 0045 1] Length : 18 [02Eh 0046 2] Reserved : 0000 [030h 0048 4] Local GIC Hardware ID : 00000000 [034h 0052 8] Base Address : 0000000008000000 [03Ch 0060 4] Interrupt Base : 00000000 @@ -48,37 +48,29 @@ [064h 0100 8] Base Address : 0000000000000000 [06Ch 0108 8] Virtual GIC Base Address : 0000000000000000 [074h 0116 8] Hypervisor GIC Base Address : 0000000000000000 [07Ch 0124 4] Virtual GIC Interrupt : 00000000 [080h 0128 8] Redistributor Base Address : 0000000000000000 [088h 0136 8] ARM MPIDR : 0000000000000000 [090h 0144 1] Efficiency Class : 00 [091h 0145 1] Reserved : 00 [092h 0146 2] SPE Overflow Interrupt : 0000 [094h 0148 1] Subtable Type : 0E [Generic Interrupt Redistributor] [095h 0149 1] Length : 10 [096h 0150 2] Reserved : 0000 [098h 0152 8] Base Address : 00000000080A0000 [0A0h 0160 4] Length : 00F60000 -[0A4h 0164 1] Subtable Type : 0F [Generic Interrupt Translator] -[0A5h 0165 1] Length : 14 -[0A6h 0166 2] Reserved : 0000 -[0A8h 0168 4] Translation ID : 00000000 -[0ACh 0172 8] Base Address : 0000000008080000 -[0B4h 0180 4] Reserved : 00000000 IORT diff: [000h 0000 4] Signature : "IORT" [IO Remapping Table] -[004h 0004 4] Table Length : 000000EC +[004h 0004 4] Table Length : 000000AC [008h 0008 1] Revision : 03 -[009h 0009 1] Checksum : 57 +[009h 0009 1] Checksum : 97 [00Ah 0010 6] Oem ID : "BOCHS " [010h 0016 8] Oem Table ID : "BXPC " [018h 0024 4] Oem Revision : 00000001 [01Ch 0028 4] Asl Compiler ID : "BXPC" [020h 0032 4] Asl Compiler Revision : 00000001 -[024h 0036 4] Node Count : 00000003 +[024h 0036 4] Node Count : 00000002 [028h 0040 4] Node Offset : 00000030 [02Ch 0044 4] Reserved : 00000000 -[030h 0048 1] Type : 00 -[031h 0049 2] Length : 0018 -[033h 0051 1] Revision : 01 +[030h 0048 1] Type : 04 +[031h 0049 2] Length : 0044 +[033h 0051 1] Revision : 04 [034h 0052 4] Reserved : 00000000 [038h 0056 4] Mapping Count : 00000000 [03Ch 0060 4] Mapping Offset : 00000000 -[040h 0064 4] ItsCount : 00000001 -[044h 0068 4] Identifiers : 00000000 - -[048h 0072 1] Type : 04 -[049h 0073 2] Length : 0058 -[04Bh 0075 1] Revision : 04 -[04Ch 0076 4] Reserved : 00000001 -[050h 0080 4] Mapping Count : 00000001 -[054h 0084 4] Mapping Offset : 00000044 - -[058h 0088 8] Base Address : 0000000009050000 -[060h 0096 4] Flags (decoded below) : 00000001 +[040h 0064 8] Base Address : 0000000009050000 +[048h 0072 4] Flags (decoded below) : 00000001 COHACC Override : 1 HTTU Override : 0 Proximity Domain Valid : 0 -[064h 0100 4] Reserved : 00000000 -[068h 0104 8] VATOS Address : 0000000000000000 -[070h 0112 4] Model : 00000000 -[074h 0116 4] Event GSIV : 0000006A -[078h 0120 4] PRI GSIV : 0000006B -[07Ch 0124 4] GERR GSIV : 0000006D -[080h 0128 4] Sync GSIV : 0000006C -[084h 0132 4] Proximity Domain : 00000000 -[088h 0136 4] Device ID Mapping Index : 00000000 - -[08Ch 0140 4] Input base : 00000000 -[090h 0144 4] ID Count : 0000FFFF -[094h 0148 4] Output Base : 00000000 -[098h 0152 4] Output Reference : 00000030 -[09Ch 0156 4] Flags (decoded below) : 00000000 - Single Mapping : 0 - -[0A0h 0160 1] Type : 02 -[0A1h 0161 2] Length : 004C -[0A3h 0163 1] Revision : 03 -[0A4h 0164 4] Reserved : 00000002 -[0A8h 0168 4] Mapping Count : 00000002 -[0ACh 0172 4] Mapping Offset : 00000024 - -[0B0h 0176 8] Memory Properties : [IORT Memory Access Properties] -[0B0h 0176 4] Cache Coherency : 00000001 -[0B4h 0180 1] Hints (decoded below) : 00 +[04Ch 0076 4] Reserved : 00000000 +[050h 0080 8] VATOS Address : 0000000000000000 +[058h 0088 4] Model : 00000000 +[05Ch 0092 4] Event GSIV : 0000006A +[060h 0096 4] PRI GSIV : 0000006B +[064h 0100 4] GERR GSIV : 0000006D +[068h 0104 4] Sync GSIV : 0000006C +[06Ch 0108 4] Proximity Domain : 00000000 +[070h 0112 4] Device ID Mapping Index : 00000000 + +[074h 0116 1] Type : 02 +[075h 0117 2] Length : 0038 +[077h 0119 1] Revision : 03 +[078h 0120 4] Reserved : 00000001 +[07Ch 0124 4] Mapping Count : 00000001 +[080h 0128 4] Mapping Offset : 00000024 + +[084h 0132 8] Memory Properties : [IORT Memory Access Properties] +[084h 0132 4] Cache Coherency : 00000001 +[088h 0136 1] Hints (decoded below) : 00 Transient : 0 Write Allocate : 0 Read Allocate : 0 Override : 0 -[0B5h 0181 2] Reserved : 0000 -[0B7h 0183 1] Memory Flags (decoded below) : 03 +[089h 0137 2] Reserved : 0000 +[08Bh 0139 1] Memory Flags (decoded below) : 03 Coherency : 1 Device Attribute : 1 -[0B8h 0184 4] ATS Attribute : 00000000 -[0BCh 0188 4] PCI Segment Number : 00000000 -[0C0h 0192 1] Memory Size Limit : 40 -[0C1h 0193 3] Reserved : 000000 - -[0C4h 0196 4] Input base : 00000000 -[0C8h 0200 4] ID Count : 000000FF -[0CCh 0204 4] Output Base : 00000000 -[0D0h 0208 4] Output Reference : 00000048 -[0D4h 0212 4] Flags (decoded below) : 00000000 - Single Mapping : 0 - -[0D8h 0216 4] Input base : 00000100 -[0DCh 0220 4] ID Count : 0000FEFF -[0E0h 0224 4] Output Base : 00000100 -[0E4h 0228 4] Output Reference : 00000030 -[0E8h 0232 4] Flags (decoded below) : 00000000 +[08Ch 0140 4] ATS Attribute : 00000000 +[090h 0144 4] PCI Segment Number : 00000000 +[094h 0148 1] Memory Size Limit : 40 +[095h 0149 3] Reserved : 000000 + +[098h 0152 4] Input base : 00000000 +[09Ch 0156 4] ID Count : 000000FF +[0A0h 0160 4] Output Base : 00000000 +[0A4h 0164 4] Output Reference : 00000030 +[0A8h 0168 4] Flags (decoded below) : 00000000 Single Mapping : 0 Signed-off-by: Gustavo Romero <gustavo.romero@linaro.org> Reviewed-by: Eric Auger <eric.auger@redhat.com> Message-id: 20250628195722.977078-10-gustavo.romero@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* | hw/arm/virt-acpi-build: Fix ACPI IORT and MADT tables when its=offGustavo Romero2025-07-011-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently, the ITS Group nodes in the IORT table and the GIC ITS Struct in the MADT table are always generated, even if GIC ITS is not available on the machine. This commit fixes it by not generating the ITS Group nodes, not mapping any other node to them, and not advertising the GIC ITS in the MADT table, when GIC ITS is not available on the machine. Since the fix changes the MADT and IORT tables, add the blobs for the "its=off" test to the allow list and update them in the next commit. This commit also renames the smmu_idmaps and its_idmaps variables in build_iort() to rc_smmu_idmaps and rc_its_idmaps, respectively, to make it clearer which nodes are involved in the mappings associated with these variables. Reported-by: Udo Steinberg <udo@hypervisor.org> Signed-off-by: Gustavo Romero <gustavo.romero@linaro.org> Message-id: 20250628195722.977078-9-gustavo.romero@linaro.org Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2886 Signed-off-by: Gustavo Romero <gustavo.romero@linaro.org> Co-authored-by: Philippe Mathieu-Daudé <philmd@linaro.org> [PMM: wrapped an overlong comment] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* | qtest/bios-tables-test: Add blobs for its=off test on aarch64Gustavo Romero2025-07-013-2/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add blobs for test_acpi_aarch64_virt_tcg_its_off(), which introduces a new variant, .its_off, that requires variations of the MADT and IORT tables. MADT (aka APIC) diff: +[000h 0000 4] Signature : "APIC" [Multiple APIC Description Table (MADT)] +[004h 0004 4] Table Length : 000000B8 +[008h 0008 1] Revision : 04 +[009h 0009 1] Checksum : C1 +[00Ah 0010 6] Oem ID : "BOCHS " +[010h 0016 8] Oem Table ID : "BXPC " +[018h 0024 4] Oem Revision : 00000001 +[01Ch 0028 4] Asl Compiler ID : "BXPC" +[020h 0032 4] Asl Compiler Revision : 00000001 + +[024h 0036 4] Local Apic Address : 00000000 +[028h 0040 4] Flags (decoded below) : 00000000 + PC-AT Compatibility : 0 + +[02Ch 0044 1] Subtable Type : 0C [Generic Interrupt Distributor] +[02Dh 0045 1] Length : 18 +[02Eh 0046 2] Reserved : 0000 +[030h 0048 4] Local GIC Hardware ID : 00000000 +[034h 0052 8] Base Address : 0000000008000000 +[03Ch 0060 4] Interrupt Base : 00000000 +[040h 0064 1] Version : 03 +[041h 0065 3] Reserved : 000000 + +[044h 0068 1] Subtable Type : 0B [Generic Interrupt Controller] +[045h 0069 1] Length : 50 +[046h 0070 2] Reserved : 0000 +[048h 0072 4] CPU Interface Number : 00000000 +[04Ch 0076 4] Processor UID : 00000000 +[050h 0080 4] Flags (decoded below) : 00000001 + Processor Enabled : 1 + Performance Interrupt Trigger Mode : 0 + Virtual GIC Interrupt Trigger Mode : 0 +[054h 0084 4] Parking Protocol Version : 00000000 +[058h 0088 4] Performance Interrupt : 00000017 +[05Ch 0092 8] Parked Address : 0000000000000000 +[064h 0100 8] Base Address : 0000000000000000 +[06Ch 0108 8] Virtual GIC Base Address : 0000000000000000 +[074h 0116 8] Hypervisor GIC Base Address : 0000000000000000 +[07Ch 0124 4] Virtual GIC Interrupt : 00000000 +[080h 0128 8] Redistributor Base Address : 0000000000000000 +[088h 0136 8] ARM MPIDR : 0000000000000000 +[090h 0144 1] Efficiency Class : 00 +[091h 0145 1] Reserved : 00 +[092h 0146 2] SPE Overflow Interrupt : 0000 + +[094h 0148 1] Subtable Type : 0E [Generic Interrupt Redistributor] +[095h 0149 1] Length : 10 +[096h 0150 2] Reserved : 0000 +[098h 0152 8] Base Address : 00000000080A0000 +[0A0h 0160 4] Length : 00F60000 + +[0A4h 0164 1] Subtable Type : 0F [Generic Interrupt Translator] +[0A5h 0165 1] Length : 14 +[0A6h 0166 2] Reserved : 0000 +[0A8h 0168 4] Translation ID : 00000000 +[0ACh 0172 8] Base Address : 0000000008080000 +[0B4h 0180 4] Reserved : 00000000 IORT diff: +[000h 0000 4] Signature : "IORT" [IO Remapping Table] +[004h 0004 4] Table Length : 000000EC +[008h 0008 1] Revision : 03 +[009h 0009 1] Checksum : 57 +[00Ah 0010 6] Oem ID : "BOCHS " +[010h 0016 8] Oem Table ID : "BXPC " +[018h 0024 4] Oem Revision : 00000001 +[01Ch 0028 4] Asl Compiler ID : "BXPC" +[020h 0032 4] Asl Compiler Revision : 00000001 + +[024h 0036 4] Node Count : 00000003 +[028h 0040 4] Node Offset : 00000030 +[02Ch 0044 4] Reserved : 00000000 + +[030h 0048 1] Type : 00 +[031h 0049 2] Length : 0018 +[033h 0051 1] Revision : 01 +[034h 0052 4] Reserved : 00000000 +[038h 0056 4] Mapping Count : 00000000 +[03Ch 0060 4] Mapping Offset : 00000000 + +[040h 0064 4] ItsCount : 00000001 +[044h 0068 4] Identifiers : 00000000 + +[048h 0072 1] Type : 04 +[049h 0073 2] Length : 0058 +[04Bh 0075 1] Revision : 04 +[04Ch 0076 4] Reserved : 00000001 +[050h 0080 4] Mapping Count : 00000001 +[054h 0084 4] Mapping Offset : 00000044 + +[058h 0088 8] Base Address : 0000000009050000 +[060h 0096 4] Flags (decoded below) : 00000001 + COHACC Override : 1 + HTTU Override : 0 + Proximity Domain Valid : 0 +[064h 0100 4] Reserved : 00000000 +[068h 0104 8] VATOS Address : 0000000000000000 +[070h 0112 4] Model : 00000000 +[074h 0116 4] Event GSIV : 0000006A +[078h 0120 4] PRI GSIV : 0000006B +[07Ch 0124 4] GERR GSIV : 0000006D +[080h 0128 4] Sync GSIV : 0000006C +[084h 0132 4] Proximity Domain : 00000000 +[088h 0136 4] Device ID Mapping Index : 00000000 + +[08Ch 0140 4] Input base : 00000000 +[090h 0144 4] ID Count : 0000FFFF +[094h 0148 4] Output Base : 00000000 +[098h 0152 4] Output Reference : 00000030 +[09Ch 0156 4] Flags (decoded below) : 00000000 + Single Mapping : 0 + +[0A0h 0160 1] Type : 02 +[0A1h 0161 2] Length : 004C +[0A3h 0163 1] Revision : 03 +[0A4h 0164 4] Reserved : 00000002 +[0A8h 0168 4] Mapping Count : 00000002 +[0ACh 0172 4] Mapping Offset : 00000024 + +[0B0h 0176 8] Memory Properties : [IORT Memory Access Properties] +[0B0h 0176 4] Cache Coherency : 00000001 +[0B4h 0180 1] Hints (decoded below) : 00 + Transient : 0 + Write Allocate : 0 + Read Allocate : 0 + Override : 0 +[0B5h 0181 2] Reserved : 0000 +[0B7h 0183 1] Memory Flags (decoded below) : 03 + Coherency : 1 + Device Attribute : 1 +[0B8h 0184 4] ATS Attribute : 00000000 +[0BCh 0188 4] PCI Segment Number : 00000000 +[0C0h 0192 1] Memory Size Limit : 40 +[0C1h 0193 3] Reserved : 000000 + +[0C4h 0196 4] Input base : 00000000 +[0C8h 0200 4] ID Count : 000000FF +[0CCh 0204 4] Output Base : 00000000 +[0D0h 0208 4] Output Reference : 00000048 +[0D4h 0212 4] Flags (decoded below) : 00000000 + Single Mapping : 0 + +[0D8h 0216 4] Input base : 00000100 +[0DCh 0220 4] ID Count : 0000FEFF +[0E0h 0224 4] Output Base : 00000100 +[0E4h 0228 4] Output Reference : 00000030 +[0E8h 0232 4] Flags (decoded below) : 00000000 + Single Mapping : 0 Signed-off-by: Gustavo Romero <gustavo.romero@linaro.org> Reviewed-by: Eric Auger <eric.auger@redhat.com> Message-id: 20250628195722.977078-8-gustavo.romero@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* | qtest/bios-tables-test: Add test for when ITS is off on aarch64Philippe Mathieu-Daudé2025-07-012-0/+23
|/ | | | | | | | | | | | | | | | | | | | | | Arm64 GIC ITS (Interrupt Translation Service) is an optional piece of hardware introduced in GICv3 and, being optional, it can be disabled in QEMU aarch64 VMs that support it using machine option "its=off", like, for instance: "-M virt,its=off". In ACPI, the ITS is advertised, if present, in the MADT (aka APIC) table, while the ID mappings from the Root Complex (RC) and from the SMMU nodes to the ITS Group nodes are described in the IORT table. This new test verifies that when the "its=off" option is passed to the machine the ITS-related data is correctly pruned from the ACPI tables. The new blobs for this test will be added in a following commit. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Gustavo Romero <gustavo.romero@linaro.org> Reviewed-by: Eric Auger <eric.auger@redhat.com> Message-id: 20250628195722.977078-7-gustavo.romero@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* tests/vm: update openbsd image to 7.7Haseung Bong2025-06-261-2/+2
| | | | | | | | | Update tests/vm/openbsd to release 7.7 Signed-off-by: Haseung Bong <hasueng@gmail.com> Reviewed-by: Daniel P. Berrangé <berrange@redhat.com> Message-ID: <20250615003249.310160-1-hasueng@gmail.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
* tests/functional/test_pc_cpu_hotplug_props: Set 'pc' machine type explicitlyThomas Huth2025-06-251-0/+1
| | | | | | | | | | In case the default machine has not been compiled into the QEMU binary, the cpu_hotplug_props test is currently failing. Add a set_machine('pc') here to make sure that the tests are correctly skipped in case the machine is not available. Signed-off-by: Thomas Huth <thuth@redhat.com> Message-ID: <20250606092033.506736-1-thuth@redhat.com>
* tests/migration: Setup pre-listened cpr.sock to remove race-condition.Jaehoon Kim2025-06-231-2/+12
| | | | | | | | | | | | | | | | | | When the source VM attempts to connect to the destination VM's Unix domain socket (cpr.sock) during a cpr-transfer test, race conditions can occur if the socket file isn't ready. This can lead to connection failures when running tests. This patch creates and listens on the socket in advance, and passes the pre-listened FD directly. This avoids timing issues and improves the reliability of CPR tests. Reviewed-by: Jason J. Herne <jjherne@linux.ibm.com> Signed-off-by: Jaehoon Kim <jhkim@linux.ibm.com> Reviewed-by: Steve Sistare <steven.sistare@oracle.com> Link: https://lore.kernel.org/r/20250611205610.147008-2-jhkim@linux.ibm.com [peterx: null-initialize opts_target, per Steve] Signed-off-by: Peter Xu <peterx@redhat.com>
* tests/qtest: Remove migration-helpers.cFabiano Rosas2025-06-231-530/+0
| | | | | | | | | | | | | | Commit 407bc4bf90 ("qapi: Move include/qapi/qmp/ to include/qobject/") brought the migration-helpers.c back by mistake. This file has been replaced with migration/migration-qmp.c and migration/migration-util.c. Fixes: 407bc4bf90 ("qapi: Move include/qapi/qmp/ to include/qobject/") Signed-off-by: Fabiano Rosas <farosas@suse.de> Message-id: 20200310152141.13959-1-peter.maydell@linaro.org Reviewed-by: Markus Armbruster <armbru@redhat.com> Link: https://lore.kernel.org/r/20250523123023.19284-1-farosas@suse.de Signed-off-by: Peter Xu <peterx@redhat.com>
* Merge tag 'tracing-pull-request' of https://gitlab.com/stefanha/qemu into ↵Stefan Hajnoczi2025-06-163-3/+3
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | staging Pull request Oleg's v4 Windows build fix. # -----BEGIN PGP SIGNATURE----- # # iQEzBAABCgAdFiEEhpWov9P5fNqsNXdanKSrs4Grc8gFAmhQUoMACgkQnKSrs4Gr # c8hqAwf9G6aXBWUcF5U1ZGHmoSr4dzR3FrJLR8f693PcqQSzA9qD1JJniQiPMUXN # LpwbhvzZ5gHdheYTWuwdRbuVaynn8agQO5nTXtZqFX2MY7ym7waDbIOv0F3vD3u/ # Y7otRfT6DJMopkxlzf/UZ3qDVkoJlZEWVbhxuVYTBQukO8rAJt6cQNpNvfp68KYP # XB6S4vvrzr931eG9ccyaRLRqm16PD9qhdrslvbJTqfMXR4YJxBiheQjrgatOqN/U # brG01ObXt3o7nsLt0bTttQnGacXryXCr5B86FGhbWy2XCbpb27gwkj7WvcTtD8UN # M10mm7zDraCBSUYsPApu/y80R/BazA== # =y2IV # -----END PGP SIGNATURE----- # gpg: Signature made Mon 16 Jun 2025 13:21:07 EDT # gpg: using RSA key 8695A8BFD3F97CDAAC35775A9CA4ABB381AB73C8 # gpg: Good signature from "Stefan Hajnoczi <stefanha@redhat.com>" [ultimate] # gpg: aka "Stefan Hajnoczi <stefanha@gmail.com>" [ultimate] # Primary key fingerprint: 8695 A8BF D3F9 7CDA AC35 775A 9CA4 ABB3 81AB 73C8 * tag 'tracing-pull-request' of https://gitlab.com/stefanha/qemu: meson: fix Windows build Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
| * meson: fix Windows buildoltolm2025-06-163-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | The build fails on Windows. Replace calls to Unix programs like ´cat´, ´sed´ and ´true´ with calls to ´python´ and wrap calls to ´os.path.relpath´ in try-except because it can fail when the two paths are on different drives. Make sure to convert the Windows paths to Unix paths to prevent warnings in generated files. Signed-off-by: oltolm <oleg.tolmatcev@gmail.com> Message-id: 20250612221521.1109-2-oleg.tolmatcev@gmail.com Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
* | Merge tag 'pull-target-arm-20250616' of ↵Stefan Hajnoczi2025-06-162-0/+48
|\ \ | |/ |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | https://git.linaro.org/people/pmaydell/qemu-arm into staging target-arm queue: * hw/arm/virt: Check bypass iommu is not set for iommu-map DT property * tests/functional: Add a test for the realview-eb-mpcore machine * qemu-options.hx: Fix reversed description of icount sleep behavior * target/arm: Define raw write for PMU CLR registers * docs/interop: convert qed_spec.txt to reStructuredText format * hw/arm: make cpu targeted by arm_load_kernel the primary CPU. * hw/intc/arm_gic: introduce a first-cpu-index property * hw/arm/mps2: Configure the AN500 CPU with 16 MPU regions * linux-user/arm: Fix return value of SYS_cacheflush # -----BEGIN PGP SIGNATURE----- # # iQJNBAABCAA3FiEE4aXFk81BneKOgxXPPCUl7RQ2DN4FAmhQJLgZHHBldGVyLm1h # eWRlbGxAbGluYXJvLm9yZwAKCRA8JSXtFDYM3k+8EACPyIt6Tie/0kuTXG85r06P # Iqlp59ENb4HNB43bOBlLqNNJydx1GplKnDeDVsz4MyjhtFTZ3xvY+52IbDOgb3YL # 66uJfu1VgdnYoKOpfi3hEr9PM9QxNkENF/3+Fokn+X5tHzhNY4eo/RREQfz2tKJ5 # aKKvzmcZNYwqFLn8TKCNaAfjmqrdwVpuF+rt//4hGULZGwatt8qmlsXWLstozTAz # SPx0utJfvblHj6a+49e0lXaL+xU5yho2J01OiNHrIGtED5Oq2Wmj/q0SV3qPiLDH # hchuDXT71shE2JYoVeINaQpjRWzQNSPXvnEl9SyJ3Ghzop3sOZqE2iPVslvO0l5R # rfrbR2rLnGcRPOwgntGnSMHiW+DH9ldhMUp7UvhlU3/5MJmWX2jpDfZJPsmmdyFH # Evrf64yMO7JlLMQSMkTISZampz8aUgdlgrmQDJ4kGpdkp3GWqLE93eQGHCU16k2j # PzjGxCIeOED4HEeGG3GrPTf0P1dy8WKla2z8ou2ANLqofrKpwFHTuGRl77ETn/bD # 8c11hdS+uJ4Sx/efVPXWQhjCPNwLJL+DlCW0kKbGfTmiBdlcPPzPbrzmPNinVzJs # luSGFzNit7Invfn0KZhy3l0iucMWGPdMDqN0B15RA5fFssdkuxZga5H2kOqCswOe # 3hHo1s5PUbg+x1JAvQvi5g== # =9lWk # -----END PGP SIGNATURE----- # gpg: Signature made Mon 16 Jun 2025 10:05:44 EDT # gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE # gpg: issuer "peter.maydell@linaro.org" # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [full] # gpg: aka "Peter Maydell <pmaydell@gmail.com>" [full] # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [full] # gpg: aka "Peter Maydell <peter@archaic.org.uk>" [unknown] # Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE * tag 'pull-target-arm-20250616' of https://git.linaro.org/people/pmaydell/qemu-arm: linux-user/arm: Fix return value of SYS_cacheflush hw/arm/mps2: Configure the AN500 CPU with 16 MPU regions hw/intc/arm_gic: introduce a first-cpu-index property hw/arm: make cpu targeted by arm_load_kernel the primary CPU. docs/interop: convert qed_spec.txt to reStructuredText format target/arm: Define raw write for PMU CLR registers qemu-options.hx: Fix reversed description of icount sleep behavior tests/functional: Add a test for the realview-eb-mpcore machine hw/arm/virt: Check bypass iommu is not set for iommu-map DT property Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
| * tests/functional: Add a test for the realview-eb-mpcore machineThomas Huth2025-06-122-0/+48
| | | | | | | | | | | | | | | | | | | | Check that we can boot a Linux kernel here and that we can at least send one ping network packet. Signed-off-by: Thomas Huth <thuth@redhat.com> Message-id: 20250603101526.21217-1-thuth@redhat.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* | qga: Add tests for guest-get-load commandKonstantin Kostiuk2025-06-121-0/+17
|/ | | | | | Tested-by: Dehan Meng <demeng@redhat.com> Reviewed-by: Yan Vugenfirer <yvugenfi@redhat.com> Signed-off-by: Konstantin Kostiuk <kkostiuk@redhat.com>
* Merge tag 'pull-request-2025-06-11' of https://gitlab.com/thuth/qemu into ↵Stefan Hajnoczi2025-06-117-9/+108
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | staging * Remove aarch64 job from travis.yml * Remove deprecated s390-ccw-virtio-4.1 machine * Add memlock functional test * Various other small updates and fixes # -----BEGIN PGP SIGNATURE----- # # iQJFBAABCAAvFiEEJ7iIR+7gJQEY8+q5LtnXdP5wLbUFAmhJfHgRHHRodXRoQHJl # ZGhhdC5jb20ACgkQLtnXdP5wLbX/8Q//VCvEW3EKp/r+jDK32rfeuVtGPQfjsJ7u # iDI3OkzhWZOKpU229Nthj2rKGMPl19mBXFMRavRHceO1pW/xYlPNAErMgT9WrU9K # Cy2pYvOGIVK6pZj+qtjcWwG7wHo8mUtgklXXOvH46pXKunRaVc5vJ3ooIvxn96aE # aq6r+U4iW4WHt65OJj35Od6Fdl7eDuAHgFEzPIrb0+ip4NUNIlQBX7Ro/9Aaok5X # u7hDNbaPMqsYQ2lvU6biJEiVRYz+urqjVUbnNPSm//0SEDc+tGYbwa+XVXaGG8ws # URijEu4CTo26zm85ZVIr/b7HW2uzkSqM+phWXh1vDqOeyQq7a9k5MQ8K01reHBHp # XvJbfg5hYrKbeJIn9QFTwJ+1UPh7fkR0MUj0LCfTEyO5U42OM6TA0R3JyebVx3eG # YpjxUGUZWHLc/5OJFzthIqy0oG/PKuw1fcWTIgiojFQEAd4XIDsYyV66utONe/hJ # on1Tn3eniw0L8k2pw6/9Hwnwufe2U+HG/ZGNyfFWq0nPk0Ccdb1MrMUOryLjG3TK # OGHqGBEINUKkgX7C3ox0my+fYzUQGwi0O+jKqhDEzZP8Ci5Ozcx5mIb0XejqDBXM # IvUqPirXvLFwh0djnisIXIIdDNWYH6TpjyyGLyUj8rPeE2FVyiNBQRT25rNMNdVn # 0zYwfxH7pno= # =Ky62 # -----END PGP SIGNATURE----- # gpg: Signature made Wed 11 Jun 2025 08:54:16 EDT # gpg: using RSA key 27B88847EEE0250118F3EAB92ED9D774FE702DB5 # gpg: issuer "thuth@redhat.com" # gpg: Good signature from "Thomas Huth <th.huth@gmx.de>" [full] # gpg: aka "Thomas Huth <thuth@redhat.com>" [full] # gpg: aka "Thomas Huth <huth@tuxfamily.org>" [full] # gpg: aka "Thomas Huth <th.huth@posteo.de>" [unknown] # Primary key fingerprint: 27B8 8847 EEE0 2501 18F3 EAB9 2ED9 D774 FE70 2DB5 * tag 'pull-request-2025-06-11' of https://gitlab.com/thuth/qemu: scripts/meson-buildoptions: Sort coroutine_backend choices lexicographically MAINTAINERS: Update Akihiko Odaki's affiliation MAINTAINERS: Update the paths to the testing documentation files tests/vm/README: fix documentation path in tests/vm/README tests/functional: add memlock tests tests/functional: add skipLockedMemoryTest decorator tests/functional: Speed up the avr_mega2560 test tests/functional: Use the 'none' machine for the VNC test hw/s390x/s390-virtio-ccw: Remove the deprecated 4.1 machine type travis.yml: Remove the aarch64 job Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
| * tests/vm/README: fix documentation path in tests/vm/READMEHaseung Bong2025-06-111-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | The README file in tests/vm/ points to a non-existent file, docs/devel/testing.rst. Update the README to point to docs/devel/testing/main.rst, which now contains information about VM testing. Signed-off-by: Haseung Bong <hasueng@gmail.com> Fixes: ff41da50308 ("docs/devel: Split testing docs from the build docs and move to separate folder") Reviewed-by: Thomas Huth <thuth@redhat.com> Message-ID: <20250607060456.28902-1-hasueng@gmail.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
| * tests/functional: add memlock testsAlexandr Moshkov2025-06-112-0/+80
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add new tests to check the correctness of the `-overcommit memlock` option (possible values: off, on, on-fault) by using `/proc/{qemu_pid}/status` file to check in VmSize, VmRSS and VmLck values: * if `memlock=off`, then VmLck = 0; * if `memlock=on`, then VmLck > 0 and almost all memory is resident; * if `memlock=on-fault`, then VmLck > 0 and only few memory is resident. Signed-off-by: Alexandr Moshkov <dtalexundeer@yandex-team.ru> Message-ID: <20250605065908.299979-3-dtalexundeer@yandex-team.ru> Signed-off-by: Thomas Huth <thuth@redhat.com>