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* tests/tcg/s390x: Test modifying code using the MVC instructionIlya Leoshkevich2025-01-302-0/+83
| | | | | | | | | Add a small test to prevent regressions. Signed-off-by: Ilya Leoshkevich <iii@linux.ibm.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-ID: <20250128001338.11474-2-iii@linux.ibm.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
* tests/functional/test_mips_malta: Fix comment about endianness of the testThomas Huth2025-01-301-1/+1
| | | | | | | | | | This test is for the big endian MIPS target, not for the little endian target. Fixes: 79cb4a14cb6 ("tests/functional: Convert mips32eb 4Kc Malta tests") Message-ID: <20250127184112.108122-1-thuth@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Thomas Huth <thuth@redhat.com>
* tests/functional: Add a ppc64 mac99 testCédric Le Goater2025-01-302-0/+46
| | | | | | | | | | | | | | | | | | The test sequence boots from disk a mac99 machine in 64-bit mode, in which case the CPU is a PPC 970. The buildroot rootfs is built with config : BR2_powerpc64=y BR2_powerpc_970=y and the kernel with the g5 deconfig. Reviewed-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Cédric Le Goater <clg@redhat.com> Message-ID: <20250128212145.1186617-1-clg@redhat.com> [thuth: Adjusted the comment about '-nographic] Signed-off-by: Thomas Huth <thuth@redhat.com>
* tests/functional: Fix the aarch64_tcg_plugins testThomas Huth2025-01-302-6/+10
| | | | | | | | | | | | | | | | | | | | | | Unfortunately, this test had not been added to meson.build, so we did not notice a regression: Looking for 'Kernel panic - not syncing: VFS:' as the indication for the final boot state of the kernel was a bad idea since 'Kernel panic - not syncing' is the default failure message of the LinuxKernelTest class, and since we're now reading the console input byte by byte instead of linewise (see commit cdad03b74f75), the failure now triggers before we fully read the success string. Let's fix this by simply looking for the previous line in the console output instead. Also, replace the call to cancel() - this was only available in the Avocado framework. In the functional framework, we must use skipTest() instead. While we're at it, also fix the TODO here by looking for the exact error and only skip the test if the plugins are not available. Fixes: 3abc545e66 ("tests/functional: Convert the tcg_plugins test") Fixes: cdad03b74f ("tests/functional: rewrite console handling to be bytewise") Message-ID: <20250123083625.1498495-1-thuth@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
* tests/functional: Convert the migration avocado testThomas Huth2025-01-303-135/+132
| | | | | | | | | | | | | | | Now that we've got a find_free_port() function in the functional test framework, we can convert the migration test, too. While the original avocado test was only meant to run on aarch64, ppc64 and x86, we can turn this into a more generic test by now and run it on all architectures that have a machine which ships with a working firmware. To avoid overlapping with the migration qtest, we now also test migration on machines that are not covered by the migration qtest yet. Acked-by: Fabiano Rosas <farosas@suse.de> Message-ID: <20250103074308.463860-1-thuth@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
* tests/functional: Fix broken decorators with lamda functionsThomas Huth2025-01-301-23/+21
| | | | | | | | | | | | The decorators that use a lambda function are currently broken and do not properly skip the test if the condition is not met. Using "return skipUnless(lambda: ...)" does not work as expected. To fix it, rewrite the decorators without lambda, it's simpler that way anyway. Reviewed-by: Daniel P. Berrangé <berrange@redhat.com> Message-ID: <20250122134315.1448794-3-thuth@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
* tests/functional/qemu_test/decorators: Fix bad check for importsThomas Huth2025-01-301-1/+2
| | | | | | | | | | | | | | skipIfMissingImports should use importlib.import_module() for checking whether a module with the name stored in the "impname" variable is available or not, otherwise the code tries to import a module with the name "impname" instead. (This bug hasn't been noticed before since there is another issue with this decorator that will be fixed by the next patch) Suggested-by: Daniel P. Berrangé <berrange@redhat.com> Reviewed-by: Daniel P. Berrangé <berrange@redhat.com> Message-ID: <20250122134315.1448794-2-thuth@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
* Merge tag 'pull-target-arm-20250128-1' of ↵Stefan Hajnoczi2025-01-292-0/+32
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | https://git.linaro.org/people/pmaydell/qemu-arm into staging target-arm queue: * hw/arm: Remove various uses of first_cpu global * hw/char/imx_serial: Fix reset value of UFCR register * hw/char/imx_serial: Update all state before restarting ageing timer * hw/pci-host/designware: Expose MSI IRQ * hw/arm/stellaris: refactoring, cleanup * hw/arm/stellaris: map both I2C controllers * tests/functional: Add a test for the arm microbit machine * target/arm: arm_reset_sve_state() should set FPSR, not FPCR * target/arm: refactorings preparatory to FEAT_AFP implementation * fpu: Rename float_flag_input_denormal to float_flag_input_denormal_flushed * fpu: Rename float_flag_output_denormal to float_flag_output_denormal_flushed * hw/usb/canokey: Fix buffer overflow for OUT packet # -----BEGIN PGP SIGNATURE----- # # iQJNBAABCAA3FiEE4aXFk81BneKOgxXPPCUl7RQ2DN4FAmeZOi0ZHHBldGVyLm1h # eWRlbGxAbGluYXJvLm9yZwAKCRA8JSXtFDYM3sUeEACwDhM4ldn/gVZgVN7nf42a # /CLD/qJx1vqi5bAB5zkY1bSCR9hS2IkhTBoQQH9Ng6ztG1IRpT/tKXDJAemWty70 # XgExdl4yjdwXMQK4JKU9qSfaBTuX7Z8Hz+nA1AnblO/4H+XpVNVJzp8Ee/uWTyEd # BKPBpwqbIXNwUWEqkzDok074Q05rHlhsJD2DsoJTcmtpROhLHLATwQDZGGFuf56H # LVcdx6GRP+/mWEGWLtj19mvaR/2cn4rQf+I1MACZ81nRjQCHbCohNAMr2wFsKg1+ # 2jYk9uHdFoambJ5+mFuC55Efk+QJaP4vDR0Gf3jLloFr+rS/5h3HiUuD8dUWOwFd # mPWXsjwYzqBW2knt1nfq1ByzYWZ8rVQEn5G53dX/eoNXuDGsonZxPnevgmv5kIUc # /W618Jez1nu9RDtNKccobHEtTGlGInJxJ7YzkU7Q6FO80IAqSdV7t9v7uPLJwcnz # nQz+wVzb4oOmwMzn3BpKY7N/S7IZOSy3ASNHj8o4yCHMJT8Ki0/N4bl0k0DLxJ0T # RiNCsV9c7MJfo9a+pbOnu0Lc3SjjropdvHYU+bB7R0mgd8ysN+Tou0dpa+i7tUTu # DHWqs2/+UApHKBiC+DSynPjjRR2aT/5lYFncGaiEVoEQttPLka3SAzgHPVQZs1zD # bxZkEAFktAFGIjU70fYNkg== # =H4p7 # -----END PGP SIGNATURE----- # gpg: Signature made Tue 28 Jan 2025 15:12:29 EST # gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE # gpg: issuer "peter.maydell@linaro.org" # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [full] # gpg: aka "Peter Maydell <pmaydell@gmail.com>" [full] # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [full] # gpg: aka "Peter Maydell <peter@archaic.org.uk>" [unknown] # Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE * tag 'pull-target-arm-20250128-1' of https://git.linaro.org/people/pmaydell/qemu-arm: (36 commits) hw/usb/canokey: Fix buffer overflow for OUT packet target/arm: Use FPST_A64_F16 for halfprec-to-other conversions target/arm: Remove redundant advsimd float16 helpers fpu: Fix a comment in softfloat-types.h fpu: Rename float_flag_output_denormal to float_flag_output_denormal_flushed fpu: Rename float_flag_input_denormal to float_flag_input_denormal_flushed target/arm: Remove now-unused vfp.fp_status_f16 and FPST_FPCR_F16 target/arm: Use FPST_A64_F16 in A64 decoder target/arm: Use FPST_A32_F16 in A32 decoder target/arm: Use fp_status_f16_a64 in AArch64-only helpers target/arm: Use fp_status_f16_a32 in AArch32-only helpers target/arm: Define new fp_status_f16_a32 and fp_status_f16_a64 target/arm: Remove now-unused vfp.fp_status and FPST_FPCR target/arm: Use FPST_A64 in A64 decoder target/arm: Use FPST_A32 in A32 decoder target/arm: Use fp_status_a32 in vfp_cmp helpers target/arm: Use fp_status_a32 in vjvct helper target/arm: Use fp_status_a64 or fp_status_a32 in is_ebf() target/arm: Use vfp.fp_status_a64 in A64-only helper functions target/arm: Define new fp_status_a32 and fp_status_a64 ... Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
| * tests/functional: Add a test for the arm microbit machineThomas Huth2025-01-282-0/+32
| | | | | | | | | | | | | | | | | | | | | | | | We don't have any functional tests for this machine yet, thus let's add a test with a MicroPython binary that is available online (thanks to Joel Stanley for providing it, see: https://www.mail-archive.com/qemu-devel@nongnu.org/msg606064.html ). Signed-off-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-id: 20250124101709.1591761-1-thuth@redhat.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* | test/functional: Update buildroot images to 2024.11Cédric Le Goater2025-01-273-9/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The main changes compared to upstream 2024.11 buildroot are - bumped Linux to version 6.11.11 with a custom config - changed U-Boot to OpenBMC branch for more support - included extra target packages See branch [1] for more details. There is a slight output change when powering off the machine, the console now contains : reboot: Power off not available: System halted Adjust accordingly the expect string in do_test_arm_aspeed_buildroot_poweroff(). [1] https://github.com/legoater/buildroot/commits/aspeed-2024.11 Reviewed-by: Jamin Lin <jamin_lin@aspeedtech.com> Link: https://lore.kernel.org/qemu-devel/20250122070909.1138598-9-clg@redhat.com Signed-off-by: Cédric Le Goater <clg@redhat.com>
* | test/functional: Update the Aspeed aarch64 testCédric Le Goater2025-01-271-5/+5
|/ | | | | | | | | Bumped SDK version to v09.03. v09.04 is available but not yet supported in QEMU. Reviewed-by: Jamin Lin <jamin_lin@aspeedtech.com> Link: https://lore.kernel.org/qemu-devel/20250122070909.1138598-8-clg@redhat.com Signed-off-by: Cédric Le Goater <clg@redhat.com>
* tests/functional: Convert the kvm_xen_guest avocado testThomas Huth2025-01-222-37/+54
| | | | | | | | | | Use the serial console to execute the commands in the guest instead of using ssh since we don't have ssh support in the functional framework yet. Acked-by: David Woodhouse <dwmw@amazon.co.uk> Message-ID: <20250113082516.57894-1-thuth@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
* Merge tag 'pull-riscv-to-apply-20250119-1' of ↵Stefan Hajnoczi2025-01-191-0/+0
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | https://github.com/alistair23/qemu into staging Second RISC-V PR for 10.0 * Reduce the overhead for simple RISC-V vector unit-stride loads and stores * Add V bit to GDB priv reg * Add 'sha' support * Add traces for exceptions in user mode * Update Pointer Masking to Zjpm v1.0 * Add Smrnmi support * Fix timebase-frequency when using KVM acceleration * Add RISC-V Counter delegation ISA extension support * Add support for Smdbltrp and Ssdbltrp extensions * Introduce a translation tag for the IOMMU page table cache * Support Supm and Sspm as part of Zjpm v1.0 * Convert htif debug prints to trace event # -----BEGIN PGP SIGNATURE----- # # iQIzBAABCAAdFiEEaukCtqfKh31tZZKWr3yVEwxTgBMFAmeMUUwACgkQr3yVEwxT # gBNgDQ/+JeqcsbJRX+PZQJEV06tDIJpk+mfaBHUYSGdNkjI9fzowNaxFIEB2vaLt # 4+xAGMnJ4vMcjJyBcPOn1FKAlowM7MsUNITOF9Rstnyriqnj2UsUZ9YBtkuG6gWH # ZHoYEKu7mAZoZw5RRx4TatHDXw7TYfUsrDPrn+x6yeCZTq9ruRTlHkzp2LC725Vq # KTnbWAP7WlqiJaSxB5eIFYT5tYP1Blp0yD358B037C57EU9j5zm2FQdFmVK1+xRF # dFg/urBIzfAjjkCS/t9DmH+S6NgMEut6udUhllk/KUJAzWvsggc4wZZlWjFOJFJY # fIxx3alhY3pcm1PYjFpf15Poz6Pqva/KGjwgZafirKQtPbRSzfRkUwcHOYRTQT9j # abeiB44XPaeIl8Jvw7GLxcWtlJ5NmBrZho+2Z9mIhB/Ix5H3PDgs18Oc/s73P2qQ # JFLRb7cpYy1HbRc0ugvwAmOTY1t6HX8HAtT+3rNhiXpXnj4RW2C/WU1cEqrg8QkM # cTPiy2zHoBhAWt9aDK1Kvbhb1vur3JaF7rk9jeKlriFr87Ly+yPU+8mnEDw40NMR # Tc9nivqmOqqXS5AM9O/W1uzTWzpxIUy7XBy3cuSk0uZCoge4IE2Or7P2Rb2uyaNZ # RkAo/PL2N1cMjP7gB3kLRtYY7FA+nal66KhfbHPRHqj+ZwUAxzs= # =F3IG # -----END PGP SIGNATURE----- # gpg: Signature made Sat 18 Jan 2025 20:11:40 EST # gpg: using RSA key 6AE902B6A7CA877D6D659296AF7C95130C538013 # gpg: Good signature from "Alistair Francis <alistair@alistair23.me>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 6AE9 02B6 A7CA 877D 6D65 9296 AF7C 9513 0C53 8013 * tag 'pull-riscv-to-apply-20250119-1' of https://github.com/alistair23/qemu: (50 commits) hw/char/riscv_htif: Convert HTIF_DEBUG() to trace events target/riscv: Support Supm and Sspm as part of Zjpm v1.0 hw/riscv/riscv-iommu.c: Introduce a translation tag for the page table cache target/riscv: Add Smdbltrp ISA extension enable switch target/riscv: Implement Smdbltrp behavior target/riscv: Implement Smdbltrp sret, mret and mnret behavior target/riscv: Add Smdbltrp CSRs handling target/riscv: Add Ssdbltrp ISA extension enable switch target/riscv: Implement Ssdbltrp exception handling target/riscv: Implement Ssdbltrp sret, mret and mnret behavior target/riscv: Add Ssdbltrp CSRs handling target/riscv: Fix henvcfg potentially containing stale bits target/riscv: Add configuration for S[m|s]csrind, Smcdeleg/Ssccfg target/riscv: Add implied rule for counter delegation extensions target/riscv: Invoke pmu init after feature enable target/riscv: Add counter delegation/configuration support target/riscv: Add select value range check for counter delegation target/riscv: Add counter delegation definitions target/riscv: Add properties for counter delegation ISA extensions target/riscv: Support generic CSR indirect access ... Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
| * target/riscv: add shgatpaDaniel Henrique Barboza2025-01-191-0/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | shgatpa is defined in RVA22 as: "For each supported virtual memory scheme SvNN supported in satp, the corresponding hgatp SvNNx4 mode must be supported. The hgatp mode Bare must also be supported." Claim support for shgatpa since this is always true for TCG. Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20241218114026.1652352-9-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
| * target/riscv: add shvsatpaDaniel Henrique Barboza2025-01-191-0/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | shvsatpa is defined in RVA22 as: "All translation modes supported in satp must be supported in vsatp." This is always true in TCG so let's claim support for it. Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20241218114026.1652352-8-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
| * target/riscv: add shvstvecdDaniel Henrique Barboza2025-01-191-0/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | shvstvecd is defined in RVA22 as: "vstvec.MODE must be capable of holding the value 0 (Direct). When vstvec.MODE=Direct, vstvec.BASE must be capable of holding any valid four-byte-aligned address." This is always true for TCG so let's claim support for it. Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20241218114026.1652352-7-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
| * target/riscv: add shtvalaDaniel Henrique Barboza2025-01-191-0/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | shtvala is described in RVA22 as: "htval must be written with the faulting guest physical address in all circumstances permitted by the ISA." This is the case since commit 3067553993, so claim support for shtvala. Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20241218114026.1652352-6-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
| * target/riscv: add shvstvalaDaniel Henrique Barboza2025-01-191-0/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | shvstvala is defined in RVA22 as: "vstval must be written in all cases described above for stval." By "cases describe above" the doc refer to the description of sstvala: "stval must be written with the faulting virtual address for load, store, and instruction page-fault, access-fault, and misaligned exceptions, and for breakpoint exceptions other than those caused by execution of the EBREAK or C.EBREAK instructions. For virtual-instruction and illegal-instruction exceptions, stval must be written with the faulting instruction." We already have sstvala, and our vstval follows the same rules as stval, so we can claim to support shvstvala too. Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20241218114026.1652352-5-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
| * target/riscv: add shcounterenwDaniel Henrique Barboza2025-01-191-0/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | shcounterenw is defined in RVA22 as: "For any hpmcounter that is not read-only zero, the corresponding bit in hcounteren must be writable." This is always true in TCG so let's claim support for it. Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20241218114026.1652352-4-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
* | Merge tag 'qtest-20250117-pull-request' of https://gitlab.com/farosas/qemu ↵Stefan Hajnoczi2025-01-188-24/+155
|\ \ | |/ |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | into staging Qtest pull request - RISCV CSR test - migration recover changed to OOB - removal of dead code in test-x86-cpuid-compat # -----BEGIN PGP SIGNATURE----- # # iQJEBAABCAAuFiEEqhtIsKIjJqWkw2TPx5jcdBvsMZ0FAmeKbx4QHGZhcm9zYXNA # c3VzZS5kZQAKCRDHmNx0G+wxnRD7D/9v4ovvGn/IwSXjjpOpkjhCSgV8TMi1F61P # hqB5TTCY8yejvT7JauplMUHmcJsVCNx+HF36D+YjxBjqrhQE8vzPRXgcLxHL9RX4 # Kwgdk24kFKADE3gsiys9gOpwRhmtY0/2CT5LvitfJRMxUNPtm0Mr7qM3Z0Taeusu # lxZgIMTBeNakpY5vua8nlLQ4r+/Df6S3TFFAaQ4UYab/T5zHVcjKaySXDlT1QXpp # M+Be21jPxuUYJnKCSxMCUtuY9wkSPcITzJW91V+JxL9STSpsKpnQe10JWDRbwLBt # /am2Jg5f8iFEblCwr5aQRMwXB+e/Y7K4qKPOUalj+weGnCXh9DmWPXnV6qzdZNO8 # sePKoFj1AMtqbVf3iOpDBRkH8dECiDh1jHmflW1grF0BuOwOw8dKYW+i2qz9ZDiW # rKWKfRcZZ059aOCQWqpMC9TGQ8osMC/v6GGJwiPBDLapGjnAm5d1683w4Z1l8tAg # vf9yti2mpzK15PB6doEj/IuZr8WKWFMklizmMMZpXgHIUpjtm3JFKXX/jGHcD3KU # E8F4ns3zPMlq7ncIwc6GADRB3XzEuzzuXAaEO8HMN0fYHevfnFIon749udyBDI/n # a1/CTzTmchItwzgpdvcoiKO6gkg6DO9n08QULCMPSVCtl5KAlz5yuwxWGI/rM6u7 # ixPi8i24oA== # =i4AD # -----END PGP SIGNATURE----- # gpg: Signature made Fri 17 Jan 2025 09:54:22 EST # gpg: using RSA key AA1B48B0A22326A5A4C364CFC798DC741BEC319D # gpg: issuer "farosas@suse.de" # gpg: Good signature from "Fabiano Rosas <farosas@suse.de>" [unknown] # gpg: aka "Fabiano Almeida Rosas <fabiano.rosas@suse.com>" [unknown] # gpg: WARNING: The key's User ID is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: AA1B 48B0 A223 26A5 A4C3 64CF C798 DC74 1BEC 319D * tag 'qtest-20250117-pull-request' of https://gitlab.com/farosas/qemu: tests/qtest/test-x86-cpuid-compat: Remove tests related to pc-i440fx-2.3 tests/qtest/migration: Use out-of-band execution for migrate-recover tests/qtest: Introduce qtest_init_with_env_and_capabilities() tests/qtest: QTest example for RISC-V CSR register target/riscv: Add RISC-V CSR qtest support Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
| * tests/qtest/test-x86-cpuid-compat: Remove tests related to pc-i440fx-2.3Thomas Huth2025-01-171-18/+0
| | | | | | | | | | | | | | | | | | | | | | The pc-i440fx-2.3 machine type has been removed in commit 46a2bd5257 ("hw/i386/pc: Remove deprecated pc-i440fx-2.3 machine") already, so these tests are just dead code by now. Signed-off-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Fabiano Rosas <farosas@suse.de> Link: https://lore.kernel.org/r/20250117102738.59714-2-thuth@redhat.com Signed-off-by: Fabiano Rosas <farosas@suse.de>
| * tests/qtest/migration: Use out-of-band execution for migrate-recoverJuraj Marcin2025-01-173-3/+24
| | | | | | | | | | | | | | | | | | | | | | | | In real use cases, the migrate-recover command requires out-of-band execution, because the thread processing normal commands is blocked by a page fault in the guest memory. With this change, the tests will be closer to real use cases and could help detect regressions and other bugs in migration recovery. Signed-off-by: Juraj Marcin <jmarcin@redhat.com> Reviewed-by: Peter Xu <peterx@redhat.com> Signed-off-by: Fabiano Rosas <farosas@suse.de>
| * tests/qtest: Introduce qtest_init_with_env_and_capabilities()Juraj Marcin2025-01-172-2/+33
| | | | | | | | | | | | | | | | | | | | | | This patch adds a new version of qtest_init_with_env() that allows specifying QMP capabilities that should be enabled during handshake. This is useful for example if a test needs out-of-band execution of QMP commands, it can initialize with the oob capability. Signed-off-by: Juraj Marcin <jmarcin@redhat.com> Reviewed-by: Peter Xu <peterx@redhat.com> Signed-off-by: Fabiano Rosas <farosas@suse.de>
| * tests/qtest: QTest example for RISC-V CSR registerIvan Klokov2025-01-172-1/+57
| | | | | | | | | | | | | | | | | | | | Added demo for reading CSR register from qtest environment. Signed-off-by: Ivan Klokov <ivan.klokov@syntacore.com> Reviewed-by: Fabiano Rosas <farosas@suse.de> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Acked-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Fabiano Rosas <farosas@suse.de>
| * target/riscv: Add RISC-V CSR qtest supportIvan Klokov2025-01-172-0/+41
| | | | | | | | | | | | | | | | | | | | | | | | The RISC-V architecture supports the creation of custom CSR-mapped devices. It would be convenient to test them in the same way as MMIO-mapped devices. To do this, a new call has been added to read/write CSR registers. Signed-off-by: Ivan Klokov <ivan.klokov@syntacore.com> Acked-by: Fabiano Rosas <farosas@suse.de> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Signed-off-by: Fabiano Rosas <farosas@suse.de>
* | tests/qtest: fix some copy and paste errors in kdocAlex Bennée2025-01-172-4/+4
| | | | | | | | | | | | | | | | | | A number of copy and paste kdoc comments are referring to the wrong definition. Fix those cases. Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20250116160306.1709518-29-alex.bennee@linaro.org>
* | plugins: enable linking with clang/lldPierrick Bouvier2025-01-171-2/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Windows uses a special mechanism to enable plugins to work (DLL delay loading). Option for lld is different than ld. MSYS2 clang based environment use lld by default, so restricting to this config on Windows is safe, and will avoid false bug reports. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Tested-by: Stefan Weil <sw@weilnetz.de> Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20250110203401.178532-4-pierrick.bouvier@linaro.org> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20250116160306.1709518-26-alex.bennee@linaro.org>
* | tests/tcg/plugins/mem: fix 32-bit buildPierrick Bouvier2025-01-171-3/+3
| | | | | | | | | | | | | | | | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Message-Id: <20241217224306.2900490-5-pierrick.bouvier@linaro.org> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20250116160306.1709518-15-alex.bennee@linaro.org>
* | tests/tcg/plugins/syscall: fix 32-bit buildPierrick Bouvier2025-01-171-3/+3
| | | | | | | | | | | | | | | | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Message-Id: <20241217224306.2900490-4-pierrick.bouvier@linaro.org> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20250116160306.1709518-14-alex.bennee@linaro.org>
* | tests/tcg/plugins/insn: remove unused callback parameterPierrick Bouvier2025-01-171-3/+1
|/ | | | | | | | Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20250116160306.1709518-12-alex.bennee@linaro.org>
* tests: acpi: update expected blobsIgor Mammedov2025-01-1541-40/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | _DSM function 7 AML should have followig change: If ((Arg2 == 0x07)) { - Local0 = Package (0x02) - { - Zero, - "" - } Local2 = AIDX (DerefOf (Arg4 [Zero]), DerefOf (Arg4 [One] )) - Local0 [Zero] = Local2 + Local0 = Package (0x02) {} + If (!((Local2 == Zero) || (Local2 == 0xFFFFFFFF))) + { + Local0 [Zero] = Local2 + Local0 [One] = "" + } + Return (Local0) } } Signed-off-by: Igor Mammedov <imammedo@redhat.com> Message-Id: <20250115125342.3883374-4-imammedo@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
* tests: acpi: whitelist expected blobsIgor Mammedov2025-01-151-0/+40
| | | | | | | Signed-off-by: Igor Mammedov <imammedo@redhat.com> Message-Id: <20250115125342.3883374-2-imammedo@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
* tests/qtest: Add intel-iommu testZhenzhong Duan2025-01-152-0/+65
| | | | | | | | | | | | | | | Add the framework to test the intel-iommu device. Currently only tested cap/ecap bits correctness when x-flts=on in scalable mode. Also tested cap/ecap bits consistency before and after system reset. Signed-off-by: Zhenzhong Duan <zhenzhong.duan@intel.com> Acked-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Clément Mathieu--Drif<clement.mathieu--drif@eviden.com> Acked-by: Jason Wang <jasowang@redhat.com> Message-Id: <20241212083757.605022-21-zhenzhong.duan@intel.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
* tests/acpi: q35: Update host address width in DMARZhenzhong Duan2025-01-152-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Differences: @@ -1,39 +1,39 @@ /* * Intel ACPI Component Architecture * AML/ASL+ Disassembler version 20200925 (64-bit version) * Copyright (c) 2000 - 2020 Intel Corporation * - * Disassembly of tests/data/acpi/x86/q35/DMAR.dmar, Mon Nov 11 15:31:18 2024 + * Disassembly of /tmp/aml-SPJ4W2, Mon Nov 11 15:31:18 2024 * * ACPI Data Table [DMAR] * * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue */ [000h 0000 4] Signature : "DMAR" [DMA Remapping table] [004h 0004 4] Table Length : 00000078 [008h 0008 1] Revision : 01 -[009h 0009 1] Checksum : 15 +[009h 0009 1] Checksum : 0C [00Ah 0010 6] Oem ID : "BOCHS " [010h 0016 8] Oem Table ID : "BXPC " [018h 0024 4] Oem Revision : 00000001 [01Ch 0028 4] Asl Compiler ID : "BXPC" [020h 0032 4] Asl Compiler Revision : 00000001 -[024h 0036 1] Host Address Width : 26 +[024h 0036 1] Host Address Width : 2F [025h 0037 1] Flags : 01 [026h 0038 10] Reserved : 00 00 00 00 00 00 00 00 00 00 [030h 0048 2] Subtable Type : 0000 [Hardware Unit Definition] [032h 0050 2] Length : 0040 [034h 0052 1] Flags : 00 [035h 0053 1] Reserved : 00 [036h 0054 2] PCI Segment Number : 0000 [038h 0056 8] Register Base Address : 00000000FED90000 [040h 0064 1] Device Scope Type : 03 [IOAPIC Device] [041h 0065 1] Entry Length : 08 [042h 0066 2] Reserved : 0000 [044h 0068 1] Enumeration ID : 00 [045h 0069 1] PCI Bus Number : FF Signed-off-by: Zhenzhong Duan <zhenzhong.duan@intel.com> Acked-by: Clément Mathieu--Drif<clement.mathieu--drif@eviden.com> Message-Id: <20241212083757.605022-18-zhenzhong.duan@intel.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
* tests/acpi: q35: allow DMAR acpi table changesZhenzhong Duan2025-01-151-0/+1
| | | | | | | | Signed-off-by: Zhenzhong Duan <zhenzhong.duan@intel.com> Acked-by: Jason Wang <jasowang@redhat.com> Message-Id: <20241212083757.605022-16-zhenzhong.duan@intel.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
* tests: acpi: update expected blobsIgor Mammedov2025-01-1543-42/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | previous patch has changed cpu hotplug AML, expected diff: @@ -2942,6 +2942,7 @@ DefinitionBlock ("", "DSDT", 1, "BOCHS ", "BXPC ", 0x00000001) { Acquire (\_SB.PCI0.PRES.CPLK, 0xFFFF) Name (CNEW, Package (0xFF) {}) + Name (CEJL, Package (0xFF) {}) Local3 = Zero Local4 = One While ((Local4 == One)) @@ -2949,6 +2950,7 @@ DefinitionBlock ("", "DSDT", 1, "BOCHS ", "BXPC ", 0x00000001) Local4 = Zero Local0 = One Local1 = Zero + Local5 = Zero While (((Local0 == One) && (Local3 < One))) { Local0 = Zero @@ -2959,7 +2961,7 @@ DefinitionBlock ("", "DSDT", 1, "BOCHS ", "BXPC ", 0x00000001) Break } - If ((Local1 == 0xFF)) + If (((Local1 == 0xFF) || (Local5 == 0xFF))) { Local4 = One Break @@ -2972,10 +2974,11 @@ DefinitionBlock ("", "DSDT", 1, "BOCHS ", "BXPC ", 0x00000001) Local1++ Local0 = One } - ElseIf ((\_SB.PCI0.PRES.CRMV == One)) + + If ((\_SB.PCI0.PRES.CRMV == One)) { - CTFY (Local3, 0x03) - \_SB.PCI0.PRES.CRMV = One + CEJL [Local5] = Local3 + Local5++ Local0 = One } @@ -2992,6 +2995,16 @@ DefinitionBlock ("", "DSDT", 1, "BOCHS ", "BXPC ", 0x00000001) \_SB.PCI0.PRES.CINS = One Local2++ } + + Local2 = Zero + While ((Local2 < Local5)) + { + Local3 = DerefOf (CEJL [Local2]) + CTFY (Local3, 0x03) + \_SB.PCI0.PRES.CSEL = Local3 + \_SB.PCI0.PRES.CRMV = One + Local2++ + } } Release (\_SB.PCI0.PRES.CPLK) Signed-off-by: Igor Mammedov <imammedo@redhat.com> Message-Id: <20241210163945.3422623-4-imammedo@redhat.com> Tested-by: Eric Mackay <eric.mackay@oracle.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
* tests: acpi: whitelist expected blobsIgor Mammedov2025-01-151-0/+42
| | | | | | | | | Signed-off-by: Igor Mammedov <imammedo@redhat.com> Message-Id: <20241210163945.3422623-2-imammedo@redhat.com> Tested-by: Eric Mackay <eric.mackay@oracle.com> Acked-by: Ani Sinha <anisinha@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
* tests: Add functional tests for HPPA machinesPhilippe Mathieu-Daudé2025-01-134-3/+40
| | | | | | | | | | | | | | | | | | | Add quick firmware boot tests (less than 1sec) for the B160L (32-bit) and C3700 (64-bit) HPPA machines: $ make check-functional-hppa ... 4/4 qemu:func-quick+func-hppa / func-hppa-hppa_seabios OK 0.22s 2 subtests passed Remove the duplicated B160L test in qtest/boot-serial-test.c. Suggested-by: Helge Deller <deller@gmx.de> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Helge Deller <deller@gmx.de> Tested-by: Helge Deller <deller@gmx.de> Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20250102100340.43014-3-philmd@linaro.org>
* tests/qtest/boot-serial-test: Correct HPPA machine namePhilippe Mathieu-Daudé2025-01-131-1/+1
| | | | | | | | | | | | | | Commit 7df6f751176 ("hw/hppa: Split out machine creation") renamed the 'hppa' machine as 'B160L', but forgot to update the boot serial test, which ended being skipped. Cc: qemu-stable@nongnu.org Fixes: 7df6f751176 ("hw/hppa: Split out machine creation") Reported-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Message-Id: <20250102100340.43014-2-philmd@linaro.org>
* tests/qtest/libqos: Reuse TYPE_IMX_I2C defineBernhard Beschow2025-01-132-4/+5
| | | | | | | | | Signed-off-by: Bernhard Beschow <shentey@gmail.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Fabiano Rosas <farosas@suse.de> Message-ID: <20250108092538.11474-12-shentey@gmail.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
* hw/ufs: Adjust value to match CPU's endian formatKeoseong Park2025-01-131-1/+1
| | | | | | | | | | | | | | In ufs_write_attr_value(), the value parameter is handled in the CPU's endian format but provided in big-endian format by the caller. Thus, it is converted to the CPU's endian format. The related test code is also fixed to reflect this change. Fixes: 7c85332a2b3e ("hw/ufs: minor bug fixes related to ufs-test") Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Keoseong Park <keosung.park@samsung.com> Reviewed-by: Jeuk Kim <jeuk20.kim@samsung.com> Message-ID: <20250107084356epcms2p2af4d86432174d76ea57336933e46b4c3@epcms2p2> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
* Merge tag 'pull-target-arm-20250113' of ↵Stefan Hajnoczi2025-01-133-13/+28
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | https://git.linaro.org/people/pmaydell/qemu-arm into staging target-arm queue: * hw/arm_sysctl: fix extracting 31th bit of val * hw/misc: cast rpm to uint64_t * tests/qtest/boot-serial-test: Improve ASM * target/arm: Move minor arithmetic helpers out of helper.c * target/arm: change default pauth algorithm to impdef # -----BEGIN PGP SIGNATURE----- # # iQJNBAABCAA3FiEE4aXFk81BneKOgxXPPCUl7RQ2DN4FAmeFGuUZHHBldGVyLm1h # eWRlbGxAbGluYXJvLm9yZwAKCRA8JSXtFDYM3mFPEAChT9DR/+bNSt0Q28TsCv84 # dMMXle7c821NHTNeP/uBQ0i3aopmOJE145wMSoZza8l+EYjOdQwHpinjfu8J/rOS # mJUgAFRcgUoH77+k0p0x1tqKi7+669TznOMOF4RyudKju5SteVyOGgLNjzJlnItq # 3QRBiDTS+qXqAUhgQtzcuY6Xl5M2KA/cpSWYxQf/JPpZMX2c37V8AlSF/1GkLo6Z # 3afrasXUp+U0+03Pe3Ffknzx/LtkLc2hg2LVX8CeqMLRJSA0ohkSwa/xax+2hn+G # 9fKn92IpQOjEFw6qBTBvkerP2hr6yhDFTVFI9v+lsY4bf7tQGIE75HEGZ1EMr26b # LCIPSQvez9exZl/usLGkUq9MWAiEkhBMy99ajwg5X4IhcbS+oyFtH2teYpt9rd9N # 2dVS5qzErN7TCZQza9A7+bt8v5OtbJk2K8Qx9QhMFU/dIUSp0vOA3NwGu+qkciAb # wNdoXT22Hy0czDiQ/ln3aocmwWeVZN4+AxKNoigQhor+5oIR4lMn1P7yAmsCLeL8 # AaLXJdR4aLnYugh23qzv9wf9kAbxRBMvLbsNTKGG00DYQ0xoY4pQ2CmPAJoVVxpU # FjRydG9sC/6sMoJiOoDVpPW003VY2If8r0ObzqUd2gkw1HLf12yug+lij0LkcXKC # Au7ycaoHiTlluNxyQjsgPg== # =FGfo # -----END PGP SIGNATURE----- # gpg: Signature made Mon 13 Jan 2025 08:53:41 EST # gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE # gpg: issuer "peter.maydell@linaro.org" # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [full] # gpg: aka "Peter Maydell <pmaydell@gmail.com>" [full] # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [full] # gpg: aka "Peter Maydell <peter@archaic.org.uk>" [unknown] # Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE * tag 'pull-target-arm-20250113' of https://git.linaro.org/people/pmaydell/qemu-arm: docs/system/arm/virt: mention specific migration information target/arm: change default pauth algorithm to impdef tests/tcg/aarch64: force qarma5 for pauth-3 test target/arm: add new property to select pauth-qarma5 target/arm: Move minor arithmetic helpers out of helper.c tests/qtest/boot-serial-test: Initialize PL011 Control register tests/qtest/boot-serial-test: Reorder pair of instructions in PL011 test tests/qtest/boot-serial-test: Reduce for() loop in PL011 tests tests/qtest/boot-serial-test: Improve ASM comments of PL011 tests hw/misc: cast rpm to uint64_t hw/arm_sysctl: fix extracting 31th bit of val Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
| * tests/tcg/aarch64: force qarma5 for pauth-3 testPeter Maydell2025-01-131-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | The pauth-3 test explicitly tests that a computation of the pointer-authentication produces the expected result. This means that it must be run with the QARMA5 algorithm. Explicitly set the pauth algorithm when running this test, so that it doesn't break when we change the default algorithm the 'max' CPU uses. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * target/arm: add new property to select pauth-qarma5Pierrick Bouvier2025-01-131-4/+11
| | | | | | | | | | | | | | | | | | | | | | | | Before changing default pauth algorithm, we need to make sure current default one (QARMA5) can still be selected. $ qemu-system-aarch64 -cpu max,pauth-qarma5=on ... Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20241219183211.3493974-2-pierrick.bouvier@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * tests/qtest/boot-serial-test: Initialize PL011 Control registerPhilippe Mathieu-Daudé2025-01-131-1/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The tests using the PL011 UART of the virt and raspi machines weren't properly enabling the UART and its transmitter previous to sending characters. Follow the PL011 manual initialization recommendation by setting the proper bits of the control register. Update the ASM code prefixing: *UART_CTRL = UART_ENABLE | TX_ENABLE; to: while (true) { *UART_DATA = 'T'; } Note, since commit 51b61dd4d56 ("hw/char/pl011: Warn when using disabled transmitter") incomplete PL011 initialization can be logged using the '-d guest_errors' command line option. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * tests/qtest/boot-serial-test: Reorder pair of instructions in PL011 testPhilippe Mathieu-Daudé2025-01-131-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | In the next commit we are going to use a different value for the $w1 register, maintaining the same $x2 value. In order to keep the next commit trivial to review, set $x2 before $w1. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Fabiano Rosas <farosas@suse.de> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * tests/qtest/boot-serial-test: Reduce for() loop in PL011 testsPhilippe Mathieu-Daudé2025-01-131-6/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Since registers are not modified, we don't need to refill their values. Directly jump to the previous store instruction to keep filling the TXDAT register. The equivalent C code remains: while (true) { *UART_DATA = 'T'; } Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Fabiano Rosas <farosas@suse.de> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * tests/qtest/boot-serial-test: Improve ASM comments of PL011 testsPhilippe Mathieu-Daudé2025-01-131-9/+9
| | | | | | | | | | | | | | | | | | Re-indent ASM comments adding the 'loop:' label. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Fabiano Rosas <farosas@suse.de> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* | dockerfiles: Remove 'MAINTAINER' entry in debian-tricore-cross.dockerPhilippe Mathieu-Daudé2025-01-111-2/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | AMSAT closed its email service [*] so my personal email address is now defunct. Remove it to avoid bouncing emails. [*] https://web.archive.org/web/20240617194936/https://forum.amsat-dl.org/index.php?thread/4581-amsat-mail-alias-service-to-end-august-1-2024/ Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Message-Id: <20250102152513.61065-1-philmd@linaro.org> [AJB: update URL to web.archive.org] Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20250108121054.1126164-32-alex.bennee@linaro.org>
* | pc-bios: ensure keymaps dependencies set vnc testsAlex Bennée2025-01-111-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | I was seeing failures on vnc-display-test on FreeBSD: make vm-build-freebsd V=1 TARGET_LIST=aarch64-softmmu BUILD_TARGET=check-qtest QEMU_LOCAL=1 DEBUG=1 Leads to: qemu-system-aarch64: -vnc none: could not read keymap file: 'en-us' Broken pipe ../src/tests/qtest/libqtest.c:196: kill_qemu() tried to terminate QEMU process but encountered exit status 1 (expected 0) which was as far as I could tell because we don't populate the $BLD/pc-bios/keymaps (although scripts/symlink-install-tree.py attempts to symlink qemu-bundle/usr/local/share/qemu/keymaps/ to that dir). Reviewed-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20250108121054.1126164-31-alex.bennee@linaro.org>