From 4bce526ec4b88362a684fd858e0e14c83ddf0db4 Mon Sep 17 00:00:00 2001 From: Laurent Dufour Date: Fri, 27 Jun 2014 15:47:37 +0200 Subject: target-ppc: KVMPPC_H_CAS fix cpu-version endianess During KVMPPC_H_CAS processing, the cpu-version updated value is stored without taking care of the current endianess. As a consequence, the guest may not switch to the right CPU model, leading to unexpected results. If needed, the value is now converted. Fixes: 6d9412ea8132 ("target-ppc: Implement "compat" CPU option") Signed-off-by: Laurent Dufour Reviewed-by: Greg Kurz Signed-off-by: Alexander Graf --- hw/ppc/spapr.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c index a8ba916970..a23c0f080e 100644 --- a/hw/ppc/spapr.c +++ b/hw/ppc/spapr.c @@ -160,8 +160,7 @@ static int spapr_fixup_cpu_smt_dt(void *fdt, int offset, PowerPCCPU *cpu, int index = ppc_get_vcpu_dt_id(cpu); if (cpu->cpu_version) { - ret = fdt_setprop(fdt, offset, "cpu-version", - &cpu->cpu_version, sizeof(cpu->cpu_version)); + ret = fdt_setprop_cell(fdt, offset, "cpu-version", cpu->cpu_version); if (ret < 0) { return ret; } -- cgit 1.4.1 From a74029f6cbce43074793dc30534fb6b3aeab7584 Mon Sep 17 00:00:00 2001 From: Richard Henderson Date: Sat, 28 Jun 2014 09:45:27 -0700 Subject: target-ppc: Change default cpu for ppc64le-linux-user The default, 970fx, doesn't support MSR_LE. So even though we set LE in ppc_cpu_reset, it gets cleared again in hreg_store_msr. Error out if a user-selected cpu model doesn't support LE. Signed-off-by: Richard Henderson [agraf: switch to POWER7 as default for BE and LE] Signed-off-by: Alexander Graf --- linux-user/main.c | 8 ++++---- target-ppc/translate_init.c | 4 ++++ 2 files changed, 8 insertions(+), 4 deletions(-) diff --git a/linux-user/main.c b/linux-user/main.c index 900a17fa33..b453a39853 100644 --- a/linux-user/main.c +++ b/linux-user/main.c @@ -3901,11 +3901,11 @@ int main(int argc, char **argv, char **envp) #elif defined TARGET_OPENRISC cpu_model = "or1200"; #elif defined(TARGET_PPC) -#ifdef TARGET_PPC64 - cpu_model = "970fx"; -#else +# ifdef TARGET_PPC64 + cpu_model = "POWER7"; +# else cpu_model = "750"; -#endif +# endif #else cpu_model = "any"; #endif diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c index 2ab281069c..7b4d9beae2 100644 --- a/target-ppc/translate_init.c +++ b/target-ppc/translate_init.c @@ -9551,6 +9551,10 @@ static void ppc_cpu_reset(CPUState *s) #endif #if !defined(TARGET_WORDS_BIGENDIAN) msr |= (target_ulong)1 << MSR_LE; /* Little-endian user mode */ + if (!((env->msr_mask >> MSR_LE) & 1)) { + fprintf(stderr, "Selected CPU does not support little-endian.\n"); + exit(1); + } #endif #endif -- cgit 1.4.1 From be5c9ddabc25f73b619974027f7894d8cb8a2c82 Mon Sep 17 00:00:00 2001 From: Richard Henderson Date: Sat, 28 Jun 2014 09:45:28 -0700 Subject: target-ppc: Fix gdbstub for ppc64le-linux-user The bswap that's needed for system mode isn't required for user mode, and in fact breaks debugging. Signed-off-by: Richard Henderson [agraf: fix apple gdbstub implementation] Signed-off-by: Alexander Graf --- target-ppc/gdbstub.c | 34 +++++++++++++++------------------- 1 file changed, 15 insertions(+), 19 deletions(-) diff --git a/target-ppc/gdbstub.c b/target-ppc/gdbstub.c index 694d303e19..14675f4565 100644 --- a/target-ppc/gdbstub.c +++ b/target-ppc/gdbstub.c @@ -83,16 +83,24 @@ static int ppc_gdb_register_len(int n) } } - -static void ppc_gdb_swap_register(uint8_t *mem_buf, int n, int len) +/* We need to present the registers to gdb in the "current" memory ordering. + For user-only mode we get this for free; TARGET_WORDS_BIGENDIAN is set to + the proper ordering for the binary, and cannot be changed. + For system mode, TARGET_WORDS_BIGENDIAN is always set, and we must check + the current mode of the chip to see if we're running in little-endian. */ +static void maybe_bswap_register(CPUPPCState *env, uint8_t *mem_buf, int len) { - if (len == 4) { +#ifndef CONFIG_USER_ONLY + if (!msr_le) { + /* do nothing */ + } else if (len == 4) { bswap32s((uint32_t *)mem_buf); } else if (len == 8) { bswap64s((uint64_t *)mem_buf); } else { g_assert_not_reached(); } +#endif } /* Old gdb always expects FP registers. Newer (xml-aware) gdb only @@ -150,10 +158,7 @@ int ppc_cpu_gdb_read_register(CPUState *cs, uint8_t *mem_buf, int n) break; } } - if (msr_le) { - /* If cpu is in LE mode, convert memory contents to LE. */ - ppc_gdb_swap_register(mem_buf, n, r); - } + maybe_bswap_register(env, mem_buf, r); return r; } @@ -209,10 +214,7 @@ int ppc_cpu_gdb_read_register_apple(CPUState *cs, uint8_t *mem_buf, int n) break; } } - if (msr_le) { - /* If cpu is in LE mode, convert memory contents to LE. */ - ppc_gdb_swap_register(mem_buf, n, r); - } + maybe_bswap_register(env, mem_buf, r); return r; } @@ -225,10 +227,7 @@ int ppc_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) if (!r) { return r; } - if (msr_le) { - /* If cpu is in LE mode, convert memory contents to LE. */ - ppc_gdb_swap_register(mem_buf, n, r); - } + maybe_bswap_register(env, mem_buf, r); if (n < 32) { /* gprs */ env->gpr[n] = ldtul_p(mem_buf); @@ -278,10 +277,7 @@ int ppc_cpu_gdb_write_register_apple(CPUState *cs, uint8_t *mem_buf, int n) if (!r) { return r; } - if (msr_le) { - /* If cpu is in LE mode, convert memory contents to LE. */ - ppc_gdb_swap_register(mem_buf, n, r); - } + maybe_bswap_register(env, mem_buf, r); if (n < 32) { /* gprs */ env->gpr[n] = ldq_p(mem_buf); -- cgit 1.4.1 From da89a1cf92be6c195ff35afd253a11b427a152c3 Mon Sep 17 00:00:00 2001 From: Alexander Graf Date: Wed, 2 Jul 2014 19:09:47 +0200 Subject: PPC: Fix booke206 TLB with phys addrs > 32bit We were truncating physical addresses to 32bit when using qemu-system-ppc with a booke206 TLB implementation. This patch fixes that and makes the full address space available. Signed-off-by: Alexander Graf --- target-ppc/mmu_helper.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/target-ppc/mmu_helper.c b/target-ppc/mmu_helper.c index 4d6b1e20c0..4a34a73ad4 100644 --- a/target-ppc/mmu_helper.c +++ b/target-ppc/mmu_helper.c @@ -897,10 +897,10 @@ static hwaddr booke206_tlb_to_page_size(CPUPPCState *env, /* TLB check function for MAS based SoftTLBs */ static int ppcmas_tlb_check(CPUPPCState *env, ppcmas_tlb_t *tlb, - hwaddr *raddrp, - target_ulong address, uint32_t pid) + hwaddr *raddrp, target_ulong address, + uint32_t pid) { - target_ulong mask; + hwaddr mask; uint32_t tlb_pid; if (!msr_cm) { -- cgit 1.4.1 From d6c23f8a1b0d3ffdd7e826e1d555b519645257d9 Mon Sep 17 00:00:00 2001 From: Alexey Kardashevskiy Date: Thu, 3 Jul 2014 23:25:56 +1000 Subject: pseries: Update SLOF firmware image to qemu-slof-20140630 The changelog is: > Quieten the grub warning > Add boot menu support > boot from disk having chrp-boot file > fat16: fix read and remove debug messages > dhcparch define missing in compilation > pci-scan: reserve memory for pci-bridge without devices > pci-bridge: Fix ranges when no device beyond the bridge > Set dhcp arch in board-qemu config file > xhci: fix controller stop > dhcp: support client architecture code 93 > virtio-blk: support variable block size > usb: use common pci dma alloc/mapping routines > Remove unused SLOF code > pci-bridge: generic bridge needs to support pci dma functions > pci: extract dma functions as separate file > e1000: fix usage of multiple nics Signed-off-by: Alexey Kardashevskiy Signed-off-by: Alexander Graf --- pc-bios/README | 2 +- pc-bios/slof.bin | Bin 921720 -> 923896 bytes roms/SLOF | 2 +- 3 files changed, 2 insertions(+), 2 deletions(-) diff --git a/pc-bios/README b/pc-bios/README index 49cdacfaa5..edfadd7d38 100644 --- a/pc-bios/README +++ b/pc-bios/README @@ -17,7 +17,7 @@ - SLOF (Slimline Open Firmware) is a free IEEE 1275 Open Firmware implementation for certain IBM POWER hardware. The sources are at https://github.com/aik/SLOF, and the image currently in qemu is - built from git tag qemu-slof-20140404. + built from git tag qemu-slof-20140630. - sgabios (the Serial Graphics Adapter option ROM) provides a means for legacy x86 software to communicate with an attached serial console as diff --git a/pc-bios/slof.bin b/pc-bios/slof.bin index 972e012e51..69b0a5dbc3 100644 Binary files a/pc-bios/slof.bin and b/pc-bios/slof.bin differ diff --git a/roms/SLOF b/roms/SLOF index c90b50b505..f284ab3f03 160000 --- a/roms/SLOF +++ b/roms/SLOF @@ -1 +1 @@ -Subproject commit c90b50b5055f976a0da3c032f26fb80157292adc +Subproject commit f284ab3f03ae69a20e1ae966f6ddf76da33cbf72 -- cgit 1.4.1 From 03ae4133ab8675d4c67e6fdc8032de7c53a89514 Mon Sep 17 00:00:00 2001 From: Alexey Kardashevskiy Date: Fri, 4 Jul 2014 00:48:55 +1000 Subject: target-ppc: Add pvr_match() callback So far it was enough to have a base PVR value and mask per CPU family such as POWER7 or POWER8. However there CPUs which are completely architecturally compatible but have different PVRs such as POWER7/POWER7+ and POWER8/POWER8E. For these CPUs, top 16 bits are CPU family and low 16 bits are the version. The families have PVR base values different enough so defining a mask which would cover both (or potentially more) CPUs within the family is not possible. This adds a pvr_match() callback to PowerPCCPUClass. The default handler simply compares PVR defined in the class. This implements ppc_pvr_match_power7/ppc_pvr_match_power8 callbacks for POWER7/8 families. These check for POWER7/POWER7+ and POWER8/POWER8E. This changes ppc_cpu_compare_class_pvr_mask() not to check masks but use the pvr_match() callback. Since all server CPUs use the same mask, this defines one mask value - CPU_POWERPC_POWER_SERVER_MASK - which is used everywhere now. This removes other mask definitions. This removes pvr_mask from PowerPCCPUClass as it is not used anymore. This removes pvr initialization for POWER7/8 families as it is not used to find the class, the pvr_match() callback is used instead. Signed-off-by: Alexey Kardashevskiy Signed-off-by: Alexander Graf --- target-ppc/cpu-models.c | 1 - target-ppc/cpu-models.h | 6 +----- target-ppc/cpu-qom.h | 2 +- target-ppc/translate_init.c | 49 ++++++++++++++++++++++++++++++++------------- 4 files changed, 37 insertions(+), 21 deletions(-) diff --git a/target-ppc/cpu-models.c b/target-ppc/cpu-models.c index 9a91af9dbf..c9112e9cd8 100644 --- a/target-ppc/cpu-models.c +++ b/target-ppc/cpu-models.c @@ -44,7 +44,6 @@ PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); \ \ pcc->pvr = _pvr; \ - pcc->pvr_mask = CPU_POWERPC_DEFAULT_MASK; \ pcc->svr = _svr; \ dc->desc = _desc; \ } \ diff --git a/target-ppc/cpu-models.h b/target-ppc/cpu-models.h index c39d03a504..290a7597dc 100644 --- a/target-ppc/cpu-models.h +++ b/target-ppc/cpu-models.h @@ -39,7 +39,6 @@ extern PowerPCCPUAlias ppc_cpu_aliases[]; /*****************************************************************************/ /* PVR definitions for most known PowerPC */ enum { - CPU_POWERPC_DEFAULT_MASK = 0xFFFFFFFF, /* PowerPC 401 family */ /* Generic PowerPC 401 */ #define CPU_POWERPC_401 CPU_POWERPC_401G2 @@ -553,17 +552,14 @@ enum { CPU_POWERPC_POWER6 = 0x003E0000, CPU_POWERPC_POWER6_5 = 0x0F000001, /* POWER6 in POWER5 mode */ CPU_POWERPC_POWER6A = 0x0F000002, + CPU_POWERPC_POWER_SERVER_MASK = 0xFFFF0000, CPU_POWERPC_POWER7_BASE = 0x003F0000, - CPU_POWERPC_POWER7_MASK = 0xFFFF0000, CPU_POWERPC_POWER7_v23 = 0x003F0203, CPU_POWERPC_POWER7P_BASE = 0x004A0000, - CPU_POWERPC_POWER7P_MASK = 0xFFFF0000, CPU_POWERPC_POWER7P_v21 = 0x004A0201, CPU_POWERPC_POWER8E_BASE = 0x004B0000, - CPU_POWERPC_POWER8E_MASK = 0xFFFF0000, CPU_POWERPC_POWER8E_v10 = 0x004B0100, CPU_POWERPC_POWER8_BASE = 0x004D0000, - CPU_POWERPC_POWER8_MASK = 0xFFFF0000, CPU_POWERPC_POWER8_v10 = 0x004D0100, CPU_POWERPC_970 = 0x00390202, CPU_POWERPC_970FX_v10 = 0x00391100, diff --git a/target-ppc/cpu-qom.h b/target-ppc/cpu-qom.h index f1f0a52998..0fee36f06a 100644 --- a/target-ppc/cpu-qom.h +++ b/target-ppc/cpu-qom.h @@ -56,7 +56,7 @@ typedef struct PowerPCCPUClass { void (*parent_reset)(CPUState *cpu); uint32_t pvr; - uint32_t pvr_mask; + bool (*pvr_match)(struct PowerPCCPUClass *pcc, uint32_t pvr); uint64_t pcr_mask; uint32_t svr; uint64_t insns_flags; diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c index 7b4d9beae2..2c9c27714b 100644 --- a/target-ppc/translate_init.c +++ b/target-ppc/translate_init.c @@ -8062,6 +8062,17 @@ static void init_proc_POWER7 (CPUPPCState *env) init_proc_book3s_64(env, BOOK3S_CPU_POWER7); } +static bool ppc_pvr_match_power7(PowerPCCPUClass *pcc, uint32_t pvr) +{ + if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER7P_BASE) { + return true; + } + if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER7_BASE) { + return true; + } + return false; +} + POWERPC_FAMILY(POWER7)(ObjectClass *oc, void *data) { DeviceClass *dc = DEVICE_CLASS(oc); @@ -8070,8 +8081,7 @@ POWERPC_FAMILY(POWER7)(ObjectClass *oc, void *data) dc->fw_name = "PowerPC,POWER7"; dc->desc = "POWER7"; dc->props = powerpc_servercpu_properties; - pcc->pvr = CPU_POWERPC_POWER7_BASE; - pcc->pvr_mask = CPU_POWERPC_POWER7_MASK; + pcc->pvr_match = ppc_pvr_match_power7; pcc->pcr_mask = PCR_COMPAT_2_05 | PCR_COMPAT_2_06; pcc->init_proc = init_proc_POWER7; pcc->check_pow = check_pow_nocheck; @@ -8131,8 +8141,7 @@ POWERPC_FAMILY(POWER7P)(ObjectClass *oc, void *data) dc->fw_name = "PowerPC,POWER7+"; dc->desc = "POWER7+"; dc->props = powerpc_servercpu_properties; - pcc->pvr = CPU_POWERPC_POWER7P_BASE; - pcc->pvr_mask = CPU_POWERPC_POWER7P_MASK; + pcc->pvr_match = ppc_pvr_match_power7; pcc->pcr_mask = PCR_COMPAT_2_05 | PCR_COMPAT_2_06; pcc->init_proc = init_proc_POWER7; pcc->check_pow = check_pow_nocheck; @@ -8189,6 +8198,17 @@ static void init_proc_POWER8(CPUPPCState *env) init_proc_book3s_64(env, BOOK3S_CPU_POWER8); } +static bool ppc_pvr_match_power8(PowerPCCPUClass *pcc, uint32_t pvr) +{ + if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER8E_BASE) { + return true; + } + if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER8_BASE) { + return true; + } + return false; +} + POWERPC_FAMILY(POWER8E)(ObjectClass *oc, void *data) { DeviceClass *dc = DEVICE_CLASS(oc); @@ -8197,8 +8217,7 @@ POWERPC_FAMILY(POWER8E)(ObjectClass *oc, void *data) dc->fw_name = "PowerPC,POWER8"; dc->desc = "POWER8E"; dc->props = powerpc_servercpu_properties; - pcc->pvr = CPU_POWERPC_POWER8E_BASE; - pcc->pvr_mask = CPU_POWERPC_POWER8E_MASK; + pcc->pvr_match = ppc_pvr_match_power8; pcc->pcr_mask = PCR_COMPAT_2_05 | PCR_COMPAT_2_06; pcc->init_proc = init_proc_POWER8; pcc->check_pow = check_pow_nocheck; @@ -8256,13 +8275,10 @@ POWERPC_FAMILY(POWER8E)(ObjectClass *oc, void *data) POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data) { DeviceClass *dc = DEVICE_CLASS(oc); - PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); ppc_POWER8E_cpu_family_class_init(oc, data); dc->desc = "POWER8"; - pcc->pvr = CPU_POWERPC_POWER8_BASE; - pcc->pvr_mask = CPU_POWERPC_POWER8_MASK; } #endif /* defined (TARGET_PPC64) */ @@ -9245,7 +9261,6 @@ static gint ppc_cpu_compare_class_pvr_mask(gconstpointer a, gconstpointer b) ObjectClass *oc = (ObjectClass *)a; uint32_t pvr = *(uint32_t *)b; PowerPCCPUClass *pcc = (PowerPCCPUClass *)a; - gint ret; /* -cpu host does a PVR lookup during construction */ if (unlikely(strcmp(object_class_get_name(oc), @@ -9257,9 +9272,11 @@ static gint ppc_cpu_compare_class_pvr_mask(gconstpointer a, gconstpointer b) return -1; } - ret = (((pcc->pvr & pcc->pvr_mask) == (pvr & pcc->pvr_mask)) ? 0 : -1); + if (pcc->pvr_match(pcc, pvr)) { + return 0; + } - return ret; + return -1; } PowerPCCPUClass *ppc_cpu_class_by_pvr_mask(uint32_t pvr) @@ -9660,6 +9677,11 @@ static void ppc_cpu_initfn(Object *obj) } } +static bool ppc_pvr_match_default(PowerPCCPUClass *pcc, uint32_t pvr) +{ + return pcc->pvr == pvr; +} + static void ppc_cpu_class_init(ObjectClass *oc, void *data) { PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); @@ -9667,8 +9689,7 @@ static void ppc_cpu_class_init(ObjectClass *oc, void *data) DeviceClass *dc = DEVICE_CLASS(oc); pcc->parent_realize = dc->realize; - pcc->pvr = CPU_POWERPC_DEFAULT_MASK; - pcc->pvr_mask = CPU_POWERPC_DEFAULT_MASK; + pcc->pvr_match = ppc_pvr_match_default; pcc->interrupts_big_endian = ppc_cpu_interrupts_big_endian_always; dc->realize = ppc_cpu_realizefn; dc->unrealize = ppc_cpu_unrealizefn; -- cgit 1.4.1 From b60c60070c0df4ef01d5c727929fe0e93e6fdd09 Mon Sep 17 00:00:00 2001 From: Alexey Kardashevskiy Date: Tue, 1 Jul 2014 00:30:18 +1000 Subject: target-ppc: Remove POWER7+ and POWER8E families POWER8E is architecturally equal to POWER8 and POWER7+ is equal to POWER7. Also no user space tool makes any difference for CPU node name in the device tree (such as PowerPC,POWER7@0 vs. PowerPC,POWER7+@0). So there is no point in emulating POWER7+ and POWER8E apart from POWER7 and POWER8. Also, the previos patch implemented multiple PVR mask support per CPU class so POWER7 class now covers both POWER7 and POWER7+ CPUs, same is valid for POWER8/8E. This removes POWER7+ and POWER8E classes. This replaces references to POWER7P/POWER8E families with POWER7/POWER8 families. Signed-off-by: Alexey Kardashevskiy Signed-off-by: Alexander Graf --- target-ppc/cpu-models.c | 4 +-- target-ppc/translate_init.c | 73 ++------------------------------------------- 2 files changed, 4 insertions(+), 73 deletions(-) diff --git a/target-ppc/cpu-models.c b/target-ppc/cpu-models.c index c9112e9cd8..52ac6ec156 100644 --- a/target-ppc/cpu-models.c +++ b/target-ppc/cpu-models.c @@ -1135,9 +1135,9 @@ #endif POWERPC_DEF("POWER7_v2.3", CPU_POWERPC_POWER7_v23, POWER7, "POWER7 v2.3") - POWERPC_DEF("POWER7+_v2.1", CPU_POWERPC_POWER7P_v21, POWER7P, + POWERPC_DEF("POWER7+_v2.1", CPU_POWERPC_POWER7P_v21, POWER7, "POWER7+ v2.1") - POWERPC_DEF("POWER8E_v1.0", CPU_POWERPC_POWER8E_v10, POWER8E, + POWERPC_DEF("POWER8E_v1.0", CPU_POWERPC_POWER8E_v10, POWER8, "POWER8E v1.0") POWERPC_DEF("POWER8_v1.0", CPU_POWERPC_POWER8_v10, POWER8, "POWER8 v1.0") diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c index 2c9c27714b..5eacd46a52 100644 --- a/target-ppc/translate_init.c +++ b/target-ppc/translate_init.c @@ -8133,66 +8133,6 @@ POWERPC_FAMILY(POWER7)(ObjectClass *oc, void *data) pcc->interrupts_big_endian = ppc_cpu_interrupts_big_endian_lpcr; } -POWERPC_FAMILY(POWER7P)(ObjectClass *oc, void *data) -{ - DeviceClass *dc = DEVICE_CLASS(oc); - PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); - - dc->fw_name = "PowerPC,POWER7+"; - dc->desc = "POWER7+"; - dc->props = powerpc_servercpu_properties; - pcc->pvr_match = ppc_pvr_match_power7; - pcc->pcr_mask = PCR_COMPAT_2_05 | PCR_COMPAT_2_06; - pcc->init_proc = init_proc_POWER7; - pcc->check_pow = check_pow_nocheck; - pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB | - PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | - PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | - PPC_FLOAT_FRSQRTES | - PPC_FLOAT_STFIWX | - PPC_FLOAT_EXT | - PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | - PPC_MEM_SYNC | PPC_MEM_EIEIO | - PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | - PPC_64B | PPC_ALTIVEC | - PPC_SEGMENT_64B | PPC_SLBI | - PPC_POPCNTB | PPC_POPCNTWD; - pcc->insns_flags2 = PPC2_VSX | PPC2_DFP | PPC2_DBRX | PPC2_ISA205 | - PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 | - PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 | - PPC2_FP_TST_ISA206; - pcc->msr_mask = (1ull << MSR_SF) | - (1ull << MSR_VR) | - (1ull << MSR_VSX) | - (1ull << MSR_EE) | - (1ull << MSR_PR) | - (1ull << MSR_FP) | - (1ull << MSR_ME) | - (1ull << MSR_FE0) | - (1ull << MSR_SE) | - (1ull << MSR_DE) | - (1ull << MSR_FE1) | - (1ull << MSR_IR) | - (1ull << MSR_DR) | - (1ull << MSR_PMM) | - (1ull << MSR_RI) | - (1ull << MSR_LE); - pcc->mmu_model = POWERPC_MMU_2_06; -#if defined(CONFIG_SOFTMMU) - pcc->handle_mmu_fault = ppc_hash64_handle_mmu_fault; -#endif - pcc->excp_model = POWERPC_EXCP_POWER7; - pcc->bus_model = PPC_FLAGS_INPUT_POWER7; - pcc->bfd_mach = bfd_mach_ppc64; - pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | - POWERPC_FLAG_BE | POWERPC_FLAG_PMM | - POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR | - POWERPC_FLAG_VSX; - pcc->l1_dcache_size = 0x8000; - pcc->l1_icache_size = 0x8000; - pcc->interrupts_big_endian = ppc_cpu_interrupts_big_endian_lpcr; -} - static void init_proc_POWER8(CPUPPCState *env) { init_proc_book3s_64(env, BOOK3S_CPU_POWER8); @@ -8209,13 +8149,13 @@ static bool ppc_pvr_match_power8(PowerPCCPUClass *pcc, uint32_t pvr) return false; } -POWERPC_FAMILY(POWER8E)(ObjectClass *oc, void *data) +POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data) { DeviceClass *dc = DEVICE_CLASS(oc); PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); dc->fw_name = "PowerPC,POWER8"; - dc->desc = "POWER8E"; + dc->desc = "POWER8"; dc->props = powerpc_servercpu_properties; pcc->pvr_match = ppc_pvr_match_power8; pcc->pcr_mask = PCR_COMPAT_2_05 | PCR_COMPAT_2_06; @@ -8271,15 +8211,6 @@ POWERPC_FAMILY(POWER8E)(ObjectClass *oc, void *data) pcc->l1_icache_size = 0x8000; pcc->interrupts_big_endian = ppc_cpu_interrupts_big_endian_lpcr; } - -POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data) -{ - DeviceClass *dc = DEVICE_CLASS(oc); - - ppc_POWER8E_cpu_family_class_init(oc, data); - - dc->desc = "POWER8"; -} #endif /* defined (TARGET_PPC64) */ -- cgit 1.4.1 From 0c6ab8c988830d3fe01c4ee88100a95ea95c49fa Mon Sep 17 00:00:00 2001 From: Cole Robinson Date: Fri, 4 Jul 2014 15:43:18 -0400 Subject: PPC: e500: Actually install u-boot.e500 Signed-off-by: Cole Robinson Signed-off-by: Alexander Graf --- Makefile | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/Makefile b/Makefile index 1eea0c418f..d6b9dc1ebe 100644 --- a/Makefile +++ b/Makefile @@ -344,7 +344,8 @@ multiboot.bin linuxboot.bin kvmvapic.bin \ s390-zipl.rom \ s390-ccw.img \ spapr-rtas.bin slof.bin \ -palcode-clipper +palcode-clipper \ +u-boot.e500 else BLOBS= endif -- cgit 1.4.1