From 6e6d5fb4b928f09b46d0fa99830d75cddb22f73b Mon Sep 17 00:00:00 2001 From: Gustavo Romero Date: Tue, 26 Aug 2025 11:21:28 +0100 Subject: target/arm: Implement FEAT_TCR2 and enable with -cpu max Add FEAT_TCR2, which introduces the TCR2_EL1 and TCR2_EL2 registers. These registers are extensions of the TCR_ELx registers and provide top-level control of the EL10 and EL20 translation regimes. Signed-off-by: Gustavo Romero Signed-off-by: Richard Henderson Reviewed-by: Richard Henderson Message-id: 20250727074202.83141-5-richard.henderson@linaro.org Message-ID: <20250711140828.1714666-5-gustavo.romero@linaro.org> Reviewed-by: Richard Henderson [rth: Remove FEAT_MEC code; handle SCR and HCRX enable bits.] Signed-off-by: Richard Henderson Signed-off-by: Peter Maydell --- docs/system/arm/emulation.rst | 1 + 1 file changed, 1 insertion(+) (limited to 'docs/system/arm') diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst index 66043b0747..1c597d8673 100644 --- a/docs/system/arm/emulation.rst +++ b/docs/system/arm/emulation.rst @@ -149,6 +149,7 @@ the following architecture extensions: - FEAT_SPECRES (Speculation restriction instructions) - FEAT_SSBS (Speculative Store Bypass Safe) - FEAT_SSBS2 (MRS and MSR instructions for SSBS version 2) +- FEAT_TCR2 (Support for TCR2_ELx) - FEAT_TGran16K (Support for 16KB memory translation granule size at stage 1) - FEAT_TGran4K (Support for 4KB memory translation granule size at stage 1) - FEAT_TGran64K (Support for 64KB memory translation granule size at stage 1) -- cgit 1.4.1