From aaf4e67f0efce49ca5cf2648706bf0b834d2535f Mon Sep 17 00:00:00 2001 From: Cédric Le Goater Date: Thu, 22 Sep 2016 18:13:05 +0100 Subject: palmetto-bmc: rename the Aspeed board file to aspeed.c MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit We plan to add more Aspeed boards to this file. There are no changes in the code. Signed-off-by: Cédric Le Goater Reviewed-by: Andrew Jeffery Reviewed-by: Peter Maydell Message-id: 1473438177-26079-5-git-send-email-clg@kaod.org Signed-off-by: Peter Maydell --- hw/arm/aspeed.c | 106 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 106 insertions(+) create mode 100644 hw/arm/aspeed.c (limited to 'hw/arm/aspeed.c') diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c new file mode 100644 index 0000000000..43191210f3 --- /dev/null +++ b/hw/arm/aspeed.c @@ -0,0 +1,106 @@ +/* + * OpenPOWER Palmetto BMC + * + * Andrew Jeffery + * + * Copyright 2016 IBM Corp. + * + * This code is licensed under the GPL version 2 or later. See + * the COPYING file in the top-level directory. + */ + +#include "qemu/osdep.h" +#include "qapi/error.h" +#include "qemu-common.h" +#include "cpu.h" +#include "exec/address-spaces.h" +#include "hw/arm/arm.h" +#include "hw/arm/aspeed_soc.h" +#include "hw/boards.h" +#include "qemu/log.h" +#include "sysemu/block-backend.h" +#include "sysemu/blockdev.h" + +static struct arm_boot_info palmetto_bmc_binfo = { + .board_id = -1, /* device-tree-only board */ + .nb_cpus = 1, +}; + +typedef struct PalmettoBMCState { + AspeedSoCState soc; + MemoryRegion ram; +} PalmettoBMCState; + +static void palmetto_bmc_init_flashes(AspeedSMCState *s, const char *flashtype, + Error **errp) +{ + int i ; + + for (i = 0; i < s->num_cs; ++i) { + AspeedSMCFlash *fl = &s->flashes[i]; + DriveInfo *dinfo = drive_get_next(IF_MTD); + qemu_irq cs_line; + + /* + * FIXME: check that we are not using a flash module exceeding + * the controller segment size + */ + fl->flash = ssi_create_slave_no_init(s->spi, flashtype); + if (dinfo) { + qdev_prop_set_drive(fl->flash, "drive", blk_by_legacy_dinfo(dinfo), + errp); + } + qdev_init_nofail(fl->flash); + + cs_line = qdev_get_gpio_in_named(fl->flash, SSI_GPIO_CS, 0); + sysbus_connect_irq(SYS_BUS_DEVICE(s), i + 1, cs_line); + } +} + +static void palmetto_bmc_init(MachineState *machine) +{ + PalmettoBMCState *bmc; + AspeedSoCClass *sc; + + bmc = g_new0(PalmettoBMCState, 1); + object_initialize(&bmc->soc, (sizeof(bmc->soc)), "ast2400-a0"); + object_property_add_child(OBJECT(machine), "soc", OBJECT(&bmc->soc), + &error_abort); + + sc = ASPEED_SOC_GET_CLASS(&bmc->soc); + + memory_region_allocate_system_memory(&bmc->ram, NULL, "ram", ram_size); + memory_region_add_subregion(get_system_memory(), sc->info->sdram_base, + &bmc->ram); + object_property_add_const_link(OBJECT(&bmc->soc), "ram", OBJECT(&bmc->ram), + &error_abort); + object_property_set_int(OBJECT(&bmc->soc), 0x120CE416, "hw-strap1", + &error_abort); + object_property_set_bool(OBJECT(&bmc->soc), true, "realized", + &error_abort); + + palmetto_bmc_init_flashes(&bmc->soc.smc, "n25q256a", &error_abort); + palmetto_bmc_init_flashes(&bmc->soc.spi, "mx25l25635e", &error_abort); + + palmetto_bmc_binfo.kernel_filename = machine->kernel_filename; + palmetto_bmc_binfo.initrd_filename = machine->initrd_filename; + palmetto_bmc_binfo.kernel_cmdline = machine->kernel_cmdline; + palmetto_bmc_binfo.ram_size = ram_size; + palmetto_bmc_binfo.loader_start = sc->info->sdram_base; + + arm_load_kernel(ARM_CPU(first_cpu), &palmetto_bmc_binfo); +} + +static void palmetto_bmc_machine_init(MachineClass *mc) +{ + mc->desc = "OpenPOWER Palmetto BMC"; + mc->init = palmetto_bmc_init; + mc->max_cpus = 1; + mc->no_sdcard = 1; + mc->no_floppy = 1; + mc->no_cdrom = 1; + mc->no_sdcard = 1; + mc->no_parallel = 1; +} + +DEFINE_MACHINE("palmetto-bmc", palmetto_bmc_machine_init); -- cgit 1.4.1 From 74fb1f38071f557154558141ed8d3a57914b0996 Mon Sep 17 00:00:00 2001 From: Cédric Le Goater Date: Thu, 22 Sep 2016 18:13:05 +0100 Subject: palmetto-bmc: replace palmetto_bmc with aspeed MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This is mostly a name replacement to prepare ground for other SoCs specificities. It also adds a TypeInfo struct for the palmetto-bmc board with a custom initialization for the same reason. Signed-off-by: Cédric Le Goater Reviewed-by: Andrew Jeffery Reviewed-by: Peter Maydell Message-id: 1473438177-26079-6-git-send-email-clg@kaod.org Signed-off-by: Peter Maydell --- hw/arm/aspeed.c | 54 ++++++++++++++++++++++++++++++++++++------------------ 1 file changed, 36 insertions(+), 18 deletions(-) (limited to 'hw/arm/aspeed.c') diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c index 43191210f3..3b901eaa6f 100644 --- a/hw/arm/aspeed.c +++ b/hw/arm/aspeed.c @@ -21,17 +21,17 @@ #include "sysemu/block-backend.h" #include "sysemu/blockdev.h" -static struct arm_boot_info palmetto_bmc_binfo = { +static struct arm_boot_info aspeed_board_binfo = { .board_id = -1, /* device-tree-only board */ .nb_cpus = 1, }; -typedef struct PalmettoBMCState { +typedef struct AspeedBoardState { AspeedSoCState soc; MemoryRegion ram; -} PalmettoBMCState; +} AspeedBoardState; -static void palmetto_bmc_init_flashes(AspeedSMCState *s, const char *flashtype, +static void aspeed_board_init_flashes(AspeedSMCState *s, const char *flashtype, Error **errp) { int i ; @@ -57,12 +57,12 @@ static void palmetto_bmc_init_flashes(AspeedSMCState *s, const char *flashtype, } } -static void palmetto_bmc_init(MachineState *machine) +static void aspeed_board_init(MachineState *machine) { - PalmettoBMCState *bmc; + AspeedBoardState *bmc; AspeedSoCClass *sc; - bmc = g_new0(PalmettoBMCState, 1); + bmc = g_new0(AspeedBoardState, 1); object_initialize(&bmc->soc, (sizeof(bmc->soc)), "ast2400-a0"); object_property_add_child(OBJECT(machine), "soc", OBJECT(&bmc->soc), &error_abort); @@ -79,21 +79,28 @@ static void palmetto_bmc_init(MachineState *machine) object_property_set_bool(OBJECT(&bmc->soc), true, "realized", &error_abort); - palmetto_bmc_init_flashes(&bmc->soc.smc, "n25q256a", &error_abort); - palmetto_bmc_init_flashes(&bmc->soc.spi, "mx25l25635e", &error_abort); + aspeed_board_init_flashes(&bmc->soc.smc, "n25q256a", &error_abort); + aspeed_board_init_flashes(&bmc->soc.spi, "mx25l25635e", &error_abort); + + aspeed_board_binfo.kernel_filename = machine->kernel_filename; + aspeed_board_binfo.initrd_filename = machine->initrd_filename; + aspeed_board_binfo.kernel_cmdline = machine->kernel_cmdline; + aspeed_board_binfo.ram_size = ram_size; + aspeed_board_binfo.loader_start = sc->info->sdram_base; - palmetto_bmc_binfo.kernel_filename = machine->kernel_filename; - palmetto_bmc_binfo.initrd_filename = machine->initrd_filename; - palmetto_bmc_binfo.kernel_cmdline = machine->kernel_cmdline; - palmetto_bmc_binfo.ram_size = ram_size; - palmetto_bmc_binfo.loader_start = sc->info->sdram_base; + arm_load_kernel(ARM_CPU(first_cpu), &aspeed_board_binfo); +} - arm_load_kernel(ARM_CPU(first_cpu), &palmetto_bmc_binfo); +static void palmetto_bmc_init(MachineState *machine) +{ + aspeed_board_init(machine); } -static void palmetto_bmc_machine_init(MachineClass *mc) +static void palmetto_bmc_class_init(ObjectClass *oc, void *data) { - mc->desc = "OpenPOWER Palmetto BMC"; + MachineClass *mc = MACHINE_CLASS(oc); + + mc->desc = "OpenPOWER Palmetto BMC (ARM926EJ-S)"; mc->init = palmetto_bmc_init; mc->max_cpus = 1; mc->no_sdcard = 1; @@ -103,4 +110,15 @@ static void palmetto_bmc_machine_init(MachineClass *mc) mc->no_parallel = 1; } -DEFINE_MACHINE("palmetto-bmc", palmetto_bmc_machine_init); +static const TypeInfo palmetto_bmc_type = { + .name = MACHINE_TYPE_NAME("palmetto-bmc"), + .parent = TYPE_MACHINE, + .class_init = palmetto_bmc_class_init, +}; + +static void aspeed_machine_init(void) +{ + type_register_static(&palmetto_bmc_type); +} + +type_init(aspeed_machine_init) -- cgit 1.4.1 From c3ba99f723af21f27d0f6c839443b218c75b0dc0 Mon Sep 17 00:00:00 2001 From: Cédric Le Goater Date: Thu, 22 Sep 2016 18:13:05 +0100 Subject: palmetto-bmc: add board specific configuration MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit aspeed_board_init() now uses a board identifier to customize some values specific to the board. Signed-off-by: Cédric Le Goater Reviewed-by: Andrew Jeffery Reviewed-by: Peter Maydell Message-id: 1473438177-26079-7-git-send-email-clg@kaod.org Signed-off-by: Peter Maydell --- hw/arm/aspeed.c | 22 ++++++++++++++++++---- 1 file changed, 18 insertions(+), 4 deletions(-) (limited to 'hw/arm/aspeed.c') diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c index 3b901eaa6f..b4eb8049af 100644 --- a/hw/arm/aspeed.c +++ b/hw/arm/aspeed.c @@ -31,6 +31,19 @@ typedef struct AspeedBoardState { MemoryRegion ram; } AspeedBoardState; +typedef struct AspeedBoardConfig { + const char *soc_name; + uint32_t hw_strap1; +} AspeedBoardConfig; + +enum { + PALMETTO_BMC, +}; + +static const AspeedBoardConfig aspeed_boards[] = { + [PALMETTO_BMC] = { "ast2400-a0", 0x120CE416 }, +}; + static void aspeed_board_init_flashes(AspeedSMCState *s, const char *flashtype, Error **errp) { @@ -57,13 +70,14 @@ static void aspeed_board_init_flashes(AspeedSMCState *s, const char *flashtype, } } -static void aspeed_board_init(MachineState *machine) +static void aspeed_board_init(MachineState *machine, + const AspeedBoardConfig *cfg) { AspeedBoardState *bmc; AspeedSoCClass *sc; bmc = g_new0(AspeedBoardState, 1); - object_initialize(&bmc->soc, (sizeof(bmc->soc)), "ast2400-a0"); + object_initialize(&bmc->soc, (sizeof(bmc->soc)), cfg->soc_name); object_property_add_child(OBJECT(machine), "soc", OBJECT(&bmc->soc), &error_abort); @@ -74,7 +88,7 @@ static void aspeed_board_init(MachineState *machine) &bmc->ram); object_property_add_const_link(OBJECT(&bmc->soc), "ram", OBJECT(&bmc->ram), &error_abort); - object_property_set_int(OBJECT(&bmc->soc), 0x120CE416, "hw-strap1", + object_property_set_int(OBJECT(&bmc->soc), cfg->hw_strap1, "hw-strap1", &error_abort); object_property_set_bool(OBJECT(&bmc->soc), true, "realized", &error_abort); @@ -93,7 +107,7 @@ static void aspeed_board_init(MachineState *machine) static void palmetto_bmc_init(MachineState *machine) { - aspeed_board_init(machine); + aspeed_board_init(machine, &aspeed_boards[PALMETTO_BMC]); } static void palmetto_bmc_class_init(ObjectClass *oc, void *data) -- cgit 1.4.1 From 8da33ef757d6d49b41432a22e4ab357652ec0e14 Mon Sep 17 00:00:00 2001 From: Cédric Le Goater Date: Thu, 22 Sep 2016 18:13:05 +0100 Subject: hw/misc: use macros to define hw-strap1 register on the AST2400 Aspeed SoC MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This gives some explanation behind the magic number 0x120CE416. Signed-off-by: Cédric Le Goater Reviewed-by: Andrew Jeffery Reviewed-by: Peter Maydell Message-id: 1473438177-26079-8-git-send-email-clg@kaod.org Signed-off-by: Peter Maydell --- hw/arm/aspeed.c | 15 +++++- include/hw/misc/aspeed_scu.h | 118 +++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 132 insertions(+), 1 deletion(-) (limited to 'hw/arm/aspeed.c') diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c index b4eb8049af..c08213c04e 100644 --- a/hw/arm/aspeed.c +++ b/hw/arm/aspeed.c @@ -40,8 +40,21 @@ enum { PALMETTO_BMC, }; +#define PALMETTO_BMC_HW_STRAP1 ( \ + SCU_AST2400_HW_STRAP_DRAM_SIZE(DRAM_SIZE_256MB) | \ + SCU_AST2400_HW_STRAP_DRAM_CONFIG(2 /* DDR3 with CL=6, CWL=5 */) | \ + SCU_AST2400_HW_STRAP_ACPI_DIS | \ + SCU_AST2400_HW_STRAP_SET_CLK_SOURCE(AST2400_CLK_48M_IN) | \ + SCU_HW_STRAP_VGA_CLASS_CODE | \ + SCU_HW_STRAP_LPC_RESET_PIN | \ + SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_M_S_EN) | \ + SCU_AST2400_HW_STRAP_SET_CPU_AHB_RATIO(AST2400_CPU_AHB_RATIO_2_1) | \ + SCU_HW_STRAP_SPI_WIDTH | \ + SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) | \ + SCU_AST2400_HW_STRAP_BOOT_MODE(AST2400_SPI_BOOT)) + static const AspeedBoardConfig aspeed_boards[] = { - [PALMETTO_BMC] = { "ast2400-a0", 0x120CE416 }, + [PALMETTO_BMC] = { "ast2400-a0", PALMETTO_BMC_HW_STRAP1 }, }; static void aspeed_board_init_flashes(AspeedSMCState *s, const char *flashtype, diff --git a/include/hw/misc/aspeed_scu.h b/include/hw/misc/aspeed_scu.h index fdfd982288..4d3e770cec 100644 --- a/include/hw/misc/aspeed_scu.h +++ b/include/hw/misc/aspeed_scu.h @@ -36,4 +36,122 @@ typedef struct AspeedSCUState { extern bool is_supported_silicon_rev(uint32_t silicon_rev); +/* + * Extracted from Aspeed SDK v00.03.21. Fixes and extra definitions + * were added. + * + * Original header file : + * arch/arm/mach-aspeed/include/mach/regs-scu.h + * + * Copyright (C) 2012-2020 ASPEED Technology Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * History : + * 1. 2012/12/29 Ryan Chen Create + */ + +/* Hardware Strapping Register definition (for Aspeed AST2400 SOC) + * + * 31:29 Software defined strapping registers + * 28:27 DRAM size setting (for VGA driver use) + * 26:24 DRAM configuration setting + * 23 Enable 25 MHz reference clock input + * 22 Enable GPIOE pass-through mode + * 21 Enable GPIOD pass-through mode + * 20 Disable LPC to decode SuperIO 0x2E/0x4E address + * 19 Disable ACPI function + * 23,18 Clock source selection + * 17 Enable BMC 2nd boot watchdog timer + * 16 SuperIO configuration address selection + * 15 VGA Class Code selection + * 14 Enable LPC dedicated reset pin function + * 13:12 SPI mode selection + * 11:10 CPU/AHB clock frequency ratio selection + * 9:8 H-PLL default clock frequency selection + * 7 Define MAC#2 interface + * 6 Define MAC#1 interface + * 5 Enable VGA BIOS ROM + * 4 Boot flash memory extended option + * 3:2 VGA memory size selection + * 1:0 BMC CPU boot code selection + */ +#define SCU_AST2400_HW_STRAP_SW_DEFINE(x) ((x) << 29) +#define SCU_AST2400_HW_STRAP_SW_DEFINE_MASK (0x7 << 29) + +#define SCU_AST2400_HW_STRAP_DRAM_SIZE(x) ((x) << 27) +#define SCU_AST2400_HW_STRAP_DRAM_SIZE_MASK (0x3 << 27) +#define DRAM_SIZE_64MB 0 +#define DRAM_SIZE_128MB 1 +#define DRAM_SIZE_256MB 2 +#define DRAM_SIZE_512MB 3 + +#define SCU_AST2400_HW_STRAP_DRAM_CONFIG(x) ((x) << 24) +#define SCU_AST2400_HW_STRAP_DRAM_CONFIG_MASK (0x7 << 24) + +#define SCU_HW_STRAP_GPIOE_PT_EN (0x1 << 22) +#define SCU_HW_STRAP_GPIOD_PT_EN (0x1 << 21) +#define SCU_HW_STRAP_LPC_DEC_SUPER_IO (0x1 << 20) +#define SCU_AST2400_HW_STRAP_ACPI_DIS (0x1 << 19) + +/* bit 23, 18 [1,0] */ +#define SCU_AST2400_HW_STRAP_SET_CLK_SOURCE(x) (((((x) & 0x3) >> 1) << 23) \ + | (((x) & 0x1) << 18)) +#define SCU_AST2400_HW_STRAP_GET_CLK_SOURCE(x) (((((x) >> 23) & 0x1) << 1) \ + | (((x) >> 18) & 0x1)) +#define SCU_AST2400_HW_STRAP_CLK_SOURCE_MASK ((0x1 << 23) | (0x1 << 18)) +#define AST2400_CLK_25M_IN (0x1 << 23) +#define AST2400_CLK_24M_IN 0 +#define AST2400_CLK_48M_IN 1 +#define AST2400_CLK_25M_IN_24M_USB_CKI 2 +#define AST2400_CLK_25M_IN_48M_USB_CKI 3 + +#define SCU_HW_STRAP_2ND_BOOT_WDT (0x1 << 17) +#define SCU_HW_STRAP_SUPER_IO_CONFIG (0x1 << 16) +#define SCU_HW_STRAP_VGA_CLASS_CODE (0x1 << 15) +#define SCU_HW_STRAP_LPC_RESET_PIN (0x1 << 14) + +#define SCU_HW_STRAP_SPI_MODE(x) ((x) << 12) +#define SCU_HW_STRAP_SPI_MODE_MASK (0x3 << 12) +#define SCU_HW_STRAP_SPI_DIS 0 +#define SCU_HW_STRAP_SPI_MASTER 1 +#define SCU_HW_STRAP_SPI_M_S_EN 2 +#define SCU_HW_STRAP_SPI_PASS_THROUGH 3 + +#define SCU_AST2400_HW_STRAP_SET_CPU_AHB_RATIO(x) ((x) << 10) +#define SCU_AST2400_HW_STRAP_GET_CPU_AHB_RATIO(x) (((x) >> 10) & 3) +#define SCU_AST2400_HW_STRAP_CPU_AHB_RATIO_MASK (0x3 << 10) +#define AST2400_CPU_AHB_RATIO_1_1 0 +#define AST2400_CPU_AHB_RATIO_2_1 1 +#define AST2400_CPU_AHB_RATIO_4_1 2 +#define AST2400_CPU_AHB_RATIO_3_1 3 + +#define SCU_AST2400_HW_STRAP_GET_H_PLL_CLK(x) (((x) >> 8) & 0x3) +#define SCU_AST2400_HW_STRAP_H_PLL_CLK_MASK (0x3 << 8) +#define AST2400_CPU_384MHZ 0 +#define AST2400_CPU_360MHZ 1 +#define AST2400_CPU_336MHZ 2 +#define AST2400_CPU_408MHZ 3 + +#define SCU_HW_STRAP_MAC1_RGMII (0x1 << 7) +#define SCU_HW_STRAP_MAC0_RGMII (0x1 << 6) +#define SCU_HW_STRAP_VGA_BIOS_ROM (0x1 << 5) +#define SCU_HW_STRAP_SPI_WIDTH (0x1 << 4) + +#define SCU_HW_STRAP_VGA_SIZE_GET(x) (((x) >> 2) & 0x3) +#define SCU_HW_STRAP_VGA_MASK (0x3 << 2) +#define SCU_HW_STRAP_VGA_SIZE_SET(x) ((x) << 2) +#define VGA_8M_DRAM 0 +#define VGA_16M_DRAM 1 +#define VGA_32M_DRAM 2 +#define VGA_64M_DRAM 3 + +#define SCU_AST2400_HW_STRAP_BOOT_MODE(x) (x) +#define AST2400_NOR_BOOT 0 +#define AST2400_NAND_BOOT 1 +#define AST2400_SPI_BOOT 2 +#define AST2400_DIS_BOOT 3 + #endif /* ASPEED_SCU_H */ -- cgit 1.4.1 From 9a7c17501187061e60102164bd84509a4d854d1d Mon Sep 17 00:00:00 2001 From: Cédric Le Goater Date: Thu, 22 Sep 2016 18:13:06 +0100 Subject: arm: add support for an ast2500 evaluation board MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The ast2500 eval board has a hardware strapping register value of 0xF100C2E6 which we use for a definition of AST2500_EVB_HW_STRAP1 below. Signed-off-by: Cédric Le Goater Reviewed-by: Andrew Jeffery Reviewed-by: Peter Maydell Message-id: 1473438177-26079-10-git-send-email-clg@kaod.org Signed-off-by: Peter Maydell --- hw/arm/aspeed.c | 37 +++++++++++++++++++++++++++++++++++++ 1 file changed, 37 insertions(+) (limited to 'hw/arm/aspeed.c') diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c index c08213c04e..2af9fe9344 100644 --- a/hw/arm/aspeed.c +++ b/hw/arm/aspeed.c @@ -38,6 +38,7 @@ typedef struct AspeedBoardConfig { enum { PALMETTO_BMC, + AST2500_EVB, }; #define PALMETTO_BMC_HW_STRAP1 ( \ @@ -53,8 +54,19 @@ enum { SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) | \ SCU_AST2400_HW_STRAP_BOOT_MODE(AST2400_SPI_BOOT)) +#define AST2500_EVB_HW_STRAP1 (( \ + AST2500_HW_STRAP1_DEFAULTS | \ + SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \ + SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \ + SCU_AST2500_HW_STRAP_UART_DEBUG | \ + SCU_AST2500_HW_STRAP_DDR4_ENABLE | \ + SCU_HW_STRAP_MAC1_RGMII | \ + SCU_HW_STRAP_MAC0_RGMII) & \ + ~SCU_HW_STRAP_2ND_BOOT_WDT) + static const AspeedBoardConfig aspeed_boards[] = { [PALMETTO_BMC] = { "ast2400-a0", PALMETTO_BMC_HW_STRAP1 }, + [AST2500_EVB] = { "ast2500-a1", AST2500_EVB_HW_STRAP1 }, }; static void aspeed_board_init_flashes(AspeedSMCState *s, const char *flashtype, @@ -143,9 +155,34 @@ static const TypeInfo palmetto_bmc_type = { .class_init = palmetto_bmc_class_init, }; +static void ast2500_evb_init(MachineState *machine) +{ + aspeed_board_init(machine, &aspeed_boards[AST2500_EVB]); +} + +static void ast2500_evb_class_init(ObjectClass *oc, void *data) +{ + MachineClass *mc = MACHINE_CLASS(oc); + + mc->desc = "Aspeed AST2500 EVB (ARM1176)"; + mc->init = ast2500_evb_init; + mc->max_cpus = 1; + mc->no_sdcard = 1; + mc->no_floppy = 1; + mc->no_cdrom = 1; + mc->no_parallel = 1; +} + +static const TypeInfo ast2500_evb_type = { + .name = MACHINE_TYPE_NAME("ast2500-evb"), + .parent = TYPE_MACHINE, + .class_init = ast2500_evb_class_init, +}; + static void aspeed_machine_init(void) { type_register_static(&palmetto_bmc_type); + type_register_static(&ast2500_evb_type); } type_init(aspeed_machine_init) -- cgit 1.4.1 From 67077e301454069fd849de755e9d04da70474304 Mon Sep 17 00:00:00 2001 From: Cédric Le Goater Date: Thu, 22 Sep 2016 18:13:06 +0100 Subject: palmetto-bmc: remove extra no_sdcard assignement MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Cédric Le Goater Reviewed-by: Andrew Jeffery Reviewed-by: Peter Maydell Message-id: 1473438177-26079-11-git-send-email-clg@kaod.org Signed-off-by: Peter Maydell --- hw/arm/aspeed.c | 1 - 1 file changed, 1 deletion(-) (limited to 'hw/arm/aspeed.c') diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c index 2af9fe9344..9013d35a67 100644 --- a/hw/arm/aspeed.c +++ b/hw/arm/aspeed.c @@ -145,7 +145,6 @@ static void palmetto_bmc_class_init(ObjectClass *oc, void *data) mc->no_sdcard = 1; mc->no_floppy = 1; mc->no_cdrom = 1; - mc->no_sdcard = 1; mc->no_parallel = 1; } -- cgit 1.4.1 From c6c7cfb01a00be0553f6694bbe71d45fc5e068c8 Mon Sep 17 00:00:00 2001 From: Cédric Le Goater Date: Thu, 22 Sep 2016 18:13:06 +0100 Subject: aspeed: add a ram_size property to the memory controller MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Configure the size of the RAM of the SOC using a property to propagate the value down to the memory controller from the board level. Signed-off-by: Cédric Le Goater Reviewed-by: Andrew Jeffery Message-id: 1473438177-26079-14-git-send-email-clg@kaod.org Signed-off-by: Peter Maydell --- hw/arm/aspeed.c | 2 ++ hw/arm/aspeed_soc.c | 2 ++ hw/misc/aspeed_sdmc.c | 23 +++++++++++++---------- include/hw/misc/aspeed_sdmc.h | 1 + 4 files changed, 18 insertions(+), 10 deletions(-) (limited to 'hw/arm/aspeed.c') diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c index 9013d35a67..562bbb2533 100644 --- a/hw/arm/aspeed.c +++ b/hw/arm/aspeed.c @@ -113,6 +113,8 @@ static void aspeed_board_init(MachineState *machine, &bmc->ram); object_property_add_const_link(OBJECT(&bmc->soc), "ram", OBJECT(&bmc->ram), &error_abort); + object_property_set_int(OBJECT(&bmc->soc), ram_size, "ram-size", + &error_abort); object_property_set_int(OBJECT(&bmc->soc), cfg->hw_strap1, "hw-strap1", &error_abort); object_property_set_bool(OBJECT(&bmc->soc), true, "realized", diff --git a/hw/arm/aspeed_soc.c b/hw/arm/aspeed_soc.c index 93bc7bb66e..c0a3102058 100644 --- a/hw/arm/aspeed_soc.c +++ b/hw/arm/aspeed_soc.c @@ -113,6 +113,8 @@ static void aspeed_soc_init(Object *obj) qdev_set_parent_bus(DEVICE(&s->sdmc), sysbus_get_default()); qdev_prop_set_uint32(DEVICE(&s->sdmc), "silicon-rev", sc->info->silicon_rev); + object_property_add_alias(obj, "ram-size", OBJECT(&s->sdmc), + "ram-size", &error_abort); } static void aspeed_soc_realize(DeviceState *dev, Error **errp) diff --git a/hw/misc/aspeed_sdmc.c b/hw/misc/aspeed_sdmc.c index 20bcdb52c4..8830dc084c 100644 --- a/hw/misc/aspeed_sdmc.c +++ b/hw/misc/aspeed_sdmc.c @@ -140,9 +140,9 @@ static const MemoryRegionOps aspeed_sdmc_ops = { .valid.max_access_size = 4, }; -static int ast2400_rambits(void) +static int ast2400_rambits(AspeedSDMCState *s) { - switch (ram_size >> 20) { + switch (s->ram_size >> 20) { case 64: return ASPEED_SDMC_DRAM_64MB; case 128: @@ -156,14 +156,15 @@ static int ast2400_rambits(void) } /* use a common default */ - error_report("warning: Invalid RAM size 0x" RAM_ADDR_FMT - ". Using default 256M", ram_size); + error_report("warning: Invalid RAM size 0x%" PRIx64 + ". Using default 256M", s->ram_size); + s->ram_size = 256 << 20; return ASPEED_SDMC_DRAM_256MB; } -static int ast2500_rambits(void) +static int ast2500_rambits(AspeedSDMCState *s) { - switch (ram_size >> 20) { + switch (s->ram_size >> 20) { case 128: return ASPEED_SDMC_AST2500_128MB; case 256: @@ -177,8 +178,9 @@ static int ast2500_rambits(void) } /* use a common default */ - error_report("warning: Invalid RAM size 0x" RAM_ADDR_FMT - ". Using default 512M", ram_size); + error_report("warning: Invalid RAM size 0x%" PRIx64 + ". Using default 512M", s->ram_size); + s->ram_size = 512 << 20; return ASPEED_SDMC_AST2500_512MB; } @@ -222,11 +224,11 @@ static void aspeed_sdmc_realize(DeviceState *dev, Error **errp) switch (s->silicon_rev) { case AST2400_A0_SILICON_REV: - s->ram_bits = ast2400_rambits(); + s->ram_bits = ast2400_rambits(s); break; case AST2500_A0_SILICON_REV: case AST2500_A1_SILICON_REV: - s->ram_bits = ast2500_rambits(); + s->ram_bits = ast2500_rambits(s); break; default: g_assert_not_reached(); @@ -249,6 +251,7 @@ static const VMStateDescription vmstate_aspeed_sdmc = { static Property aspeed_sdmc_properties[] = { DEFINE_PROP_UINT32("silicon-rev", AspeedSDMCState, silicon_rev, 0), + DEFINE_PROP_UINT64("ram-size", AspeedSDMCState, ram_size, 0), DEFINE_PROP_END_OF_LIST(), }; diff --git a/include/hw/misc/aspeed_sdmc.h b/include/hw/misc/aspeed_sdmc.h index df7dce0edd..551c8afdf4 100644 --- a/include/hw/misc/aspeed_sdmc.h +++ b/include/hw/misc/aspeed_sdmc.h @@ -26,6 +26,7 @@ typedef struct AspeedSDMCState { uint32_t regs[ASPEED_SDMC_NR_REGS]; uint32_t silicon_rev; uint32_t ram_bits; + uint64_t ram_size; } AspeedSDMCState; -- cgit 1.4.1 From de46f5f46c1bb169045432a8208a9e10a662b55d Mon Sep 17 00:00:00 2001 From: Cédric Le Goater Date: Thu, 22 Sep 2016 18:13:06 +0100 Subject: aspeed: allocate RAM after the memory controller has checked the size MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit If the RAM size is invalid, the memory controller will use a default value. Signed-off-by: Cédric Le Goater Reviewed-by: Andrew Jeffery Message-id: 1473438177-26079-15-git-send-email-clg@kaod.org Signed-off-by: Peter Maydell --- hw/arm/aspeed.c | 18 +++++++++++++----- 1 file changed, 13 insertions(+), 5 deletions(-) (limited to 'hw/arm/aspeed.c') diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c index 562bbb2533..6b18c7f172 100644 --- a/hw/arm/aspeed.c +++ b/hw/arm/aspeed.c @@ -108,11 +108,6 @@ static void aspeed_board_init(MachineState *machine, sc = ASPEED_SOC_GET_CLASS(&bmc->soc); - memory_region_allocate_system_memory(&bmc->ram, NULL, "ram", ram_size); - memory_region_add_subregion(get_system_memory(), sc->info->sdram_base, - &bmc->ram); - object_property_add_const_link(OBJECT(&bmc->soc), "ram", OBJECT(&bmc->ram), - &error_abort); object_property_set_int(OBJECT(&bmc->soc), ram_size, "ram-size", &error_abort); object_property_set_int(OBJECT(&bmc->soc), cfg->hw_strap1, "hw-strap1", @@ -120,6 +115,19 @@ static void aspeed_board_init(MachineState *machine, object_property_set_bool(OBJECT(&bmc->soc), true, "realized", &error_abort); + /* + * Allocate RAM after the memory controller has checked the size + * was valid. If not, a default value is used. + */ + ram_size = object_property_get_int(OBJECT(&bmc->soc), "ram-size", + &error_abort); + + memory_region_allocate_system_memory(&bmc->ram, NULL, "ram", ram_size); + memory_region_add_subregion(get_system_memory(), sc->info->sdram_base, + &bmc->ram); + object_property_add_const_link(OBJECT(&bmc->soc), "ram", OBJECT(&bmc->ram), + &error_abort); + aspeed_board_init_flashes(&bmc->soc.smc, "n25q256a", &error_abort); aspeed_board_init_flashes(&bmc->soc.spi, "mx25l25635e", &error_abort); -- cgit 1.4.1