From 0e5803dfbce6cf056fe15b3b5cb31fe8519a6f6e Mon Sep 17 00:00:00 2001 From: Cédric Le Goater Date: Mon, 17 Oct 2016 19:22:16 +0100 Subject: aspeed: rename the smc object to fmc MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The Aspeed SoC has three different types of SMC (Static Memory Controller) controllers: the SMC (legacy), the FMC (the new one) and the SPI for the host PNOR. The FMC and the SPI models are now converging on the AST2500 SoC and the SMC, which was still available on the AST2400 SoC, was removed. The Aspeed SoC does not provide support for the legacy SMC controller. So, let's rename the 'smc' object to 'fmc' to clarify its nature. Signed-off-by: Cédric Le Goater Reviewed-by: Andrew Jeffery Message-id: 1474977462-28032-2-git-send-email-clg@kaod.org Signed-off-by: Peter Maydell --- hw/arm/aspeed_soc.c | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) (limited to 'hw/arm/aspeed_soc.c') diff --git a/hw/arm/aspeed_soc.c b/hw/arm/aspeed_soc.c index c0a3102058..479c0d2039 100644 --- a/hw/arm/aspeed_soc.c +++ b/hw/arm/aspeed_soc.c @@ -100,9 +100,9 @@ static void aspeed_soc_init(Object *obj) object_property_add_alias(obj, "hw-strap2", OBJECT(&s->scu), "hw-strap2", &error_abort); - object_initialize(&s->smc, sizeof(s->smc), "aspeed.smc.fmc"); - object_property_add_child(obj, "smc", OBJECT(&s->smc), NULL); - qdev_set_parent_bus(DEVICE(&s->smc), sysbus_get_default()); + object_initialize(&s->fmc, sizeof(s->fmc), "aspeed.smc.fmc"); + object_property_add_child(obj, "fmc", OBJECT(&s->fmc), NULL); + qdev_set_parent_bus(DEVICE(&s->fmc), sysbus_get_default()); object_initialize(&s->spi, sizeof(s->spi), "aspeed.smc.spi"); object_property_add_child(obj, "spi", OBJECT(&s->spi), NULL); @@ -178,17 +178,17 @@ static void aspeed_soc_realize(DeviceState *dev, Error **errp) sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c), 0, qdev_get_gpio_in(DEVICE(&s->vic), 12)); - /* SMC */ - object_property_set_int(OBJECT(&s->smc), 1, "num-cs", &err); - object_property_set_bool(OBJECT(&s->smc), true, "realized", &local_err); + /* FMC */ + object_property_set_int(OBJECT(&s->fmc), 1, "num-cs", &err); + object_property_set_bool(OBJECT(&s->fmc), true, "realized", &local_err); error_propagate(&err, local_err); if (err) { error_propagate(errp, err); return; } - sysbus_mmio_map(SYS_BUS_DEVICE(&s->smc), 0, ASPEED_SOC_FMC_BASE); - sysbus_mmio_map(SYS_BUS_DEVICE(&s->smc), 1, ASPEED_SOC_FMC_FLASH_BASE); - sysbus_connect_irq(SYS_BUS_DEVICE(&s->smc), 0, + sysbus_mmio_map(SYS_BUS_DEVICE(&s->fmc), 0, ASPEED_SOC_FMC_BASE); + sysbus_mmio_map(SYS_BUS_DEVICE(&s->fmc), 1, ASPEED_SOC_FMC_FLASH_BASE); + sysbus_connect_irq(SYS_BUS_DEVICE(&s->fmc), 0, qdev_get_gpio_in(DEVICE(&s->vic), 19)); /* SPI */ -- cgit 1.4.1 From dcb834447f7b22b08a918e2266e5751035fbfc83 Mon Sep 17 00:00:00 2001 From: Cédric Le Goater Date: Mon, 17 Oct 2016 19:22:16 +0100 Subject: aspeed: move the flash module mapping address under the controller definition MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This will ease the definition of the new controllers for the AST2500 SoC and also ease the support of the segment registers, which provide a way to reconfigure the mapping window of each slave. Signed-off-by: Cédric Le Goater Reviewed-by: Andrew Jeffery Message-id: 1474977462-28032-3-git-send-email-clg@kaod.org Signed-off-by: Peter Maydell --- hw/arm/aspeed_soc.c | 9 ++++----- hw/ssi/aspeed_smc.c | 15 +++++++++++---- include/hw/ssi/aspeed_smc.h | 3 ++- 3 files changed, 17 insertions(+), 10 deletions(-) (limited to 'hw/arm/aspeed_soc.c') diff --git a/hw/arm/aspeed_soc.c b/hw/arm/aspeed_soc.c index 479c0d2039..80ad7322bd 100644 --- a/hw/arm/aspeed_soc.c +++ b/hw/arm/aspeed_soc.c @@ -31,9 +31,6 @@ #define ASPEED_SOC_TIMER_BASE 0x1E782000 #define ASPEED_SOC_I2C_BASE 0x1E78A000 -#define ASPEED_SOC_FMC_FLASH_BASE 0x20000000 -#define ASPEED_SOC_SPI_FLASH_BASE 0x30000000 - static const int uart_irqs[] = { 9, 32, 33, 34, 10 }; static const int timer_irqs[] = { 16, 17, 18, 35, 36, 37, 38, 39, }; @@ -187,7 +184,8 @@ static void aspeed_soc_realize(DeviceState *dev, Error **errp) return; } sysbus_mmio_map(SYS_BUS_DEVICE(&s->fmc), 0, ASPEED_SOC_FMC_BASE); - sysbus_mmio_map(SYS_BUS_DEVICE(&s->fmc), 1, ASPEED_SOC_FMC_FLASH_BASE); + sysbus_mmio_map(SYS_BUS_DEVICE(&s->fmc), 1, + s->fmc.ctrl->flash_window_base); sysbus_connect_irq(SYS_BUS_DEVICE(&s->fmc), 0, qdev_get_gpio_in(DEVICE(&s->vic), 19)); @@ -200,7 +198,8 @@ static void aspeed_soc_realize(DeviceState *dev, Error **errp) return; } sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi), 0, ASPEED_SOC_SPI_BASE); - sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi), 1, ASPEED_SOC_SPI_FLASH_BASE); + sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi), 1, + s->spi.ctrl->flash_window_base); /* SDMC - SDRAM Memory Controller */ object_property_set_bool(OBJECT(&s->sdmc), true, "realized", &err); diff --git a/hw/ssi/aspeed_smc.c b/hw/ssi/aspeed_smc.c index d319e04a27..84c18299de 100644 --- a/hw/ssi/aspeed_smc.c +++ b/hw/ssi/aspeed_smc.c @@ -127,6 +127,10 @@ #define R_SPI_MISC_CTRL (0x10 / 4) #define R_SPI_TIMINGS (0x14 / 4) +#define ASPEED_SOC_SMC_FLASH_BASE 0x10000000 +#define ASPEED_SOC_FMC_FLASH_BASE 0x20000000 +#define ASPEED_SOC_SPI_FLASH_BASE 0x30000000 + /* * Default segments mapping addresses and size for each slave per * controller. These can be changed when board is initialized with the @@ -151,11 +155,14 @@ static const AspeedSegments aspeed_segments_spi[] = { static const AspeedSMCController controllers[] = { { "aspeed.smc.smc", R_CONF, R_CE_CTRL, R_CTRL0, R_TIMINGS, - CONF_ENABLE_W0, 5, aspeed_segments_legacy, 0x6000000 }, + CONF_ENABLE_W0, 5, aspeed_segments_legacy, + ASPEED_SOC_SMC_FLASH_BASE, 0x6000000 }, { "aspeed.smc.fmc", R_CONF, R_CE_CTRL, R_CTRL0, R_TIMINGS, - CONF_ENABLE_W0, 5, aspeed_segments_fmc, 0x10000000 }, + CONF_ENABLE_W0, 5, aspeed_segments_fmc, + ASPEED_SOC_FMC_FLASH_BASE, 0x10000000 }, { "aspeed.smc.spi", R_SPI_CONF, 0xff, R_SPI_CTRL0, R_SPI_TIMINGS, - SPI_CONF_ENABLE_W0, 1, aspeed_segments_spi, 0x10000000 }, + SPI_CONF_ENABLE_W0, 1, aspeed_segments_spi, + ASPEED_SOC_SPI_FLASH_BASE, 0x10000000 }, }; static uint64_t aspeed_smc_flash_default_read(void *opaque, hwaddr addr, @@ -395,7 +402,7 @@ static void aspeed_smc_realize(DeviceState *dev, Error **errp) memory_region_init_io(&s->mmio_flash, OBJECT(s), &aspeed_smc_flash_default_ops, s, name, - s->ctrl->mapping_window_size); + s->ctrl->flash_window_size); sysbus_init_mmio(sbd, &s->mmio_flash); s->flashes = g_new0(AspeedSMCFlash, s->num_cs); diff --git a/include/hw/ssi/aspeed_smc.h b/include/hw/ssi/aspeed_smc.h index def3b4507e..bdfbcc0ffa 100644 --- a/include/hw/ssi/aspeed_smc.h +++ b/include/hw/ssi/aspeed_smc.h @@ -42,7 +42,8 @@ typedef struct AspeedSMCController { uint8_t conf_enable_w0; uint8_t max_slaves; const AspeedSegments *segments; - uint32_t mapping_window_size; + hwaddr flash_window_base; + uint32_t flash_window_size; } AspeedSMCController; typedef struct AspeedSMCFlash { -- cgit 1.4.1 From dbcabeeb54e9101307cf6225b9311a3ceaab7d1a Mon Sep 17 00:00:00 2001 From: Cédric Le Goater Date: Mon, 17 Oct 2016 19:22:16 +0100 Subject: aspeed: extend the number of host SPI controllers MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The AST2500 SoC has two. Let's prepare ground for the next changes which will add the required definitions for the second host SPI controller. Signed-off-by: Cédric Le Goater Reviewed-by: Andrew Jeffery Message-id: 1474977462-28032-4-git-send-email-clg@kaod.org Signed-off-by: Peter Maydell --- hw/arm/aspeed.c | 2 +- hw/arm/aspeed_soc.c | 44 +++++++++++++++++++++++++++++--------------- include/hw/arm/aspeed_soc.h | 6 +++++- 3 files changed, 35 insertions(+), 17 deletions(-) (limited to 'hw/arm/aspeed_soc.c') diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c index 4bb33cbb5e..c7206fda6d 100644 --- a/hw/arm/aspeed.c +++ b/hw/arm/aspeed.c @@ -129,7 +129,7 @@ static void aspeed_board_init(MachineState *machine, &error_abort); aspeed_board_init_flashes(&bmc->soc.fmc, "n25q256a", &error_abort); - aspeed_board_init_flashes(&bmc->soc.spi, "mx25l25635e", &error_abort); + aspeed_board_init_flashes(&bmc->soc.spi[0], "mx25l25635e", &error_abort); aspeed_board_binfo.kernel_filename = machine->kernel_filename; aspeed_board_binfo.initrd_filename = machine->initrd_filename; diff --git a/hw/arm/aspeed_soc.c b/hw/arm/aspeed_soc.c index 80ad7322bd..b3103f3373 100644 --- a/hw/arm/aspeed_soc.c +++ b/hw/arm/aspeed_soc.c @@ -37,10 +37,17 @@ static const int timer_irqs[] = { 16, 17, 18, 35, 36, 37, 38, 39, }; #define AST2400_SDRAM_BASE 0x40000000 #define AST2500_SDRAM_BASE 0x80000000 +static const hwaddr aspeed_soc_ast2400_spi_bases[] = { ASPEED_SOC_SPI_BASE }; + +static const hwaddr aspeed_soc_ast2500_spi_bases[] = { ASPEED_SOC_SPI_BASE }; + static const AspeedSoCInfo aspeed_socs[] = { - { "ast2400-a0", "arm926", AST2400_A0_SILICON_REV, AST2400_SDRAM_BASE }, - { "ast2400", "arm926", AST2400_A0_SILICON_REV, AST2400_SDRAM_BASE }, - { "ast2500-a1", "arm1176", AST2500_A1_SILICON_REV, AST2500_SDRAM_BASE }, + { "ast2400-a0", "arm926", AST2400_A0_SILICON_REV, AST2400_SDRAM_BASE, + 1, aspeed_soc_ast2400_spi_bases }, + { "ast2400", "arm926", AST2400_A0_SILICON_REV, AST2400_SDRAM_BASE, + 1, aspeed_soc_ast2400_spi_bases }, + { "ast2500-a1", "arm1176", AST2500_A1_SILICON_REV, AST2500_SDRAM_BASE, + 1, aspeed_soc_ast2500_spi_bases }, }; /* @@ -72,6 +79,7 @@ static void aspeed_soc_init(Object *obj) { AspeedSoCState *s = ASPEED_SOC(obj); AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); + int i; s->cpu = cpu_arm_init(sc->info->cpu_model); @@ -101,9 +109,11 @@ static void aspeed_soc_init(Object *obj) object_property_add_child(obj, "fmc", OBJECT(&s->fmc), NULL); qdev_set_parent_bus(DEVICE(&s->fmc), sysbus_get_default()); - object_initialize(&s->spi, sizeof(s->spi), "aspeed.smc.spi"); - object_property_add_child(obj, "spi", OBJECT(&s->spi), NULL); - qdev_set_parent_bus(DEVICE(&s->spi), sysbus_get_default()); + for (i = 0; i < sc->info->spis_num; i++) { + object_initialize(&s->spi[i], sizeof(s->spi[i]), "aspeed.smc.spi"); + object_property_add_child(obj, "spi", OBJECT(&s->spi[i]), NULL); + qdev_set_parent_bus(DEVICE(&s->spi[i]), sysbus_get_default()); + } object_initialize(&s->sdmc, sizeof(s->sdmc), TYPE_ASPEED_SDMC); object_property_add_child(obj, "sdmc", OBJECT(&s->sdmc), NULL); @@ -118,6 +128,7 @@ static void aspeed_soc_realize(DeviceState *dev, Error **errp) { int i; AspeedSoCState *s = ASPEED_SOC(dev); + AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); Error *err = NULL, *local_err = NULL; /* IO space */ @@ -190,16 +201,19 @@ static void aspeed_soc_realize(DeviceState *dev, Error **errp) qdev_get_gpio_in(DEVICE(&s->vic), 19)); /* SPI */ - object_property_set_int(OBJECT(&s->spi), 1, "num-cs", &err); - object_property_set_bool(OBJECT(&s->spi), true, "realized", &local_err); - error_propagate(&err, local_err); - if (err) { - error_propagate(errp, err); - return; + for (i = 0; i < sc->info->spis_num; i++) { + object_property_set_int(OBJECT(&s->spi[i]), 1, "num-cs", &err); + object_property_set_bool(OBJECT(&s->spi[i]), true, "realized", + &local_err); + error_propagate(&err, local_err); + if (err) { + error_propagate(errp, err); + return; + } + sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 0, sc->info->spi_bases[i]); + sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 1, + s->spi[i].ctrl->flash_window_base); } - sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi), 0, ASPEED_SOC_SPI_BASE); - sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi), 1, - s->spi.ctrl->flash_window_base); /* SDMC - SDRAM Memory Controller */ object_property_set_bool(OBJECT(&s->sdmc), true, "realized", &err); diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h index 7359e25fce..f26a9f0439 100644 --- a/include/hw/arm/aspeed_soc.h +++ b/include/hw/arm/aspeed_soc.h @@ -20,6 +20,8 @@ #include "hw/i2c/aspeed_i2c.h" #include "hw/ssi/aspeed_smc.h" +#define ASPEED_SPIS_NUM 2 + typedef struct AspeedSoCState { /*< private >*/ DeviceState parent; @@ -32,7 +34,7 @@ typedef struct AspeedSoCState { AspeedI2CState i2c; AspeedSCUState scu; AspeedSMCState fmc; - AspeedSMCState spi; + AspeedSMCState spi[ASPEED_SPIS_NUM]; AspeedSDMCState sdmc; } AspeedSoCState; @@ -44,6 +46,8 @@ typedef struct AspeedSoCInfo { const char *cpu_model; uint32_t silicon_rev; hwaddr sdram_base; + int spis_num; + const hwaddr *spi_bases; } AspeedSoCInfo; typedef struct AspeedSoCClass { -- cgit 1.4.1 From 6dc52326ccbb826c3b61aa1429001a79d34be1e3 Mon Sep 17 00:00:00 2001 From: Cédric Le Goater Date: Mon, 17 Oct 2016 19:22:16 +0100 Subject: aspeed: add support for the AST2500 SoC SMC controllers MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The SMC controllers on the Aspeed AST2500 SoC are very similar to the ones found on the AST2400. The differences are on the number of supported flash modules and their default mappings in the SoC address space. The Aspeed AST2500 has one SPI controller for the BMC firmware and two for the host firmware. All controllers have now the same set of registers compatible with the AST2400 FMC controller and the legacy 'SMC' controller is fully gone. We keep the FMC object to act as the BMC SPI controller and add a new SPI controller for the host. We also have to introduce new type names to handle the differences in the flash modules memory mappping. Signed-off-by: Cédric Le Goater Reviewed-by: Andrew Jeffery Message-id: 1474977462-28032-5-git-send-email-clg@kaod.org Signed-off-by: Peter Maydell --- hw/arm/aspeed_soc.c | 21 +++++++++++++++------ hw/ssi/aspeed_smc.c | 28 +++++++++++++++++++++++++++- include/hw/arm/aspeed_soc.h | 2 ++ 3 files changed, 44 insertions(+), 7 deletions(-) (limited to 'hw/arm/aspeed_soc.c') diff --git a/hw/arm/aspeed_soc.c b/hw/arm/aspeed_soc.c index b3103f3373..e14f5c217e 100644 --- a/hw/arm/aspeed_soc.c +++ b/hw/arm/aspeed_soc.c @@ -25,6 +25,7 @@ #define ASPEED_SOC_IOMEM_BASE 0x1E600000 #define ASPEED_SOC_FMC_BASE 0x1E620000 #define ASPEED_SOC_SPI_BASE 0x1E630000 +#define ASPEED_SOC_SPI2_BASE 0x1E631000 #define ASPEED_SOC_VIC_BASE 0x1E6C0000 #define ASPEED_SOC_SDMC_BASE 0x1E6E0000 #define ASPEED_SOC_SCU_BASE 0x1E6E2000 @@ -38,16 +39,23 @@ static const int timer_irqs[] = { 16, 17, 18, 35, 36, 37, 38, 39, }; #define AST2500_SDRAM_BASE 0x80000000 static const hwaddr aspeed_soc_ast2400_spi_bases[] = { ASPEED_SOC_SPI_BASE }; +static const char *aspeed_soc_ast2400_typenames[] = { "aspeed.smc.spi" }; -static const hwaddr aspeed_soc_ast2500_spi_bases[] = { ASPEED_SOC_SPI_BASE }; +static const hwaddr aspeed_soc_ast2500_spi_bases[] = { ASPEED_SOC_SPI_BASE, + ASPEED_SOC_SPI2_BASE}; +static const char *aspeed_soc_ast2500_typenames[] = { + "aspeed.smc.ast2500-spi1", "aspeed.smc.ast2500-spi2" }; static const AspeedSoCInfo aspeed_socs[] = { { "ast2400-a0", "arm926", AST2400_A0_SILICON_REV, AST2400_SDRAM_BASE, - 1, aspeed_soc_ast2400_spi_bases }, + 1, aspeed_soc_ast2400_spi_bases, + "aspeed.smc.fmc", aspeed_soc_ast2400_typenames }, { "ast2400", "arm926", AST2400_A0_SILICON_REV, AST2400_SDRAM_BASE, - 1, aspeed_soc_ast2400_spi_bases }, + 1, aspeed_soc_ast2400_spi_bases, + "aspeed.smc.fmc", aspeed_soc_ast2400_typenames }, { "ast2500-a1", "arm1176", AST2500_A1_SILICON_REV, AST2500_SDRAM_BASE, - 1, aspeed_soc_ast2500_spi_bases }, + 2, aspeed_soc_ast2500_spi_bases, + "aspeed.smc.ast2500-fmc", aspeed_soc_ast2500_typenames }, }; /* @@ -105,12 +113,13 @@ static void aspeed_soc_init(Object *obj) object_property_add_alias(obj, "hw-strap2", OBJECT(&s->scu), "hw-strap2", &error_abort); - object_initialize(&s->fmc, sizeof(s->fmc), "aspeed.smc.fmc"); + object_initialize(&s->fmc, sizeof(s->fmc), sc->info->fmc_typename); object_property_add_child(obj, "fmc", OBJECT(&s->fmc), NULL); qdev_set_parent_bus(DEVICE(&s->fmc), sysbus_get_default()); for (i = 0; i < sc->info->spis_num; i++) { - object_initialize(&s->spi[i], sizeof(s->spi[i]), "aspeed.smc.spi"); + object_initialize(&s->spi[i], sizeof(s->spi[i]), + sc->info->spi_typename[i]); object_property_add_child(obj, "spi", OBJECT(&s->spi[i]), NULL); qdev_set_parent_bus(DEVICE(&s->spi[i]), sysbus_get_default()); } diff --git a/hw/ssi/aspeed_smc.c b/hw/ssi/aspeed_smc.c index 84c18299de..21943f4e5d 100644 --- a/hw/ssi/aspeed_smc.c +++ b/hw/ssi/aspeed_smc.c @@ -130,6 +130,7 @@ #define ASPEED_SOC_SMC_FLASH_BASE 0x10000000 #define ASPEED_SOC_FMC_FLASH_BASE 0x20000000 #define ASPEED_SOC_SPI_FLASH_BASE 0x30000000 +#define ASPEED_SOC_SPI2_FLASH_BASE 0x38000000 /* * Default segments mapping addresses and size for each slave per @@ -142,7 +143,7 @@ static const AspeedSegments aspeed_segments_legacy[] = { }; static const AspeedSegments aspeed_segments_fmc[] = { - { 0x20000000, 64 * 1024 * 1024 }, + { 0x20000000, 64 * 1024 * 1024 }, /* start address is readonly */ { 0x24000000, 32 * 1024 * 1024 }, { 0x26000000, 32 * 1024 * 1024 }, { 0x28000000, 32 * 1024 * 1024 }, @@ -153,6 +154,22 @@ static const AspeedSegments aspeed_segments_spi[] = { { 0x30000000, 64 * 1024 * 1024 }, }; +static const AspeedSegments aspeed_segments_ast2500_fmc[] = { + { 0x20000000, 128 * 1024 * 1024 }, /* start address is readonly */ + { 0x28000000, 32 * 1024 * 1024 }, + { 0x2A000000, 32 * 1024 * 1024 }, +}; + +static const AspeedSegments aspeed_segments_ast2500_spi1[] = { + { 0x30000000, 32 * 1024 * 1024 }, /* start address is readonly */ + { 0x32000000, 96 * 1024 * 1024 }, /* end address is readonly */ +}; + +static const AspeedSegments aspeed_segments_ast2500_spi2[] = { + { 0x38000000, 32 * 1024 * 1024 }, /* start address is readonly */ + { 0x3A000000, 96 * 1024 * 1024 }, /* end address is readonly */ +}; + static const AspeedSMCController controllers[] = { { "aspeed.smc.smc", R_CONF, R_CE_CTRL, R_CTRL0, R_TIMINGS, CONF_ENABLE_W0, 5, aspeed_segments_legacy, @@ -163,6 +180,15 @@ static const AspeedSMCController controllers[] = { { "aspeed.smc.spi", R_SPI_CONF, 0xff, R_SPI_CTRL0, R_SPI_TIMINGS, SPI_CONF_ENABLE_W0, 1, aspeed_segments_spi, ASPEED_SOC_SPI_FLASH_BASE, 0x10000000 }, + { "aspeed.smc.ast2500-fmc", R_CONF, R_CE_CTRL, R_CTRL0, R_TIMINGS, + CONF_ENABLE_W0, 3, aspeed_segments_ast2500_fmc, + ASPEED_SOC_FMC_FLASH_BASE, 0x10000000 }, + { "aspeed.smc.ast2500-spi1", R_CONF, R_CE_CTRL, R_CTRL0, R_TIMINGS, + CONF_ENABLE_W0, 2, aspeed_segments_ast2500_spi1, + ASPEED_SOC_SPI_FLASH_BASE, 0x8000000 }, + { "aspeed.smc.ast2500-spi2", R_CONF, R_CE_CTRL, R_CTRL0, R_TIMINGS, + CONF_ENABLE_W0, 2, aspeed_segments_ast2500_spi2, + ASPEED_SOC_SPI2_FLASH_BASE, 0x8000000 }, }; static uint64_t aspeed_smc_flash_default_read(void *opaque, hwaddr addr, diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h index f26a9f0439..5406b498d7 100644 --- a/include/hw/arm/aspeed_soc.h +++ b/include/hw/arm/aspeed_soc.h @@ -48,6 +48,8 @@ typedef struct AspeedSoCInfo { hwaddr sdram_base; int spis_num; const hwaddr *spi_bases; + const char *fmc_typename; + const char **spi_typename; } AspeedSoCInfo; typedef struct AspeedSoCClass { -- cgit 1.4.1