From 4a04655c6bdeb1043a4b7477f54f76a3d6a3ec59 Mon Sep 17 00:00:00 2001 From: Samuel Tardieu Date: Sat, 6 Jan 2024 19:15:03 +0100 Subject: hw/arm/socs: configure priority bits for existing SOCs Update the number of priority bits for a number of existing SoCs according to their technical documentation: - STM32F100/F205/F405/L4x5: 4 bits - Stellaris (Sandstorm/Fury): 3 bits Signed-off-by: Samuel Tardieu Reviewed-by: Peter Maydell Message-id: 20240106181503.1746200-4-sam@rfc1149.net Signed-off-by: Peter Maydell --- hw/arm/stellaris.c | 2 ++ 1 file changed, 2 insertions(+) (limited to 'hw/arm/stellaris.c') diff --git a/hw/arm/stellaris.c b/hw/arm/stellaris.c index 729a8bf569..d18b1144af 100644 --- a/hw/arm/stellaris.c +++ b/hw/arm/stellaris.c @@ -47,6 +47,7 @@ #define BP_GAMEPAD 0x04 #define NUM_IRQ_LINES 64 +#define NUM_PRIO_BITS 3 typedef const struct { const char *name; @@ -1067,6 +1068,7 @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board) nvic = qdev_new(TYPE_ARMV7M); qdev_prop_set_uint32(nvic, "num-irq", NUM_IRQ_LINES); + qdev_prop_set_uint8(nvic, "num-prio-bits", NUM_PRIO_BITS); qdev_prop_set_string(nvic, "cpu-type", ms->cpu_type); qdev_prop_set_bit(nvic, "enable-bitband", true); qdev_connect_clock_in(nvic, "cpuclk", -- cgit 1.4.1