From 4a04655c6bdeb1043a4b7477f54f76a3d6a3ec59 Mon Sep 17 00:00:00 2001 From: Samuel Tardieu Date: Sat, 6 Jan 2024 19:15:03 +0100 Subject: hw/arm/socs: configure priority bits for existing SOCs Update the number of priority bits for a number of existing SoCs according to their technical documentation: - STM32F100/F205/F405/L4x5: 4 bits - Stellaris (Sandstorm/Fury): 3 bits Signed-off-by: Samuel Tardieu Reviewed-by: Peter Maydell Message-id: 20240106181503.1746200-4-sam@rfc1149.net Signed-off-by: Peter Maydell --- hw/arm/stm32l4x5_soc.c | 1 + 1 file changed, 1 insertion(+) (limited to 'hw/arm/stm32l4x5_soc.c') diff --git a/hw/arm/stm32l4x5_soc.c b/hw/arm/stm32l4x5_soc.c index 70609a6dac..159d5315c9 100644 --- a/hw/arm/stm32l4x5_soc.c +++ b/hw/arm/stm32l4x5_soc.c @@ -102,6 +102,7 @@ static void stm32l4x5_soc_realize(DeviceState *dev_soc, Error **errp) object_initialize_child(OBJECT(dev_soc), "armv7m", &s->armv7m, TYPE_ARMV7M); armv7m = DEVICE(&s->armv7m); qdev_prop_set_uint32(armv7m, "num-irq", 96); + qdev_prop_set_uint32(armv7m, "num-prio-bits", 4); qdev_prop_set_string(armv7m, "cpu-type", ARM_CPU_TYPE_NAME("cortex-m4")); qdev_prop_set_bit(armv7m, "enable-bitband", true); qdev_connect_clock_in(armv7m, "cpuclk", s->sysclk); -- cgit 1.4.1