From a55c910e0b18aee2f67b129f0046b53cb8c42f21 Mon Sep 17 00:00:00 2001 From: Peter Maydell Date: Fri, 4 Mar 2016 11:30:22 +0000 Subject: hw/intc/arm_gic.c: Implement GICv2 GICC_DIR The GICv2 introduces a new CPU interface register GICC_DIR, which allows an OS to split the "priority drop" and "deactivate interrupt" parts of interrupt completion. Implement this register. (Note that the register is at offset 0x1000 in the CPU interface, which means it is on a different 4K page from all the other registers.) Signed-off-by: Peter Maydell Reviewed-by: Sergey Fedorov Message-id: 1456854176-7813-1-git-send-email-peter.maydell@linaro.org --- hw/cpu/a15mpcore.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'hw/cpu/a15mpcore.c') diff --git a/hw/cpu/a15mpcore.c b/hw/cpu/a15mpcore.c index e9063ad6d3..a221b8fe7b 100644 --- a/hw/cpu/a15mpcore.c +++ b/hw/cpu/a15mpcore.c @@ -109,7 +109,7 @@ static void a15mp_priv_realize(DeviceState *dev, Error **errp) /* Memory map (addresses are offsets from PERIPHBASE): * 0x0000-0x0fff -- reserved * 0x1000-0x1fff -- GIC Distributor - * 0x2000-0x2fff -- GIC CPU interface + * 0x2000-0x3fff -- GIC CPU interface * 0x4000-0x4fff -- GIC virtual interface control (not modelled) * 0x5000-0x5fff -- GIC virtual interface control (not modelled) * 0x6000-0x7fff -- GIC virtual CPU interface (not modelled) -- cgit 1.4.1