From c2e6d7d8e7fc270a90c61944ef36574b1549ddcf Mon Sep 17 00:00:00 2001 From: Bernhard Beschow Date: Sat, 6 Jan 2024 14:25:45 +0100 Subject: hw/i386/x86: Fix PIC interrupt handling if APIC is globally disabled QEMU populates the apic_state attribute of x86 CPUs if supported by real hardware or if SMP is active. When handling interrupts, it just checks whether apic_state is populated to route the interrupt to the PIC or to the APIC. However, chapter 10.4.3 of [1] requires that: When IA32_APIC_BASE[11] is 0, the processor is functionally equivalent to an IA-32 processor without an on-chip APIC. This means that when apic_state is populated, QEMU needs to check for the MSR_IA32_APICBASE_ENABLE flag in addition. Implement this which fixes some real-world BIOSes. [1] Intel 64 and IA-32 Architectures Software Developer's Manual, Vol. 3A: System Programming Guide, Part 1 Signed-off-by: Bernhard Beschow Message-Id: <20240106132546.21248-3-shentey@gmail.com> Reviewed-by: Michael S. Tsirkin Signed-off-by: Michael S. Tsirkin --- hw/intc/apic_common.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) (limited to 'hw/intc/apic_common.c') diff --git a/hw/intc/apic_common.c b/hw/intc/apic_common.c index 16ab40a35f..d8fc1e2815 100644 --- a/hw/intc/apic_common.c +++ b/hw/intc/apic_common.c @@ -62,6 +62,19 @@ uint64_t cpu_get_apic_base(DeviceState *dev) } } +bool cpu_is_apic_enabled(DeviceState *dev) +{ + APICCommonState *s; + + if (!dev) { + return false; + } + + s = APIC_COMMON(dev); + + return s->apicbase & MSR_IA32_APICBASE_ENABLE; +} + void cpu_set_apic_tpr(DeviceState *dev, uint8_t val) { APICCommonState *s; -- cgit 1.4.1