From d89daa893f51280652032640d77a8bc1dea95bdd Mon Sep 17 00:00:00 2001 From: Jinjie Ruan Date: Fri, 19 Apr 2024 14:33:05 +0100 Subject: hw/intc/arm_gicv3: Implement NMI interrupt priority If GICD_CTLR_DS bit is zero and the NMI is non-secure, the NMI priority is higher than 0x80, otherwise it is higher than 0x0. And save the interrupt non-maskable property in hppi.nmi to deliver NMI exception. Since both GICR and GICD can deliver NMI, it is both necessary to check whether the pending irq is NMI in gicv3_redist_update_noirqset and gicv3_update_noirqset. Signed-off-by: Jinjie Ruan Reviewed-by: Richard Henderson Reviewed-by: Peter Maydell Message-id: 20240407081733.3231820-21-ruanjinjie@huawei.com Signed-off-by: Peter Maydell --- hw/intc/arm_gicv3_common.c | 3 +++ 1 file changed, 3 insertions(+) (limited to 'hw/intc/arm_gicv3_common.c') diff --git a/hw/intc/arm_gicv3_common.c b/hw/intc/arm_gicv3_common.c index 9810558b07..207f8417e1 100644 --- a/hw/intc/arm_gicv3_common.c +++ b/hw/intc/arm_gicv3_common.c @@ -536,8 +536,11 @@ static void arm_gicv3_common_reset_hold(Object *obj) memset(cs->gicr_ipriorityr, 0, sizeof(cs->gicr_ipriorityr)); cs->hppi.prio = 0xff; + cs->hppi.nmi = false; cs->hpplpi.prio = 0xff; + cs->hpplpi.nmi = false; cs->hppvlpi.prio = 0xff; + cs->hppvlpi.nmi = false; /* State in the CPU interface must *not* be reset here, because it * is part of the CPU's reset domain, not the GIC device's. -- cgit 1.4.1