From d407be0877d8397218c6b79e5ad8b25267f6f5f1 Mon Sep 17 00:00:00 2001 From: Philippe Mathieu-Daudé Date: Tue, 13 Feb 2024 08:20:43 +0100 Subject: hw/ide/ahci: Expose AHCIPCIState structure MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit In order to be able to QOM-embed a structure, we need its full definition. Move it from "ahci_internal.h" to the new "hw/ide/ahci-pci.h" header. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Michael S. Tsirkin Reviewed-by: Richard Henderson Message-Id: <20240213081201.78951-3-philmd@linaro.org> --- hw/mips/boston.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'hw/mips/boston.c') diff --git a/hw/mips/boston.c b/hw/mips/boston.c index 4e11ff6cd6..cbcefdd693 100644 --- a/hw/mips/boston.c +++ b/hw/mips/boston.c @@ -24,7 +24,7 @@ #include "hw/boards.h" #include "hw/char/serial.h" #include "hw/ide/pci.h" -#include "hw/ide/ahci.h" +#include "hw/ide/ahci-pci.h" #include "hw/loader.h" #include "hw/loader-fit.h" #include "hw/mips/bootloader.h" -- cgit 1.4.1 From 41c05b41e3b3c5b6b167c315d0f25eb355dcc326 Mon Sep 17 00:00:00 2001 From: Philippe Mathieu-Daudé Date: Tue, 13 Feb 2024 08:30:00 +0100 Subject: hw/ide/ahci: Rename AHCI PCI function as 'pdev' MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit We want to access AHCIPCIState::ahci field. In order to keep the code simple (avoiding &ahci->ahci), rename the current 'ahci' variable as 'pdev' Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Michael S. Tsirkin Reviewed-by: Richard Henderson Message-Id: <20240213081201.78951-4-philmd@linaro.org> --- hw/i386/pc_q35.c | 15 ++++++++------- hw/mips/boston.c | 10 +++++----- 2 files changed, 13 insertions(+), 12 deletions(-) (limited to 'hw/mips/boston.c') diff --git a/hw/i386/pc_q35.c b/hw/i386/pc_q35.c index 76b3b6032b..a89f900c4c 100644 --- a/hw/i386/pc_q35.c +++ b/hw/i386/pc_q35.c @@ -134,7 +134,6 @@ static void pc_q35_init(MachineState *machine) GSIState *gsi_state; ISABus *isa_bus; int i; - PCIDevice *ahci; ram_addr_t lowmem; DriveInfo *hd[MAX_SATA_PORTS]; MachineClass *mc = MACHINE_GET_CLASS(machine); @@ -292,16 +291,18 @@ static void pc_q35_init(MachineState *machine) 0xff0104); if (pcms->sata_enabled) { + PCIDevice *pdev; + /* ahci and SATA device, for q35 1 ahci controller is built-in */ - ahci = pci_create_simple_multifunction(host_bus, + pdev = pci_create_simple_multifunction(host_bus, PCI_DEVFN(ICH9_SATA1_DEV, ICH9_SATA1_FUNC), "ich9-ahci"); - idebus[0] = qdev_get_child_bus(DEVICE(ahci), "ide.0"); - idebus[1] = qdev_get_child_bus(DEVICE(ahci), "ide.1"); - g_assert(MAX_SATA_PORTS == ahci_get_num_ports(ahci)); - ide_drive_get(hd, ahci_get_num_ports(ahci)); - ahci_ide_create_devs(ahci, hd); + idebus[0] = qdev_get_child_bus(DEVICE(pdev), "ide.0"); + idebus[1] = qdev_get_child_bus(DEVICE(pdev), "ide.1"); + g_assert(MAX_SATA_PORTS == ahci_get_num_ports(pdev)); + ide_drive_get(hd, ahci_get_num_ports(pdev)); + ahci_ide_create_devs(pdev, hd); } else { idebus[0] = idebus[1] = NULL; } diff --git a/hw/mips/boston.c b/hw/mips/boston.c index cbcefdd693..0ec0b98066 100644 --- a/hw/mips/boston.c +++ b/hw/mips/boston.c @@ -677,7 +677,7 @@ static void boston_mach_init(MachineState *machine) MemoryRegion *flash, *ddr_low_alias, *lcd, *platreg; MemoryRegion *sys_mem = get_system_memory(); XilinxPCIEHost *pcie2; - PCIDevice *ahci; + PCIDevice *pdev; DriveInfo *hd[6]; Chardev *chr; int fw_size, fit_err; @@ -769,11 +769,11 @@ static void boston_mach_init(MachineState *machine) qemu_chr_fe_set_handlers(&s->lcd_display, NULL, NULL, boston_lcd_event, NULL, s, NULL, true); - ahci = pci_create_simple_multifunction(&PCI_BRIDGE(&pcie2->root)->sec_bus, + pdev = pci_create_simple_multifunction(&PCI_BRIDGE(&pcie2->root)->sec_bus, PCI_DEVFN(0, 0), TYPE_ICH9_AHCI); - g_assert(ARRAY_SIZE(hd) == ahci_get_num_ports(ahci)); - ide_drive_get(hd, ahci_get_num_ports(ahci)); - ahci_ide_create_devs(ahci, hd); + g_assert(ARRAY_SIZE(hd) == ahci_get_num_ports(pdev)); + ide_drive_get(hd, ahci_get_num_ports(pdev)); + ahci_ide_create_devs(pdev, hd); if (machine->firmware) { fw_size = load_image_targphys(machine->firmware, -- cgit 1.4.1 From e6097f186416df368a7f87a37f0a7fd25de587ba Mon Sep 17 00:00:00 2001 From: Philippe Mathieu-Daudé Date: Tue, 13 Feb 2024 08:31:45 +0100 Subject: hw/ide/ahci: Inline ahci_get_num_ports() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Introduce the 'ich9' variable and inline ahci_get_num_ports(). Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Michael S. Tsirkin Reviewed-by: Richard Henderson Message-Id: <20240213081201.78951-5-philmd@linaro.org> --- hw/i386/pc_q35.c | 6 ++++-- hw/ide/ahci.c | 8 -------- hw/mips/boston.c | 6 ++++-- include/hw/ide/ahci.h | 1 - 4 files changed, 8 insertions(+), 13 deletions(-) (limited to 'hw/mips/boston.c') diff --git a/hw/i386/pc_q35.c b/hw/i386/pc_q35.c index a89f900c4c..09e12418f9 100644 --- a/hw/i386/pc_q35.c +++ b/hw/i386/pc_q35.c @@ -292,16 +292,18 @@ static void pc_q35_init(MachineState *machine) if (pcms->sata_enabled) { PCIDevice *pdev; + AHCIPCIState *ich9; /* ahci and SATA device, for q35 1 ahci controller is built-in */ pdev = pci_create_simple_multifunction(host_bus, PCI_DEVFN(ICH9_SATA1_DEV, ICH9_SATA1_FUNC), "ich9-ahci"); + ich9 = ICH9_AHCI(pdev); idebus[0] = qdev_get_child_bus(DEVICE(pdev), "ide.0"); idebus[1] = qdev_get_child_bus(DEVICE(pdev), "ide.1"); - g_assert(MAX_SATA_PORTS == ahci_get_num_ports(pdev)); - ide_drive_get(hd, ahci_get_num_ports(pdev)); + g_assert(MAX_SATA_PORTS == ich9->ahci.ports); + ide_drive_get(hd, ich9->ahci.ports); ahci_ide_create_devs(pdev, hd); } else { idebus[0] = idebus[1] = NULL; diff --git a/hw/ide/ahci.c b/hw/ide/ahci.c index aa9381a7b2..8b97c6b0e7 100644 --- a/hw/ide/ahci.c +++ b/hw/ide/ahci.c @@ -1896,14 +1896,6 @@ static void sysbus_ahci_register_types(void) type_init(sysbus_ahci_register_types) -int32_t ahci_get_num_ports(PCIDevice *dev) -{ - AHCIPCIState *d = ICH9_AHCI(dev); - AHCIState *ahci = &d->ahci; - - return ahci->ports; -} - void ahci_ide_create_devs(PCIDevice *dev, DriveInfo **hd) { AHCIPCIState *d = ICH9_AHCI(dev); diff --git a/hw/mips/boston.c b/hw/mips/boston.c index 0ec0b98066..a6c7bc18ff 100644 --- a/hw/mips/boston.c +++ b/hw/mips/boston.c @@ -678,6 +678,7 @@ static void boston_mach_init(MachineState *machine) MemoryRegion *sys_mem = get_system_memory(); XilinxPCIEHost *pcie2; PCIDevice *pdev; + AHCIPCIState *ich9; DriveInfo *hd[6]; Chardev *chr; int fw_size, fit_err; @@ -771,8 +772,9 @@ static void boston_mach_init(MachineState *machine) pdev = pci_create_simple_multifunction(&PCI_BRIDGE(&pcie2->root)->sec_bus, PCI_DEVFN(0, 0), TYPE_ICH9_AHCI); - g_assert(ARRAY_SIZE(hd) == ahci_get_num_ports(pdev)); - ide_drive_get(hd, ahci_get_num_ports(pdev)); + ich9 = ICH9_AHCI(pdev); + g_assert(ARRAY_SIZE(hd) == ich9->ahci.ports); + ide_drive_get(hd, ich9->ahci.ports); ahci_ide_create_devs(pdev, hd); if (machine->firmware) { diff --git a/include/hw/ide/ahci.h b/include/hw/ide/ahci.h index 6818d02063..dbef377f3d 100644 --- a/include/hw/ide/ahci.h +++ b/include/hw/ide/ahci.h @@ -52,7 +52,6 @@ typedef struct AHCIState { } AHCIState; -int32_t ahci_get_num_ports(PCIDevice *dev); void ahci_ide_create_devs(PCIDevice *dev, DriveInfo **hd); #define TYPE_SYSBUS_AHCI "sysbus-ahci" -- cgit 1.4.1 From e2f8d28005acdfa4e7edd6c842c6e9527a901ba5 Mon Sep 17 00:00:00 2001 From: Philippe Mathieu-Daudé Date: Tue, 13 Feb 2024 08:34:27 +0100 Subject: hw/ide/ahci: Pass AHCI context to ahci_ide_create_devs() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Since ahci_ide_create_devs() is not PCI specific, pass it an AHCIState argument instead of PCIDevice. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Michael S. Tsirkin Reviewed-by: Richard Henderson Message-Id: <20240213081201.78951-6-philmd@linaro.org> --- hw/i386/pc_q35.c | 2 +- hw/ide/ahci.c | 5 +---- hw/mips/boston.c | 2 +- include/hw/ide/ahci.h | 2 +- 4 files changed, 4 insertions(+), 7 deletions(-) (limited to 'hw/mips/boston.c') diff --git a/hw/i386/pc_q35.c b/hw/i386/pc_q35.c index 09e12418f9..d346fa3b1d 100644 --- a/hw/i386/pc_q35.c +++ b/hw/i386/pc_q35.c @@ -304,7 +304,7 @@ static void pc_q35_init(MachineState *machine) idebus[1] = qdev_get_child_bus(DEVICE(pdev), "ide.1"); g_assert(MAX_SATA_PORTS == ich9->ahci.ports); ide_drive_get(hd, ich9->ahci.ports); - ahci_ide_create_devs(pdev, hd); + ahci_ide_create_devs(&ich9->ahci, hd); } else { idebus[0] = idebus[1] = NULL; } diff --git a/hw/ide/ahci.c b/hw/ide/ahci.c index 8b97c6b0e7..bac1871a31 100644 --- a/hw/ide/ahci.c +++ b/hw/ide/ahci.c @@ -1896,10 +1896,8 @@ static void sysbus_ahci_register_types(void) type_init(sysbus_ahci_register_types) -void ahci_ide_create_devs(PCIDevice *dev, DriveInfo **hd) +void ahci_ide_create_devs(AHCIState *ahci, DriveInfo **hd) { - AHCIPCIState *d = ICH9_AHCI(dev); - AHCIState *ahci = &d->ahci; int i; for (i = 0; i < ahci->ports; i++) { @@ -1908,5 +1906,4 @@ void ahci_ide_create_devs(PCIDevice *dev, DriveInfo **hd) } ide_bus_create_drive(&ahci->dev[i].port, 0, hd[i]); } - } diff --git a/hw/mips/boston.c b/hw/mips/boston.c index a6c7bc18ff..1b44fb354c 100644 --- a/hw/mips/boston.c +++ b/hw/mips/boston.c @@ -775,7 +775,7 @@ static void boston_mach_init(MachineState *machine) ich9 = ICH9_AHCI(pdev); g_assert(ARRAY_SIZE(hd) == ich9->ahci.ports); ide_drive_get(hd, ich9->ahci.ports); - ahci_ide_create_devs(pdev, hd); + ahci_ide_create_devs(&ich9->ahci, hd); if (machine->firmware) { fw_size = load_image_targphys(machine->firmware, diff --git a/include/hw/ide/ahci.h b/include/hw/ide/ahci.h index dbef377f3d..8cd55b1333 100644 --- a/include/hw/ide/ahci.h +++ b/include/hw/ide/ahci.h @@ -52,7 +52,7 @@ typedef struct AHCIState { } AHCIState; -void ahci_ide_create_devs(PCIDevice *dev, DriveInfo **hd); +void ahci_ide_create_devs(AHCIState *ahci, DriveInfo **hd); #define TYPE_SYSBUS_AHCI "sysbus-ahci" OBJECT_DECLARE_SIMPLE_TYPE(SysbusAHCIState, SYSBUS_AHCI) -- cgit 1.4.1