From 4de9b249d37c1b382cc3e5a21fad1b4a11cec2fa Mon Sep 17 00:00:00 2001 From: ths Date: Wed, 24 Jan 2007 01:47:51 +0000 Subject: Reworking MIPS interrupt handling, by Aurelien Jarno. git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2350 c046a42c-6fe2-441c-8c8c-71466251a162 --- hw/mips_int.c | 39 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 39 insertions(+) create mode 100644 hw/mips_int.c (limited to 'hw/mips_int.c') diff --git a/hw/mips_int.c b/hw/mips_int.c new file mode 100644 index 0000000000..93d599fc60 --- /dev/null +++ b/hw/mips_int.c @@ -0,0 +1,39 @@ +#include "vl.h" +#include "cpu.h" + +/* Raise IRQ to CPU if necessary. It must be called every time the active + IRQ may change */ +void cpu_mips_update_irq(CPUState *env) +{ + if ((env->CP0_Status & env->CP0_Cause & CP0Ca_IP_mask) && + (env->CP0_Status & (1 << CP0St_IE)) && + !(env->hflags & MIPS_HFLAG_EXL) && + !(env->hflags & MIPS_HFLAG_ERL) && + !(env->hflags & MIPS_HFLAG_DM)) { + if (! (env->interrupt_request & CPU_INTERRUPT_HARD)) { + cpu_interrupt(env, CPU_INTERRUPT_HARD); + } + } else { + cpu_reset_interrupt(env, CPU_INTERRUPT_HARD); + } +} + +void cpu_mips_irq_request(void *opaque, int irq, int level) +{ + CPUState *env = first_cpu; + + uint32_t mask; + + if (irq >= 16) + return; + + mask = 1 << (irq + CP0Ca_IP); + + if (level) { + env->CP0_Cause |= mask; + } else { + env->CP0_Cause &= ~mask; + } + cpu_mips_update_irq(env); +} + -- cgit 1.4.1