From 0aa2612a01f233a4a25fb89e8362baf6cf896be6 Mon Sep 17 00:00:00 2001 From: Cédric Le Goater Date: Wed, 2 Mar 2022 06:51:39 +0100 Subject: ppc/xive: Add support for PQ state bits offload MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The trigger message coming from a HW source contains a special bit informing the XIVE interrupt controller that the PQ bits have been checked at the source or not. Depending on the value, the IC can perform the check and the state transition locally using its own PQ state bits. The following changes add new accessors to the XiveRouter required to query and update the PQ state bits. This only applies to the PowerNV machine. sPAPR accessors are provided but the pSeries machine should not be concerned by such complex configuration for the moment. Reviewed-by: Daniel Henrique Barboza Signed-off-by: Cédric Le Goater --- hw/pci-host/pnv_phb4.c | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) (limited to 'hw/pci-host/pnv_phb4.c') diff --git a/hw/pci-host/pnv_phb4.c b/hw/pci-host/pnv_phb4.c index 5344a6d4a6..58498feace 100644 --- a/hw/pci-host/pnv_phb4.c +++ b/hw/pci-host/pnv_phb4.c @@ -1660,14 +1660,19 @@ static const char *pnv_phb4_root_bus_path(PCIHostState *host_bridge, return phb->bus_path; } -static void pnv_phb4_xive_notify(XiveNotifier *xf, uint32_t srcno) +static void pnv_phb4_xive_notify(XiveNotifier *xf, uint32_t srcno, + bool pq_checked) { PnvPHB4 *phb = PNV_PHB4(xf); uint64_t notif_port = phb->regs[PHB_INT_NOTIFY_ADDR >> 3]; uint32_t offset = phb->regs[PHB_INT_NOTIFY_INDEX >> 3]; - uint64_t data = XIVE_TRIGGER_PQ | offset | srcno; + uint64_t data = offset | srcno; MemTxResult result; + if (pq_checked) { + data |= XIVE_TRIGGER_PQ; + } + trace_pnv_phb4_xive_notify(notif_port, data); address_space_stq_be(&address_space_memory, notif_port, data, -- cgit 1.4.1