From 742cc269c7e67352ebeecc528b0ade547a24de72 Mon Sep 17 00:00:00 2001 From: Akihiko Odaki Date: Sat, 3 Feb 2024 19:11:09 +0900 Subject: target/riscv: Move misa_mxl_max to class misa_mxl_max is common for all instances of a RISC-V CPU class so they are better put into class. Signed-off-by: Akihiko Odaki Reviewed-by: Alistair Francis Message-ID: <20240203-riscv-v11-2-a23f4848a628@daynix.com> Signed-off-by: Alistair Francis --- hw/riscv/boot.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'hw/riscv/boot.c') diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c index 0ffca05189..12f9792245 100644 --- a/hw/riscv/boot.c +++ b/hw/riscv/boot.c @@ -36,7 +36,8 @@ bool riscv_is_32bit(RISCVHartArrayState *harts) { - return harts->harts[0].env.misa_mxl_max == MXL_RV32; + RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(&harts->harts[0]); + return mcc->misa_mxl_max == MXL_RV32; } /* -- cgit 1.4.1