From f436ecc3156dea7edce97e7c247e3667203f5c8b Mon Sep 17 00:00:00 2001 From: Alistair Francis Date: Mon, 30 Aug 2021 15:35:02 +1000 Subject: hw/intc: sifive_plic: Convert the PLIC to use RISC-V CPU GPIO lines MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Instead of using riscv_cpu_update_mip() let's instead use the new RISC-V CPU GPIO lines to set the external MIP bits. Signed-off-by: Alistair Francis Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Reviewed-by: Bin Meng Tested-by: Bin Meng Message-id: 0364190bfa935058a845c0fa1ecf650328840ad5.1630301632.git.alistair.francis@wdc.com --- hw/riscv/microchip_pfsoc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'hw/riscv/microchip_pfsoc.c') diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c index eb8e79e0a1..eef55f69fd 100644 --- a/hw/riscv/microchip_pfsoc.c +++ b/hw/riscv/microchip_pfsoc.c @@ -274,7 +274,7 @@ static void microchip_pfsoc_soc_realize(DeviceState *dev, Error **errp) /* PLIC */ s->plic = sifive_plic_create(memmap[MICROCHIP_PFSOC_PLIC].base, - plic_hart_config, 0, + plic_hart_config, ms->smp.cpus, 0, MICROCHIP_PFSOC_PLIC_NUM_SOURCES, MICROCHIP_PFSOC_PLIC_NUM_PRIORITIES, MICROCHIP_PFSOC_PLIC_PRIORITY_BASE, -- cgit 1.4.1