From 73f6ed97acdbf7aec72d368fd5e16c00e04ac172 Mon Sep 17 00:00:00 2001 From: Bin Meng Date: Tue, 1 Sep 2020 09:38:58 +0800 Subject: target/riscv: cpu: Set reset vector based on the configured property value MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Now that we have the newly introduced 'resetvec' property in the RISC-V CPU and HART, instead of hard-coding the reset vector addr in the CPU's instance_init(), move that to riscv_cpu_realize() based on the configured property value from the RISC-V machines. Signed-off-by: Bin Meng Reviewed-by: Alistair Francis Reviewed-by: Philippe Mathieu-Daudé Message-Id: <1598924352-89526-4-git-send-email-bmeng.cn@gmail.com> Signed-off-by: Alistair Francis --- hw/riscv/opentitan.c | 1 + 1 file changed, 1 insertion(+) (limited to 'hw/riscv/opentitan.c') diff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c index 23ba3b4bfc..0531bd879b 100644 --- a/hw/riscv/opentitan.c +++ b/hw/riscv/opentitan.c @@ -111,6 +111,7 @@ static void lowrisc_ibex_soc_realize(DeviceState *dev_soc, Error **errp) &error_abort); object_property_set_int(OBJECT(&s->cpus), "num-harts", ms->smp.cpus, &error_abort); + object_property_set_int(OBJECT(&s->cpus), "resetvec", 0x8090, &error_abort); sysbus_realize(SYS_BUS_DEVICE(&s->cpus), &error_abort); /* Boot ROM */ -- cgit 1.4.1