From 766bade2da0f9b1338cbe72aea114cd0922acfc5 Mon Sep 17 00:00:00 2001 From: Richard Henderson Date: Fri, 13 Dec 2024 16:43:40 +0000 Subject: hw/riscv: Constify all Property MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Reviewed-by: Daniel Henrique Barboza Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- hw/riscv/sifive_u.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'hw/riscv/sifive_u.c') diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index c5e74126b1..124ffd4842 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -936,7 +936,7 @@ static void sifive_u_soc_realize(DeviceState *dev, Error **errp) qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_QSPI2_IRQ)); } -static Property sifive_u_soc_props[] = { +static const Property sifive_u_soc_props[] = { DEFINE_PROP_UINT32("serial", SiFiveUSoCState, serial, OTP_SERIAL), DEFINE_PROP_STRING("cpu-type", SiFiveUSoCState, cpu_type), DEFINE_PROP_END_OF_LIST() -- cgit 1.4.1