From e883e9927ae667a2473c4a4ec666df53af1b34d9 Mon Sep 17 00:00:00 2001 From: Bin Meng Date: Sat, 7 Mar 2020 04:48:39 -0800 Subject: hw/riscv: Generate correct "mmu-type" for 32-bit machines 32-bit machine should have its CPU's "mmu-type" set to "riscv,sv32". Signed-off-by: Bin Meng Reviewed-by: Alistair Francis Message-id: 1583585319-26603-1-git-send-email-bmeng.cn@gmail.com Message-Id: <1583585319-26603-1-git-send-email-bmeng.cn@gmail.com> Signed-off-by: Alistair Francis --- hw/riscv/spike.c | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'hw/riscv/spike.c') diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c index 5053fe4590..98697a244e 100644 --- a/hw/riscv/spike.c +++ b/hw/riscv/spike.c @@ -102,7 +102,11 @@ static void create_fdt(SpikeState *s, const struct MemmapEntry *memmap, char *intc = g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu); char *isa = riscv_isa_string(&s->soc.harts[cpu]); qemu_fdt_add_subnode(fdt, nodename); +#if defined(TARGET_RISCV32) + qemu_fdt_setprop_string(fdt, nodename, "mmu-type", "riscv,sv32"); +#else qemu_fdt_setprop_string(fdt, nodename, "mmu-type", "riscv,sv48"); +#endif qemu_fdt_setprop_string(fdt, nodename, "riscv,isa", isa); qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv"); qemu_fdt_setprop_string(fdt, nodename, "status", "okay"); -- cgit 1.4.1 From 5b8a986350a9ee2d9d95a76c29017c3c603bb350 Mon Sep 17 00:00:00 2001 From: Anup Patel Date: Mon, 27 Apr 2020 13:36:43 +0530 Subject: hw/riscv/spike: Allow loading firmware separately using -bios option This patch extends Spike machine support to allow loading OpenSBI firmware (fw_jump.elf) separately using -bios option. Signed-off-by: Anup Patel Reviewed-by: Alistair Francis Message-id: 20200427080644.168461-3-anup.patel@wdc.com Message-Id: <20200427080644.168461-3-anup.patel@wdc.com> Signed-off-by: Alistair Francis --- hw/riscv/spike.c | 24 +++++++++++++++++++++++- 1 file changed, 23 insertions(+), 1 deletion(-) (limited to 'hw/riscv/spike.c') diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c index 98697a244e..e7908b88fe 100644 --- a/hw/riscv/spike.c +++ b/hw/riscv/spike.c @@ -45,6 +45,12 @@ #include +#if defined(TARGET_RISCV32) +# define BIOS_FILENAME "opensbi-riscv32-spike-fw_jump.elf" +#else +# define BIOS_FILENAME "opensbi-riscv64-spike-fw_jump.elf" +#endif + static const struct MemmapEntry { hwaddr base; hwaddr size; @@ -187,8 +193,24 @@ static void spike_board_init(MachineState *machine) memory_region_add_subregion(system_memory, memmap[SPIKE_MROM].base, mask_rom); + riscv_find_and_load_firmware(machine, BIOS_FILENAME, + memmap[SPIKE_DRAM].base, + htif_symbol_callback); + if (machine->kernel_filename) { - riscv_load_kernel(machine->kernel_filename, htif_symbol_callback); + uint64_t kernel_entry = riscv_load_kernel(machine->kernel_filename, + htif_symbol_callback); + + if (machine->initrd_filename) { + hwaddr start; + hwaddr end = riscv_load_initrd(machine->initrd_filename, + machine->ram_size, kernel_entry, + &start); + qemu_fdt_setprop_cell(s->fdt, "/chosen", + "linux,initrd-start", start); + qemu_fdt_setprop_cell(s->fdt, "/chosen", "linux,initrd-end", + end); + } } /* reset vector */ -- cgit 1.4.1 From 31e6d70485b1a719ca27e9a2d21f2a61ac497cdf Mon Sep 17 00:00:00 2001 From: Anup Patel Date: Mon, 27 Apr 2020 13:36:44 +0530 Subject: hw/riscv/spike: Allow more than one CPUs Currently, the upstream Spike ISA simulator allows more than one CPUs so we update QEMU Spike machine on similar lines to allow more than one CPUs. The maximum number of CPUs for QEMU Spike machine is kept same as QEMU Virt machine. Signed-off-by: Anup Patel Reviewed-by: Alistair Francis Message-id: 20200427080644.168461-4-anup.patel@wdc.com Message-Id: <20200427080644.168461-4-anup.patel@wdc.com> Signed-off-by: Alistair Francis --- hw/riscv/spike.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'hw/riscv/spike.c') diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c index e7908b88fe..d0c4843712 100644 --- a/hw/riscv/spike.c +++ b/hw/riscv/spike.c @@ -476,7 +476,7 @@ static void spike_machine_init(MachineClass *mc) { mc->desc = "RISC-V Spike Board"; mc->init = spike_board_init; - mc->max_cpus = 1; + mc->max_cpus = 8; mc->is_default = true; mc->default_cpu_type = SPIKE_V1_10_0_CPU; } -- cgit 1.4.1