From f436ecc3156dea7edce97e7c247e3667203f5c8b Mon Sep 17 00:00:00 2001 From: Alistair Francis Date: Mon, 30 Aug 2021 15:35:02 +1000 Subject: hw/intc: sifive_plic: Convert the PLIC to use RISC-V CPU GPIO lines MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Instead of using riscv_cpu_update_mip() let's instead use the new RISC-V CPU GPIO lines to set the external MIP bits. Signed-off-by: Alistair Francis Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Reviewed-by: Bin Meng Tested-by: Bin Meng Message-id: 0364190bfa935058a845c0fa1ecf650328840ad5.1630301632.git.alistair.francis@wdc.com --- hw/riscv/virt.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'hw/riscv/virt.c') diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index 5624adda58..47f1beb473 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -625,7 +625,7 @@ static void virt_machine_init(MachineState *machine) /* Per-socket PLIC */ s->plic[i] = sifive_plic_create( memmap[VIRT_PLIC].base + i * memmap[VIRT_PLIC].size, - plic_hart_config, base_hartid, + plic_hart_config, hart_count, base_hartid, VIRT_PLIC_NUM_SOURCES, VIRT_PLIC_NUM_PRIORITIES, VIRT_PLIC_PRIORITY_BASE, -- cgit 1.4.1