From 221389657aa77ced7a17936747f288193e321d3f Mon Sep 17 00:00:00 2001 From: BALATON Zoltan Date: Fri, 29 Oct 2021 23:02:09 +0200 Subject: hw/sh4: Coding style: Fix multi-line comments MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: BALATON Zoltan Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Yoshinori Sato Message-Id: <3f192c699f4e5949ec0fcc436e5610f50afe2dbf.1635541329.git.balaton@eik.bme.hu> Signed-off-by: Philippe Mathieu-Daudé --- hw/timer/sh_timer.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) (limited to 'hw/timer/sh_timer.c') diff --git a/hw/timer/sh_timer.c b/hw/timer/sh_timer.c index 58af1a1edb..4f765b339b 100644 --- a/hw/timer/sh_timer.c +++ b/hw/timer/sh_timer.c @@ -104,9 +104,10 @@ static void sh_timer_write(void *opaque, hwaddr offset, case OFFSET_TCR: ptimer_transaction_begin(s->timer); if (s->enabled) { - /* Pause the timer if it is running. This may cause some - inaccuracy dure to rounding, but avoids a whole lot of other - messyness. */ + /* + * Pause the timer if it is running. This may cause some inaccuracy + * dure to rounding, but avoids a whole lot of other messyness + */ ptimer_stop(s->timer); } freq = s->freq; -- cgit 1.4.1 From f94bff1337ff525e2ff458b8e4cd57f9561acde3 Mon Sep 17 00:00:00 2001 From: BALATON Zoltan Date: Fri, 29 Oct 2021 23:02:09 +0200 Subject: hw/sh4: Coding style: White space fixes MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: BALATON Zoltan Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Yoshinori Sato Message-Id: <91698c54fa493a4cfe93546211206439787d4b78.1635541329.git.balaton@eik.bme.hu> Signed-off-by: Philippe Mathieu-Daudé --- hw/char/sh_serial.c | 23 ++++++++++------------- hw/intc/sh_intc.c | 39 +++++++++++++++++++++++---------------- hw/pci-host/sh_pci.c | 10 ++++------ hw/sh4/r2d.c | 39 ++++++++++++++++++++------------------- hw/sh4/sh7750.c | 26 +++++++++++++------------- hw/sh4/sh7750_regnames.c | 5 +++-- hw/sh4/sh7750_regs.h | 18 +++++++++--------- hw/sh4/shix.c | 2 +- hw/timer/sh_timer.c | 22 ++++++++++++++++------ include/hw/sh4/sh.h | 10 +++++----- 10 files changed, 104 insertions(+), 90 deletions(-) (limited to 'hw/timer/sh_timer.c') diff --git a/hw/char/sh_serial.c b/hw/char/sh_serial.c index 05ae8e84ce..3fdb9f9a99 100644 --- a/hw/char/sh_serial.c +++ b/hw/char/sh_serial.c @@ -75,7 +75,7 @@ typedef struct { qemu_irq bri; } sh_serial_state; -static void sh_serial_clear_fifo(sh_serial_state * s) +static void sh_serial_clear_fifo(sh_serial_state *s) { memset(s->rx_fifo, 0, SH_RX_FIFO_LENGTH); s->rx_cnt = 0; @@ -93,7 +93,7 @@ static void sh_serial_write(void *opaque, hwaddr offs, printf("sh_serial: write offs=0x%02x val=0x%02x\n", offs, val); #endif - switch(offs) { + switch (offs) { case 0x00: /* SMR */ s->smr = val & ((s->feat & SH_SERIAL_FEAT_SCIF) ? 0x7b : 0xff); return; @@ -131,7 +131,7 @@ static void sh_serial_write(void *opaque, hwaddr offs, #endif } if (s->feat & SH_SERIAL_FEAT_SCIF) { - switch(offs) { + switch (offs) { case 0x10: /* FSR */ if (!(val & (1 << 6))) s->flags &= ~SH_SERIAL_FLAG_TEND; @@ -178,9 +178,8 @@ static void sh_serial_write(void *opaque, hwaddr offs, case 0x24: /* LSR */ return; } - } - else { - switch(offs) { + } else { + switch (offs) { #if 0 case 0x0c: ret = s->dr; @@ -207,7 +206,7 @@ static uint64_t sh_serial_read(void *opaque, hwaddr offs, uint32_t ret = ~0; #if 0 - switch(offs) { + switch (offs) { case 0x00: ret = s->smr; break; @@ -223,7 +222,7 @@ static uint64_t sh_serial_read(void *opaque, hwaddr offs, } #endif if (s->feat & SH_SERIAL_FEAT_SCIF) { - switch(offs) { + switch (offs) { case 0x00: /* SMR */ ret = s->smr; break; @@ -270,9 +269,8 @@ static uint64_t sh_serial_read(void *opaque, hwaddr offs, ret = 0; break; } - } - else { - switch(offs) { + } else { + switch (offs) { #if 0 case 0x0c: ret = s->dr; @@ -397,8 +395,7 @@ void sh_serial_init(MemoryRegion *sysmem, if (feat & SH_SERIAL_FEAT_SCIF) { s->fcr = 0; - } - else { + } else { s->dr = 0xff; } diff --git a/hw/intc/sh_intc.c b/hw/intc/sh_intc.c index 84eec7d4ba..67005081e3 100644 --- a/hw/intc/sh_intc.c +++ b/hw/intc/sh_intc.c @@ -71,18 +71,18 @@ void sh_intc_toggle_source(struct intc_source *source, enable_changed == -1 ? "disabled " : "", source->pending ? "pending" : ""); #endif - } + } } -static void sh_intc_set_irq (void *opaque, int n, int level) +static void sh_intc_set_irq(void *opaque, int n, int level) { - struct intc_desc *desc = opaque; - struct intc_source *source = &(desc->sources[n]); + struct intc_desc *desc = opaque; + struct intc_source *source = &(desc->sources[n]); - if (level && !source->asserted) - sh_intc_toggle_source(source, 0, 1); - else if (!level && source->asserted) - sh_intc_toggle_source(source, 0, -1); + if (level && !source->asserted) + sh_intc_toggle_source(source, 0, 1); + else if (!level && source->asserted) + sh_intc_toggle_source(source, 0, -1); } int sh_intc_get_pending_vector(struct intc_desc *desc, int imask) @@ -236,7 +236,7 @@ static uint64_t sh_intc_read(void *opaque, hwaddr offset, printf("sh_intc_read 0x%lx\n", (unsigned long) offset); #endif - sh_intc_locate(desc, (unsigned long)offset, &valuep, + sh_intc_locate(desc, (unsigned long)offset, &valuep, &enum_ids, &first, &width, &mode); return *valuep; } @@ -257,14 +257,20 @@ static void sh_intc_write(void *opaque, hwaddr offset, printf("sh_intc_write 0x%lx 0x%08x\n", (unsigned long) offset, value); #endif - sh_intc_locate(desc, (unsigned long)offset, &valuep, + sh_intc_locate(desc, (unsigned long)offset, &valuep, &enum_ids, &first, &width, &mode); switch (mode) { - case INTC_MODE_ENABLE_REG | INTC_MODE_IS_PRIO: break; - case INTC_MODE_DUAL_SET: value |= *valuep; break; - case INTC_MODE_DUAL_CLR: value = *valuep & ~value; break; - default: abort(); + case INTC_MODE_ENABLE_REG | INTC_MODE_IS_PRIO: + break; + case INTC_MODE_DUAL_SET: + value |= *valuep; + break; + case INTC_MODE_DUAL_CLR: + value = *valuep & ~value; + break; + default: + abort(); } for (k = 0; k <= first; k++) { @@ -465,7 +471,7 @@ int sh_intc_init(MemoryRegion *sysmem, } desc->irqs = qemu_allocate_irqs(sh_intc_set_irq, desc, nr_sources); - + memory_region_init_io(&desc->iomem, NULL, &sh_intc_ops, desc, "interrupt-controller", 0x100000000ULL); @@ -507,7 +513,8 @@ void sh_intc_set_irl(void *opaque, int n, int level) int i, irl = level ^ 15; for (i = 0; (s = sh_intc_source(s->parent, s->next_enum_id)); i++) { if (i == irl) - sh_intc_toggle_source(s, s->enable_count?0:1, s->asserted?0:1); + sh_intc_toggle_source(s, s->enable_count ? 0 : 1, + s->asserted ? 0 : 1); else if (s->asserted) sh_intc_toggle_source(s, 0, -1); diff --git a/hw/pci-host/sh_pci.c b/hw/pci-host/sh_pci.c index 08c1562e22..719d6ca2a6 100644 --- a/hw/pci-host/sh_pci.c +++ b/hw/pci-host/sh_pci.c @@ -49,13 +49,12 @@ struct SHPCIState { uint32_t iobr; }; -static void sh_pci_reg_write (void *p, hwaddr addr, uint64_t val, - unsigned size) +static void sh_pci_reg_write(void *p, hwaddr addr, uint64_t val, unsigned size) { SHPCIState *pcic = p; PCIHostState *phb = PCI_HOST_BRIDGE(pcic); - switch(addr) { + switch (addr) { case 0 ... 0xfc: stl_le_p(pcic->dev->config + addr, val); break; @@ -75,13 +74,12 @@ static void sh_pci_reg_write (void *p, hwaddr addr, uint64_t val, } } -static uint64_t sh_pci_reg_read (void *p, hwaddr addr, - unsigned size) +static uint64_t sh_pci_reg_read(void *p, hwaddr addr, unsigned size) { SHPCIState *pcic = p; PCIHostState *phb = PCI_HOST_BRIDGE(pcic); - switch(addr) { + switch (addr) { case 0 ... 0xfc: return ldl_le_p(pcic->dev->config + addr); case 0x1c0: diff --git a/hw/sh4/r2d.c b/hw/sh4/r2d.c index 46f1fae48c..216d6e24a1 100644 --- a/hw/sh4/r2d.c +++ b/hw/sh4/r2d.c @@ -96,19 +96,19 @@ enum r2d_fpga_irq { }; static const struct { short irl; uint16_t msk; } irqtab[NR_IRQS] = { - [CF_IDE] = { 1, 1<<9 }, - [CF_CD] = { 2, 1<<8 }, - [PCI_INTA] = { 9, 1<<14 }, - [PCI_INTB] = { 10, 1<<13 }, - [PCI_INTC] = { 3, 1<<12 }, - [PCI_INTD] = { 0, 1<<11 }, - [SM501] = { 4, 1<<10 }, - [KEY] = { 5, 1<<6 }, - [RTC_A] = { 6, 1<<5 }, - [RTC_T] = { 7, 1<<4 }, - [SDCARD] = { 8, 1<<7 }, - [EXT] = { 11, 1<<0 }, - [TP] = { 12, 1<<15 }, + [CF_IDE] = { 1, 1 << 9 }, + [CF_CD] = { 2, 1 << 8 }, + [PCI_INTA] = { 9, 1 << 14 }, + [PCI_INTB] = { 10, 1 << 13 }, + [PCI_INTC] = { 3, 1 << 12 }, + [PCI_INTD] = { 0, 1 << 11 }, + [SM501] = { 4, 1 << 10 }, + [KEY] = { 5, 1 << 6 }, + [RTC_A] = { 6, 1 << 5 }, + [RTC_T] = { 7, 1 << 4 }, + [SDCARD] = { 8, 1 << 7 }, + [EXT] = { 11, 1 << 0 }, + [TP] = { 12, 1 << 15 }, }; static void update_irl(r2d_fpga_t *fpga) @@ -306,7 +306,7 @@ static void r2d_init(MachineState *machine) /* NIC: rtl8139 on-board, and 2 slots. */ for (i = 0; i < nb_nics; i++) pci_nic_init_nofail(&nd_table[i], pci_bus, - "rtl8139", i==0 ? "2" : NULL); + "rtl8139", i == 0 ? "2" : NULL); /* USB keyboard */ usb_create_simple(usb_bus_find(-1), "usb-kbd"); @@ -321,8 +321,8 @@ static void r2d_init(MachineState *machine) SDRAM_BASE + LINUX_LOAD_OFFSET, INITRD_LOAD_OFFSET - LINUX_LOAD_OFFSET); if (kernel_size < 0) { - fprintf(stderr, "qemu: could not load kernel '%s'\n", kernel_filename); - exit(1); + fprintf(stderr, "qemu: could not load kernel '%s'\n", kernel_filename); + exit(1); } /* initialization which should be done by firmware */ @@ -330,7 +330,8 @@ static void r2d_init(MachineState *machine) MEMTXATTRS_UNSPECIFIED, NULL); /* cs3 SDRAM */ address_space_stw(&address_space_memory, SH7750_BCR2, 3 << (3 * 2), MEMTXATTRS_UNSPECIFIED, NULL); /* cs3 32bit */ - reset_info->vector = (SDRAM_BASE + LINUX_LOAD_OFFSET) | 0xa0000000; /* Start from P2 area */ + /* Start from P2 area */ + reset_info->vector = (SDRAM_BASE + LINUX_LOAD_OFFSET) | 0xa0000000; } if (initrd_filename) { @@ -341,8 +342,8 @@ static void r2d_init(MachineState *machine) SDRAM_SIZE - INITRD_LOAD_OFFSET); if (initrd_size < 0) { - fprintf(stderr, "qemu: could not load initrd '%s'\n", initrd_filename); - exit(1); + fprintf(stderr, "qemu: could not load initrd '%s'\n", initrd_filename); + exit(1); } /* initialization which should be done by firmware */ diff --git a/hw/sh4/sh7750.c b/hw/sh4/sh7750.c index 2539924b00..1e61f9f1c8 100644 --- a/hw/sh4/sh7750.c +++ b/hw/sh4/sh7750.c @@ -78,7 +78,7 @@ typedef struct SH7750State { struct intc_desc intc; } SH7750State; -static inline int has_bcr3_and_bcr4(SH7750State * s) +static inline int has_bcr3_and_bcr4(SH7750State *s) { return s->cpu->env.features & SH_FEATURE_BCR3_AND_BCR4; } @@ -87,7 +87,7 @@ static inline int has_bcr3_and_bcr4(SH7750State * s) * I/O ports */ -int sh7750_register_io_device(SH7750State * s, sh7750_io_device * device) +int sh7750_register_io_device(SH7750State *s, sh7750_io_device *device) { int i; @@ -102,7 +102,7 @@ int sh7750_register_io_device(SH7750State * s, sh7750_io_device * device) static uint16_t portdir(uint32_t v) { -#define EVENPORTMASK(n) ((v & (1<<((n)<<1))) >> (n)) +#define EVENPORTMASK(n) ((v & (1 << ((n) << 1))) >> (n)) return EVENPORTMASK(15) | EVENPORTMASK(14) | EVENPORTMASK(13) | EVENPORTMASK(12) | EVENPORTMASK(11) | EVENPORTMASK(10) | @@ -114,7 +114,7 @@ static uint16_t portdir(uint32_t v) static uint16_t portpullup(uint32_t v) { -#define ODDPORTMASK(n) ((v & (1<<(((n)<<1)+1))) >> (n)) +#define ODDPORTMASK(n) ((v & (1 << (((n) << 1) + 1))) >> (n)) return ODDPORTMASK(15) | ODDPORTMASK(14) | ODDPORTMASK(13) | ODDPORTMASK(12) | ODDPORTMASK(11) | ODDPORTMASK(10) | @@ -123,26 +123,26 @@ static uint16_t portpullup(uint32_t v) ODDPORTMASK(1) | ODDPORTMASK(0); } -static uint16_t porta_lines(SH7750State * s) +static uint16_t porta_lines(SH7750State *s) { return (s->portdira & s->pdtra) | /* CPU */ (s->periph_portdira & s->periph_pdtra) | /* Peripherals */ (~(s->portdira | s->periph_portdira) & s->portpullupa); /* Pullups */ } -static uint16_t portb_lines(SH7750State * s) +static uint16_t portb_lines(SH7750State *s) { return (s->portdirb & s->pdtrb) | /* CPU */ (s->periph_portdirb & s->periph_pdtrb) | /* Peripherals */ (~(s->portdirb | s->periph_portdirb) & s->portpullupb); /* Pullups */ } -static void gen_port_interrupts(SH7750State * s) +static void gen_port_interrupts(SH7750State *s) { /* XXXXX interrupts not generated */ } -static void porta_changed(SH7750State * s, uint16_t prev) +static void porta_changed(SH7750State *s, uint16_t prev) { uint16_t currenta, changes; int i, r = 0; @@ -171,7 +171,7 @@ static void porta_changed(SH7750State * s, uint16_t prev) gen_port_interrupts(s); } -static void portb_changed(SH7750State * s, uint16_t prev) +static void portb_changed(SH7750State *s, uint16_t prev) { uint16_t currentb, changes; int i, r = 0; @@ -228,7 +228,7 @@ static uint32_t sh7750_mem_readw(void *opaque, hwaddr addr) case SH7750_BCR2_A7: return s->bcr2; case SH7750_BCR3_A7: - if(!has_bcr3_and_bcr4(s)) + if (!has_bcr3_and_bcr4(s)) error_access("word read", addr); return s->bcr3; case SH7750_FRQCR_A7: @@ -263,7 +263,7 @@ static uint32_t sh7750_mem_readl(void *opaque, hwaddr addr) case SH7750_BCR1_A7: return s->bcr1; case SH7750_BCR4_A7: - if(!has_bcr3_and_bcr4(s)) + if (!has_bcr3_and_bcr4(s)) error_access("long read", addr); return s->bcr4; case SH7750_WCR1_A7: @@ -332,7 +332,7 @@ static void sh7750_mem_writew(void *opaque, hwaddr addr, s->bcr2 = mem_value; return; case SH7750_BCR3_A7: - if(!has_bcr3_and_bcr4(s)) + if (!has_bcr3_and_bcr4(s)) error_access("word write", addr); s->bcr3 = mem_value; return; @@ -384,7 +384,7 @@ static void sh7750_mem_writel(void *opaque, hwaddr addr, s->bcr1 = mem_value; return; case SH7750_BCR4_A7: - if(!has_bcr3_and_bcr4(s)) + if (!has_bcr3_and_bcr4(s)) error_access("long write", addr); s->bcr4 = mem_value; return; diff --git a/hw/sh4/sh7750_regnames.c b/hw/sh4/sh7750_regnames.c index b1f112df3e..37b3acd620 100644 --- a/hw/sh4/sh7750_regnames.c +++ b/hw/sh4/sh7750_regnames.c @@ -81,14 +81,15 @@ static regname_t regnames[] = { REGNAME(SH7750_BCR3_A7) REGNAME(SH7750_BCR4_A7) REGNAME(SH7750_SDMR2_A7) - REGNAME(SH7750_SDMR3_A7) {(uint32_t) - 1, NULL} + REGNAME(SH7750_SDMR3_A7) + { (uint32_t)-1, NULL } }; const char *regname(uint32_t addr) { unsigned int i; - for (i = 0; regnames[i].regaddr != (uint32_t) - 1; i++) { + for (i = 0; regnames[i].regaddr != (uint32_t)-1; i++) { if (regnames[i].regaddr == addr) return regnames[i].regname; } diff --git a/hw/sh4/sh7750_regs.h b/hw/sh4/sh7750_regs.h index bd12b0532d..beb571d5e9 100644 --- a/hw/sh4/sh7750_regs.h +++ b/hw/sh4/sh7750_regs.h @@ -1015,7 +1015,7 @@ */ /* DMA Source Address Register - SAR0, SAR1, SAR2, SAR3 */ -#define SH7750_SAR_REGOFS(n) (0xA00000 + ((n)*16)) /* offset */ +#define SH7750_SAR_REGOFS(n) (0xA00000 + ((n) * 16)) /* offset */ #define SH7750_SAR(n) SH7750_P4_REG32(SH7750_SAR_REGOFS(n)) #define SH7750_SAR_A7(n) SH7750_A7_REG32(SH7750_SAR_REGOFS(n)) #define SH7750_SAR0 SH7750_SAR(0) @@ -1028,7 +1028,7 @@ #define SH7750_SAR3_A7 SH7750_SAR_A7(3) /* DMA Destination Address Register - DAR0, DAR1, DAR2, DAR3 */ -#define SH7750_DAR_REGOFS(n) (0xA00004 + ((n)*16)) /* offset */ +#define SH7750_DAR_REGOFS(n) (0xA00004 + ((n) * 16)) /* offset */ #define SH7750_DAR(n) SH7750_P4_REG32(SH7750_DAR_REGOFS(n)) #define SH7750_DAR_A7(n) SH7750_A7_REG32(SH7750_DAR_REGOFS(n)) #define SH7750_DAR0 SH7750_DAR(0) @@ -1041,7 +1041,7 @@ #define SH7750_DAR3_A7 SH7750_DAR_A7(3) /* DMA Transfer Count Register - DMATCR0, DMATCR1, DMATCR2, DMATCR3 */ -#define SH7750_DMATCR_REGOFS(n) (0xA00008 + ((n)*16)) /* offset */ +#define SH7750_DMATCR_REGOFS(n) (0xA00008 + ((n) * 16)) /* offset */ #define SH7750_DMATCR(n) SH7750_P4_REG32(SH7750_DMATCR_REGOFS(n)) #define SH7750_DMATCR_A7(n) SH7750_A7_REG32(SH7750_DMATCR_REGOFS(n)) #define SH7750_DMATCR0_P4 SH7750_DMATCR(0) @@ -1054,7 +1054,7 @@ #define SH7750_DMATCR3_A7 SH7750_DMATCR_A7(3) /* DMA Channel Control Register - CHCR0, CHCR1, CHCR2, CHCR3 */ -#define SH7750_CHCR_REGOFS(n) (0xA0000C + ((n)*16)) /* offset */ +#define SH7750_CHCR_REGOFS(n) (0xA0000C + ((n) * 16)) /* offset */ #define SH7750_CHCR(n) SH7750_P4_REG32(SH7750_CHCR_REGOFS(n)) #define SH7750_CHCR_A7(n) SH7750_A7_REG32(SH7750_CHCR_REGOFS(n)) #define SH7750_CHCR0 SH7750_CHCR(0) @@ -1208,9 +1208,9 @@ #define SH7750_PCTRA_A7 SH7750_A7_REG32(SH7750_PCTRA_REGOFS) #define SH7750_PCTRA_PBPUP(n) 0 /* Bit n is pulled up */ -#define SH7750_PCTRA_PBNPUP(n) (1 << ((n)*2+1)) /* Bit n is not pulled up */ +#define SH7750_PCTRA_PBNPUP(n) (1 << ((n) * 2 + 1)) /* Bit n is not pulled up */ #define SH7750_PCTRA_PBINP(n) 0 /* Bit n is an input */ -#define SH7750_PCTRA_PBOUT(n) (1 << ((n)*2)) /* Bit n is an output */ +#define SH7750_PCTRA_PBOUT(n) (1 << ((n) * 2)) /* Bit n is an output */ /* Port Data Register A - PDTRA(half) */ #define SH7750_PDTRA_REGOFS 0x800030 /* offset */ @@ -1225,16 +1225,16 @@ #define SH7750_PCTRB_A7 SH7750_A7_REG32(SH7750_PCTRB_REGOFS) #define SH7750_PCTRB_PBPUP(n) 0 /* Bit n is pulled up */ -#define SH7750_PCTRB_PBNPUP(n) (1 << ((n-16)*2+1)) /* Bit n is not pulled up */ +#define SH7750_PCTRB_PBNPUP(n) (1 << ((n - 16) * 2 + 1)) /* Bit n is not pulled up */ #define SH7750_PCTRB_PBINP(n) 0 /* Bit n is an input */ -#define SH7750_PCTRB_PBOUT(n) (1 << ((n-16)*2)) /* Bit n is an output */ +#define SH7750_PCTRB_PBOUT(n) (1 << ((n - 16) * 2)) /* Bit n is an output */ /* Port Data Register B - PDTRB(half) */ #define SH7750_PDTRB_REGOFS 0x800044 /* offset */ #define SH7750_PDTRB SH7750_P4_REG32(SH7750_PDTRB_REGOFS) #define SH7750_PDTRB_A7 SH7750_A7_REG32(SH7750_PDTRB_REGOFS) -#define SH7750_PDTRB_BIT(n) (1 << ((n)-16)) +#define SH7750_PDTRB_BIT(n) (1 << ((n) - 16)) /* GPIO Interrupt Control Register - GPIOIC(half) */ #define SH7750_GPIOIC_REGOFS 0x800048 /* offset */ diff --git a/hw/sh4/shix.c b/hw/sh4/shix.c index 6b39de417f..aa812512f0 100644 --- a/hw/sh4/shix.c +++ b/hw/sh4/shix.c @@ -48,7 +48,7 @@ static void shix_init(MachineState *machine) MemoryRegion *rom = g_new(MemoryRegion, 1); MemoryRegion *sdram = g_new(MemoryRegion, 2); const char *bios_name = machine->firmware ?: BIOS_FILENAME; - + cpu = SUPERH_CPU(cpu_create(machine->cpu_type)); /* Allocate memory space */ diff --git a/hw/timer/sh_timer.c b/hw/timer/sh_timer.c index 4f765b339b..01afcbd2b0 100644 --- a/hw/timer/sh_timer.c +++ b/hw/timer/sh_timer.c @@ -55,7 +55,7 @@ static void sh_timer_update(sh_timer_state *s) int new_level = s->int_level && (s->tcr & TIMER_TCR_UNIE); if (new_level != s->old_level) - qemu_set_irq (s->irq, new_level); + qemu_set_irq(s->irq, new_level); s->old_level = s->int_level; s->int_level = new_level; @@ -113,11 +113,21 @@ static void sh_timer_write(void *opaque, hwaddr offset, freq = s->freq; /* ??? Need to recalculate expiry time after changing divisor. */ switch (value & TIMER_TCR_TPSC) { - case 0: freq >>= 2; break; - case 1: freq >>= 4; break; - case 2: freq >>= 6; break; - case 3: freq >>= 8; break; - case 4: freq >>= 10; break; + case 0: + freq >>= 2; + break; + case 1: + freq >>= 4; + break; + case 2: + freq >>= 6; + break; + case 3: + freq >>= 8; + break; + case 4: + freq >>= 10; + break; case 6: case 7: if (s->feat & TIMER_FEAT_EXTCLK) { diff --git a/include/hw/sh4/sh.h b/include/hw/sh4/sh.h index 3d5ba598d0..366cedcda0 100644 --- a/include/hw/sh4/sh.h +++ b/include/hw/sh4/sh.h @@ -44,14 +44,14 @@ typedef struct { uint16_t portbmask_trigger; /* Return 0 if no action was taken */ int (*port_change_cb) (uint16_t porta, uint16_t portb, - uint16_t * periph_pdtra, - uint16_t * periph_portdira, - uint16_t * periph_pdtrb, - uint16_t * periph_portdirb); + uint16_t *periph_pdtra, + uint16_t *periph_portdira, + uint16_t *periph_pdtrb, + uint16_t *periph_portdirb); } sh7750_io_device; int sh7750_register_io_device(struct SH7750State *s, - sh7750_io_device * device); + sh7750_io_device *device); /* sh_serial.c */ #define SH_SERIAL_FEAT_SCIF (1 << 0) -- cgit 1.4.1 From ac3c9e74c1ee1071e5be692a611c5ee261b9b581 Mon Sep 17 00:00:00 2001 From: BALATON Zoltan Date: Fri, 29 Oct 2021 23:02:09 +0200 Subject: hw/sh4: Coding style: Add missing braces MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: BALATON Zoltan Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Yoshinori Sato Message-Id: Signed-off-by: Philippe Mathieu-Daudé --- hw/char/sh_serial.c | 48 +++++++++++++++++--------- hw/intc/sh_intc.c | 87 ++++++++++++++++++++++++++---------------------- hw/sh4/r2d.c | 15 +++++---- hw/sh4/sh7750.c | 24 ++++++++----- hw/sh4/sh7750_regnames.c | 3 +- hw/timer/sh_timer.c | 22 ++++++------ 6 files changed, 118 insertions(+), 81 deletions(-) (limited to 'hw/timer/sh_timer.c') diff --git a/hw/char/sh_serial.c b/hw/char/sh_serial.c index 3fdb9f9a99..1b1e6a6a04 100644 --- a/hw/char/sh_serial.c +++ b/hw/char/sh_serial.c @@ -103,8 +103,9 @@ static void sh_serial_write(void *opaque, hwaddr offs, case 0x08: /* SCR */ /* TODO : For SH7751, SCIF mask should be 0xfb. */ s->scr = val & ((s->feat & SH_SERIAL_FEAT_SCIF) ? 0xfa : 0xff); - if (!(val & (1 << 5))) + if (!(val & (1 << 5))) { s->flags |= SH_SERIAL_FLAG_TEND; + } if ((s->feat & SH_SERIAL_FEAT_SCIF) && s->txi) { qemu_set_irq(s->txi, val & (1 << 7)); } @@ -133,16 +134,21 @@ static void sh_serial_write(void *opaque, hwaddr offs, if (s->feat & SH_SERIAL_FEAT_SCIF) { switch (offs) { case 0x10: /* FSR */ - if (!(val & (1 << 6))) + if (!(val & (1 << 6))) { s->flags &= ~SH_SERIAL_FLAG_TEND; - if (!(val & (1 << 5))) + } + if (!(val & (1 << 5))) { s->flags &= ~SH_SERIAL_FLAG_TDE; - if (!(val & (1 << 4))) + } + if (!(val & (1 << 4))) { s->flags &= ~SH_SERIAL_FLAG_BRK; - if (!(val & (1 << 1))) + } + if (!(val & (1 << 1))) { s->flags &= ~SH_SERIAL_FLAG_RDF; - if (!(val & (1 << 0))) + } + if (!(val & (1 << 0))) { s->flags &= ~SH_SERIAL_FLAG_DR; + } if (!(val & (1 << 1)) || !(val & (1 << 0))) { if (s->rxi) { @@ -231,29 +237,37 @@ static uint64_t sh_serial_read(void *opaque, hwaddr offs, break; case 0x10: /* FSR */ ret = 0; - if (s->flags & SH_SERIAL_FLAG_TEND) + if (s->flags & SH_SERIAL_FLAG_TEND) { ret |= (1 << 6); - if (s->flags & SH_SERIAL_FLAG_TDE) + } + if (s->flags & SH_SERIAL_FLAG_TDE) { ret |= (1 << 5); - if (s->flags & SH_SERIAL_FLAG_BRK) + } + if (s->flags & SH_SERIAL_FLAG_BRK) { ret |= (1 << 4); - if (s->flags & SH_SERIAL_FLAG_RDF) + } + if (s->flags & SH_SERIAL_FLAG_RDF) { ret |= (1 << 1); - if (s->flags & SH_SERIAL_FLAG_DR) + } + if (s->flags & SH_SERIAL_FLAG_DR) { ret |= (1 << 0); + } - if (s->scr & (1 << 5)) + if (s->scr & (1 << 5)) { s->flags |= SH_SERIAL_FLAG_TDE | SH_SERIAL_FLAG_TEND; + } break; case 0x14: if (s->rx_cnt > 0) { ret = s->rx_fifo[s->rx_tail++]; s->rx_cnt--; - if (s->rx_tail == SH_RX_FIFO_LENGTH) + if (s->rx_tail == SH_RX_FIFO_LENGTH) { s->rx_tail = 0; - if (s->rx_cnt < s->rtrg) + } + if (s->rx_cnt < s->rtrg) { s->flags &= ~SH_SERIAL_FLAG_RDF; + } } break; case 0x18: @@ -308,8 +322,9 @@ static int sh_serial_can_receive(sh_serial_state *s) static void sh_serial_receive_break(sh_serial_state *s) { - if (s->feat & SH_SERIAL_FEAT_SCIF) + if (s->feat & SH_SERIAL_FEAT_SCIF) { s->sr |= (1 << 4); + } } static int sh_serial_can_receive1(void *opaque) @@ -361,8 +376,9 @@ static void sh_serial_receive1(void *opaque, const uint8_t *buf, int size) static void sh_serial_event(void *opaque, QEMUChrEvent event) { sh_serial_state *s = opaque; - if (event == CHR_EVENT_BREAK) + if (event == CHR_EVENT_BREAK) { sh_serial_receive_break(s); + } } static const MemoryRegionOps sh_serial_ops = { diff --git a/hw/intc/sh_intc.c b/hw/intc/sh_intc.c index 67005081e3..eddad7c195 100644 --- a/hw/intc/sh_intc.c +++ b/hw/intc/sh_intc.c @@ -26,23 +26,23 @@ void sh_intc_toggle_source(struct intc_source *source, int pending_changed = 0; int old_pending; - if ((source->enable_count == source->enable_max) && (enable_adj == -1)) + if ((source->enable_count == source->enable_max) && (enable_adj == -1)) { enable_changed = -1; - + } source->enable_count += enable_adj; - if (source->enable_count == source->enable_max) + if (source->enable_count == source->enable_max) { enable_changed = 1; - + } source->asserted += assert_adj; old_pending = source->pending; source->pending = source->asserted && (source->enable_count == source->enable_max); - if (old_pending != source->pending) + if (old_pending != source->pending) { pending_changed = 1; - + } if (pending_changed) { if (source->pending) { source->parent->pending++; @@ -79,10 +79,11 @@ static void sh_intc_set_irq(void *opaque, int n, int level) struct intc_desc *desc = opaque; struct intc_source *source = &(desc->sources[n]); - if (level && !source->asserted) - sh_intc_toggle_source(source, 0, 1); - else if (!level && source->asserted) - sh_intc_toggle_source(source, 0, -1); + if (level && !source->asserted) { + sh_intc_toggle_source(source, 0, 1); + } else if (!level && source->asserted) { + sh_intc_toggle_source(source, 0, -1); + } } int sh_intc_get_pending_vector(struct intc_desc *desc, int imask) @@ -126,16 +127,18 @@ static unsigned int sh_intc_mode(unsigned long address, return INTC_MODE_NONE; if (set_reg && clr_reg) { - if (address == INTC_A7(set_reg)) + if (address == INTC_A7(set_reg)) { return INTC_MODE_DUAL_SET; - else + } else { return INTC_MODE_DUAL_CLR; + } } - if (set_reg) + if (set_reg) { return INTC_MODE_ENABLE_REG; - else + } else { return INTC_MODE_MASK_REG; + } } static void sh_intc_locate(struct intc_desc *desc, @@ -155,9 +158,9 @@ static void sh_intc_locate(struct intc_desc *desc, struct intc_mask_reg *mr = desc->mask_regs + i; mode = sh_intc_mode(address, mr->set_reg, mr->clr_reg); - if (mode == INTC_MODE_NONE) + if (mode == INTC_MODE_NONE) { continue; - + } *modep = mode; *datap = &mr->value; *enums = mr->enum_ids; @@ -172,9 +175,9 @@ static void sh_intc_locate(struct intc_desc *desc, struct intc_prio_reg *pr = desc->prio_regs + i; mode = sh_intc_mode(address, pr->set_reg, pr->clr_reg); - if (mode == INTC_MODE_NONE) + if (mode == INTC_MODE_NONE) { continue; - + } *modep = mode | INTC_MODE_IS_PRIO; *datap = &pr->value; *enums = pr->enum_ids; @@ -192,9 +195,9 @@ static void sh_intc_toggle_mask(struct intc_desc *desc, intc_enum id, { struct intc_source *source = desc->sources + id; - if (!id) + if (!id) { return; - + } if (!source->next_enum_id && (!source->enable_max || !source->vect)) { #ifdef DEBUG_INTC_SOURCES printf("sh_intc: reserved interrupt source %d modified\n", id); @@ -202,9 +205,9 @@ static void sh_intc_toggle_mask(struct intc_desc *desc, intc_enum id, return; } - if (source->vect) + if (source->vect) { sh_intc_toggle_source(source, enable ? 1 : -1, 0); - + } #ifdef DEBUG_INTC else { printf("setting interrupt group %d to %d\n", id, !!enable); @@ -276,8 +279,9 @@ static void sh_intc_write(void *opaque, hwaddr offset, for (k = 0; k <= first; k++) { mask = ((1 << width) - 1) << ((first - k) * width); - if ((*valuep & mask) == (value & mask)) + if ((*valuep & mask) == (value & mask)) { continue; + } #if 0 printf("k = %d, first = %d, enum = %d, mask = 0x%08x\n", k, first, enum_ids[k], (unsigned int)mask); @@ -300,9 +304,9 @@ static const MemoryRegionOps sh_intc_ops = { struct intc_source *sh_intc_source(struct intc_desc *desc, intc_enum id) { - if (id) + if (id) { return desc->sources + id; - + } return NULL; } @@ -351,12 +355,13 @@ static void sh_intc_register_source(struct intc_desc *desc, struct intc_mask_reg *mr = desc->mask_regs + i; for (k = 0; k < ARRAY_SIZE(mr->enum_ids); k++) { - if (mr->enum_ids[k] != source) + if (mr->enum_ids[k] != source) { continue; - + } s = sh_intc_source(desc, mr->enum_ids[k]); - if (s) + if (s) { s->enable_max++; + } } } } @@ -366,12 +371,13 @@ static void sh_intc_register_source(struct intc_desc *desc, struct intc_prio_reg *pr = desc->prio_regs + i; for (k = 0; k < ARRAY_SIZE(pr->enum_ids); k++) { - if (pr->enum_ids[k] != source) + if (pr->enum_ids[k] != source) { continue; - + } s = sh_intc_source(desc, pr->enum_ids[k]); - if (s) + if (s) { s->enable_max++; + } } } } @@ -381,12 +387,13 @@ static void sh_intc_register_source(struct intc_desc *desc, struct intc_group *gr = groups + i; for (k = 0; k < ARRAY_SIZE(gr->enum_ids); k++) { - if (gr->enum_ids[k] != source) + if (gr->enum_ids[k] != source) { continue; - + } s = sh_intc_source(desc, gr->enum_ids[k]); - if (s) + if (s) { s->enable_max++; + } } } } @@ -425,9 +432,9 @@ void sh_intc_register_sources(struct intc_desc *desc, s->next_enum_id = gr->enum_ids[0]; for (k = 1; k < ARRAY_SIZE(gr->enum_ids); k++) { - if (!gr->enum_ids[k]) + if (!gr->enum_ids[k]) { continue; - + } s = sh_intc_source(desc, gr->enum_ids[k - 1]); s->next_enum_id = gr->enum_ids[k]; } @@ -512,11 +519,11 @@ void sh_intc_set_irl(void *opaque, int n, int level) struct intc_source *s = opaque; int i, irl = level ^ 15; for (i = 0; (s = sh_intc_source(s->parent, s->next_enum_id)); i++) { - if (i == irl) + if (i == irl) { sh_intc_toggle_source(s, s->enable_count ? 0 : 1, s->asserted ? 0 : 1); - else - if (s->asserted) - sh_intc_toggle_source(s, 0, -1); + } else if (s->asserted) { + sh_intc_toggle_source(s, 0, -1); + } } } diff --git a/hw/sh4/r2d.c b/hw/sh4/r2d.c index 216d6e24a1..57ccae7249 100644 --- a/hw/sh4/r2d.c +++ b/hw/sh4/r2d.c @@ -114,20 +114,23 @@ static const struct { short irl; uint16_t msk; } irqtab[NR_IRQS] = { static void update_irl(r2d_fpga_t *fpga) { int i, irl = 15; - for (i = 0; i < NR_IRQS; i++) - if (fpga->irlmon & fpga->irlmsk & irqtab[i].msk) - if (irqtab[i].irl < irl) - irl = irqtab[i].irl; + for (i = 0; i < NR_IRQS; i++) { + if ((fpga->irlmon & fpga->irlmsk & irqtab[i].msk) && + irqtab[i].irl < irl) { + irl = irqtab[i].irl; + } + } qemu_set_irq(fpga->irl, irl ^ 15); } static void r2d_fpga_irq_set(void *opaque, int n, int level) { r2d_fpga_t *fpga = opaque; - if (level) + if (level) { fpga->irlmon |= irqtab[n].msk; - else + } else { fpga->irlmon &= ~irqtab[n].msk; + } update_irl(fpga); } diff --git a/hw/sh4/sh7750.c b/hw/sh4/sh7750.c index 1e61f9f1c8..ca7e261aba 100644 --- a/hw/sh4/sh7750.c +++ b/hw/sh4/sh7750.c @@ -153,8 +153,9 @@ static void porta_changed(SH7750State *s, uint16_t prev) fprintf(stderr, "pdtra=0x%04x, pctra=0x%08x\n", s->pdtra, s->pctra); #endif currenta = porta_lines(s); - if (currenta == prev) + if (currenta == prev) { return; + } changes = currenta ^ prev; for (i = 0; i < NB_DEVICES; i++) { @@ -167,8 +168,9 @@ static void porta_changed(SH7750State *s, uint16_t prev) } } - if (r) + if (r) { gen_port_interrupts(s); + } } static void portb_changed(SH7750State *s, uint16_t prev) @@ -177,8 +179,9 @@ static void portb_changed(SH7750State *s, uint16_t prev) int i, r = 0; currentb = portb_lines(s); - if (currentb == prev) + if (currentb == prev) { return; + } changes = currentb ^ prev; for (i = 0; i < NB_DEVICES; i++) { @@ -191,8 +194,9 @@ static void portb_changed(SH7750State *s, uint16_t prev) } } - if (r) + if (r) { gen_port_interrupts(s); + } } /* @@ -228,8 +232,9 @@ static uint32_t sh7750_mem_readw(void *opaque, hwaddr addr) case SH7750_BCR2_A7: return s->bcr2; case SH7750_BCR3_A7: - if (!has_bcr3_and_bcr4(s)) + if (!has_bcr3_and_bcr4(s)) { error_access("word read", addr); + } return s->bcr3; case SH7750_FRQCR_A7: return 0; @@ -263,8 +268,9 @@ static uint32_t sh7750_mem_readl(void *opaque, hwaddr addr) case SH7750_BCR1_A7: return s->bcr1; case SH7750_BCR4_A7: - if (!has_bcr3_and_bcr4(s)) + if (!has_bcr3_and_bcr4(s)) { error_access("long read", addr); + } return s->bcr4; case SH7750_WCR1_A7: case SH7750_WCR2_A7: @@ -332,8 +338,9 @@ static void sh7750_mem_writew(void *opaque, hwaddr addr, s->bcr2 = mem_value; return; case SH7750_BCR3_A7: - if (!has_bcr3_and_bcr4(s)) + if (!has_bcr3_and_bcr4(s)) { error_access("word write", addr); + } s->bcr3 = mem_value; return; case SH7750_PCR_A7: @@ -384,8 +391,9 @@ static void sh7750_mem_writel(void *opaque, hwaddr addr, s->bcr1 = mem_value; return; case SH7750_BCR4_A7: - if (!has_bcr3_and_bcr4(s)) + if (!has_bcr3_and_bcr4(s)) { error_access("long write", addr); + } s->bcr4 = mem_value; return; case SH7750_WCR1_A7: diff --git a/hw/sh4/sh7750_regnames.c b/hw/sh4/sh7750_regnames.c index 37b3acd620..e531d46a8e 100644 --- a/hw/sh4/sh7750_regnames.c +++ b/hw/sh4/sh7750_regnames.c @@ -90,8 +90,9 @@ const char *regname(uint32_t addr) unsigned int i; for (i = 0; regnames[i].regaddr != (uint32_t)-1; i++) { - if (regnames[i].regaddr == addr) + if (regnames[i].regaddr == addr) { return regnames[i].regname; + } } return ""; diff --git a/hw/timer/sh_timer.c b/hw/timer/sh_timer.c index 01afcbd2b0..68c109ecfd 100644 --- a/hw/timer/sh_timer.c +++ b/hw/timer/sh_timer.c @@ -54,9 +54,9 @@ static void sh_timer_update(sh_timer_state *s) { int new_level = s->int_level && (s->tcr & TIMER_TCR_UNIE); - if (new_level != s->old_level) + if (new_level != s->old_level) { qemu_set_irq(s->irq, new_level); - + } s->old_level = s->int_level; s->int_level = new_level; } @@ -73,8 +73,9 @@ static uint32_t sh_timer_read(void *opaque, hwaddr offset) case OFFSET_TCR: return s->tcr | (s->int_level ? TIMER_TCR_UNF : 0); case OFFSET_TCPR: - if (s->feat & TIMER_FEAT_CAPT) + if (s->feat & TIMER_FEAT_CAPT) { return s->tcpr; + } /* fall through */ default: hw_error("sh_timer_read: Bad offset %x\n", (int)offset); @@ -279,17 +280,18 @@ static uint64_t tmu012_read(void *opaque, hwaddr offset, return sh_timer_read(s->timer[2], offset - 0x20); } - if (offset >= 0x14) + if (offset >= 0x14) { return sh_timer_read(s->timer[1], offset - 0x14); - - if (offset >= 0x08) + } + if (offset >= 0x08) { return sh_timer_read(s->timer[0], offset - 0x08); - - if (offset == 4) + } + if (offset == 4) { return s->tstr; - - if ((s->feat & TMU012_FEAT_TOCR) && offset == 0) + } + if ((s->feat & TMU012_FEAT_TOCR) && offset == 0) { return s->tocr; + } hw_error("tmu012_write: Bad offset %x\n", (int)offset); return 0; -- cgit 1.4.1 From 373b96b9c6d77a54a52239b422a44958d9dcc67e Mon Sep 17 00:00:00 2001 From: BALATON Zoltan Date: Fri, 29 Oct 2021 23:02:09 +0200 Subject: hw/sh4: Coding style: Remove unnecessary casts MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: BALATON Zoltan Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Yoshinori Sato Message-Id: <6cb1bcf24572ad8465c20b64fec81157f34bcbe9.1635541329.git.balaton@eik.bme.hu> Signed-off-by: Philippe Mathieu-Daudé --- hw/timer/sh_timer.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'hw/timer/sh_timer.c') diff --git a/hw/timer/sh_timer.c b/hw/timer/sh_timer.c index 68c109ecfd..02eb865908 100644 --- a/hw/timer/sh_timer.c +++ b/hw/timer/sh_timer.c @@ -233,7 +233,7 @@ static void *sh_timer_init(uint32_t freq, int feat, qemu_irq irq) { sh_timer_state *s; - s = (sh_timer_state *)g_malloc0(sizeof(sh_timer_state)); + s = g_malloc0(sizeof(*s)); s->freq = freq; s->feat = feat; s->tcor = 0xffffffff; @@ -358,7 +358,7 @@ void tmu012_init(MemoryRegion *sysmem, hwaddr base, tmu012_state *s; int timer_feat = (feat & TMU012_FEAT_EXTCLK) ? TIMER_FEAT_EXTCLK : 0; - s = (tmu012_state *)g_malloc0(sizeof(tmu012_state)); + s = g_malloc0(sizeof(*s)); s->feat = feat; s->timer[0] = sh_timer_init(freq, timer_feat, ch0_irq); s->timer[1] = sh_timer_init(freq, timer_feat, ch1_irq); -- cgit 1.4.1 From 3b885dabd09f449143adbfc0595896b47648673d Mon Sep 17 00:00:00 2001 From: BALATON Zoltan Date: Fri, 29 Oct 2021 23:02:09 +0200 Subject: hw/sh4: Fix typos in a comment MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: BALATON Zoltan Reviewed-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé Message-Id: Signed-off-by: Philippe Mathieu-Daudé --- hw/timer/sh_timer.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'hw/timer/sh_timer.c') diff --git a/hw/timer/sh_timer.c b/hw/timer/sh_timer.c index 02eb865908..cc7c1897a8 100644 --- a/hw/timer/sh_timer.c +++ b/hw/timer/sh_timer.c @@ -107,7 +107,7 @@ static void sh_timer_write(void *opaque, hwaddr offset, if (s->enabled) { /* * Pause the timer if it is running. This may cause some inaccuracy - * dure to rounding, but avoids a whole lot of other messyness + * due to rounding, but avoids a whole lot of other messiness */ ptimer_stop(s->timer); } -- cgit 1.4.1 From ad52cfc13750662fd003565e8035bb8ffbd4f0ef Mon Sep 17 00:00:00 2001 From: BALATON Zoltan Date: Fri, 29 Oct 2021 23:02:09 +0200 Subject: hw/sh4: Change debug printfs to traces MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: BALATON Zoltan Reviewed-by: Richard Henderson Message-Id: [PMD: Fixed format strings for 32-bit hosts] Signed-off-by: Philippe Mathieu-Daudé --- hw/char/sh_serial.c | 13 ++------- hw/char/trace-events | 4 +++ hw/intc/sh_intc.c | 79 +++++++++++++-------------------------------------- hw/intc/trace-events | 8 ++++++ hw/sh4/sh7750.c | 8 ++---- hw/sh4/trace-events | 3 ++ hw/sh4/trace.h | 1 + hw/timer/sh_timer.c | 22 +++----------- hw/timer/trace-events | 5 ++++ meson.build | 1 + 10 files changed, 52 insertions(+), 92 deletions(-) create mode 100644 hw/sh4/trace-events create mode 100644 hw/sh4/trace.h (limited to 'hw/timer/sh_timer.c') diff --git a/hw/char/sh_serial.c b/hw/char/sh_serial.c index 1b1e6a6a04..053f45e1a6 100644 --- a/hw/char/sh_serial.c +++ b/hw/char/sh_serial.c @@ -31,8 +31,7 @@ #include "chardev/char-fe.h" #include "qapi/error.h" #include "qemu/timer.h" - -//#define DEBUG_SERIAL +#include "trace.h" #define SH_SERIAL_FLAG_TEND (1 << 0) #define SH_SERIAL_FLAG_TDE (1 << 1) @@ -89,10 +88,7 @@ static void sh_serial_write(void *opaque, hwaddr offs, sh_serial_state *s = opaque; unsigned char ch; -#ifdef DEBUG_SERIAL - printf("sh_serial: write offs=0x%02x val=0x%02x\n", - offs, val); -#endif + trace_sh_serial_write(size, offs, val); switch (offs) { case 0x00: /* SMR */ s->smr = val & ((s->feat & SH_SERIAL_FEAT_SCIF) ? 0x7b : 0xff); @@ -301,10 +297,7 @@ static uint64_t sh_serial_read(void *opaque, hwaddr offs, break; } } -#ifdef DEBUG_SERIAL - printf("sh_serial: read offs=0x%02x val=0x%x\n", - offs, ret); -#endif + trace_sh_serial_read(size, offs, ret); if (ret & ~((1 << 16) - 1)) { fprintf(stderr, "sh_serial: unsupported read from 0x%02" diff --git a/hw/char/trace-events b/hw/char/trace-events index b774832af4..4a92e7674a 100644 --- a/hw/char/trace-events +++ b/hw/char/trace-events @@ -101,3 +101,7 @@ exynos_uart_rx_timeout(uint32_t channel, uint32_t stat, uint32_t intsp) "UART%d: # cadence_uart.c cadence_uart_baudrate(unsigned baudrate) "baudrate %u" + +# sh_serial.c +sh_serial_read(unsigned size, uint64_t offs, uint64_t val) " size %d offs 0x%02" PRIx64 " -> 0x%02" PRIx64 +sh_serial_write(unsigned size, uint64_t offs, uint64_t val) "size %d offs 0x%02" PRIx64 " <- 0x%02" PRIx64 diff --git a/hw/intc/sh_intc.c b/hw/intc/sh_intc.c index eddad7c195..673606b24b 100644 --- a/hw/intc/sh_intc.c +++ b/hw/intc/sh_intc.c @@ -9,13 +9,12 @@ */ #include "qemu/osdep.h" +#include "qemu/log.h" #include "cpu.h" #include "hw/sh4/sh_intc.h" #include "hw/irq.h" #include "hw/sh4/sh.h" - -//#define DEBUG_INTC -//#define DEBUG_INTC_SOURCES +#include "trace.h" #define INTC_A7(x) ((x) & 0x1fffffff) @@ -57,20 +56,14 @@ void sh_intc_toggle_source(struct intc_source *source, } } - if (enable_changed || assert_adj || pending_changed) { -#ifdef DEBUG_INTC_SOURCES - printf("sh_intc: (%d/%d/%d/%d) interrupt source 0x%x %s%s%s\n", - source->parent->pending, - source->asserted, - source->enable_count, - source->enable_max, - source->vect, - source->asserted ? "asserted " : - assert_adj ? "deasserted" : "", - enable_changed == 1 ? "enabled " : - enable_changed == -1 ? "disabled " : "", - source->pending ? "pending" : ""); -#endif + if (enable_changed || assert_adj || pending_changed) { + trace_sh_intc_sources(source->parent->pending, source->asserted, + source->enable_count, source->enable_max, + source->vect, source->asserted ? "asserted " : + assert_adj ? "deasserted" : "", + enable_changed == 1 ? "enabled " : + enable_changed == -1 ? "disabled " : "", + source->pending ? "pending" : ""); } } @@ -101,10 +94,7 @@ int sh_intc_get_pending_vector(struct intc_desc *desc, int imask) struct intc_source *source = desc->sources + i; if (source->pending) { -#ifdef DEBUG_INTC_SOURCES - printf("sh_intc: (%d) returning interrupt source 0x%x\n", - desc->pending, source->vect); -#endif + trace_sh_intc_pending(desc->pending, source->vect); return source->vect; } } @@ -199,30 +189,22 @@ static void sh_intc_toggle_mask(struct intc_desc *desc, intc_enum id, return; } if (!source->next_enum_id && (!source->enable_max || !source->vect)) { -#ifdef DEBUG_INTC_SOURCES - printf("sh_intc: reserved interrupt source %d modified\n", id); -#endif + qemu_log_mask(LOG_UNIMP, + "sh_intc: reserved interrupt source %d modified\n", id); return; } if (source->vect) { sh_intc_toggle_source(source, enable ? 1 : -1, 0); } -#ifdef DEBUG_INTC - else { - printf("setting interrupt group %d to %d\n", id, !!enable); - } -#endif if ((is_group || !source->vect) && source->next_enum_id) { sh_intc_toggle_mask(desc, source->next_enum_id, enable, 1); } -#ifdef DEBUG_INTC if (!source->vect) { - printf("setting interrupt group %d to %d - done\n", id, !!enable); + trace_sh_intc_set(id, !!enable); } -#endif } static uint64_t sh_intc_read(void *opaque, hwaddr offset, @@ -235,12 +217,9 @@ static uint64_t sh_intc_read(void *opaque, hwaddr offset, unsigned int mode = 0; unsigned long *valuep; -#ifdef DEBUG_INTC - printf("sh_intc_read 0x%lx\n", (unsigned long) offset); -#endif - sh_intc_locate(desc, (unsigned long)offset, &valuep, &enum_ids, &first, &width, &mode); + trace_sh_intc_read(size, (uint64_t)offset, *valuep); return *valuep; } @@ -256,13 +235,9 @@ static void sh_intc_write(void *opaque, hwaddr offset, unsigned long *valuep; unsigned long mask; -#ifdef DEBUG_INTC - printf("sh_intc_write 0x%lx 0x%08x\n", (unsigned long) offset, value); -#endif - + trace_sh_intc_write(size, (uint64_t)offset, value); sh_intc_locate(desc, (unsigned long)offset, &valuep, &enum_ids, &first, &width, &mode); - switch (mode) { case INTC_MODE_ENABLE_REG | INTC_MODE_IS_PRIO: break; @@ -282,18 +257,10 @@ static void sh_intc_write(void *opaque, hwaddr offset, if ((*valuep & mask) == (value & mask)) { continue; } -#if 0 - printf("k = %d, first = %d, enum = %d, mask = 0x%08x\n", - k, first, enum_ids[k], (unsigned int)mask); -#endif sh_intc_toggle_mask(desc, enum_ids[k], value & mask, 0); } *valuep = value; - -#ifdef DEBUG_INTC - printf("sh_intc_write 0x%lx -> 0x%08x\n", (unsigned long) offset, value); -#endif } static const MemoryRegionOps sh_intc_ops = { @@ -416,11 +383,8 @@ void sh_intc_register_sources(struct intc_desc *desc, s = sh_intc_source(desc, vect->enum_id); if (s) { s->vect = vect->vect; - -#ifdef DEBUG_INTC_SOURCES - printf("sh_intc: registered source %d -> 0x%04x (%d/%d)\n", - vect->enum_id, s->vect, s->enable_count, s->enable_max); -#endif + trace_sh_intc_register("source", vect->enum_id, s->vect, + s->enable_count, s->enable_max); } } @@ -438,11 +402,8 @@ void sh_intc_register_sources(struct intc_desc *desc, s = sh_intc_source(desc, gr->enum_ids[k - 1]); s->next_enum_id = gr->enum_ids[k]; } - -#ifdef DEBUG_INTC_SOURCES - printf("sh_intc: registered group %d (%d/%d)\n", - gr->enum_id, s->enable_count, s->enable_max); -#endif + trace_sh_intc_register("group", gr->enum_id, 0xffff, + s->enable_count, s->enable_max); } } } diff --git a/hw/intc/trace-events b/hw/intc/trace-events index 6a17d38998..9aba7e3a7a 100644 --- a/hw/intc/trace-events +++ b/hw/intc/trace-events @@ -238,3 +238,11 @@ goldfish_pic_write(void *dev, int idx, unsigned int addr, unsigned int size, uin goldfish_pic_reset(void *dev, int idx) "pic: %p goldfish-irq.%d" goldfish_pic_realize(void *dev, int idx) "pic: %p goldfish-irq.%d" goldfish_pic_instance_init(void *dev) "pic: %p goldfish-irq" + +# sh_intc.c +sh_intc_sources(int p, int a, int c, int m, unsigned short v, const char *s1, const char *s2, const char *s3) "(%d/%d/%d/%d) interrupt source 0x%x %s%s%s" +sh_intc_pending(int p, unsigned short v) "(%d) returning interrupt source 0x%x" +sh_intc_register(const char *s, int id, unsigned short v, int c, int m) "%s %u -> 0x%04x (%d/%d)" +sh_intc_read(unsigned size, uint64_t offset, unsigned long val) "size %u 0x%" PRIx64 " -> 0x%lx" +sh_intc_write(unsigned size, uint64_t offset, unsigned long val) "size %u 0x%" PRIx64 " <- 0x%lx" +sh_intc_set(int id, int enable) "setting interrupt group %d to %d" diff --git a/hw/sh4/sh7750.c b/hw/sh4/sh7750.c index ca7e261aba..6c702d627c 100644 --- a/hw/sh4/sh7750.c +++ b/hw/sh4/sh7750.c @@ -32,6 +32,7 @@ #include "hw/sh4/sh_intc.h" #include "hw/timer/tmu012.h" #include "exec/exec-all.h" +#include "trace.h" #define NB_DEVICES 4 @@ -147,15 +148,11 @@ static void porta_changed(SH7750State *s, uint16_t prev) uint16_t currenta, changes; int i, r = 0; -#if 0 - fprintf(stderr, "porta changed from 0x%04x to 0x%04x\n", - prev, porta_lines(s)); - fprintf(stderr, "pdtra=0x%04x, pctra=0x%08x\n", s->pdtra, s->pctra); -#endif currenta = porta_lines(s); if (currenta == prev) { return; } + trace_sh7750_porta(prev, currenta, s->pdtra, s->pctra); changes = currenta ^ prev; for (i = 0; i < NB_DEVICES; i++) { @@ -182,6 +179,7 @@ static void portb_changed(SH7750State *s, uint16_t prev) if (currentb == prev) { return; } + trace_sh7750_portb(prev, currentb, s->pdtrb, s->pctrb); changes = currentb ^ prev; for (i = 0; i < NB_DEVICES; i++) { diff --git a/hw/sh4/trace-events b/hw/sh4/trace-events new file mode 100644 index 0000000000..4b61cd56c8 --- /dev/null +++ b/hw/sh4/trace-events @@ -0,0 +1,3 @@ +# sh7750.c +sh7750_porta(uint16_t prev, uint16_t cur, uint16_t pdtr, uint16_t pctr) "porta changed from 0x%04x to 0x%04x\npdtra=0x%04x, pctra=0x%08x" +sh7750_portb(uint16_t prev, uint16_t cur, uint16_t pdtr, uint16_t pctr) "portb changed from 0x%04x to 0x%04x\npdtrb=0x%04x, pctrb=0x%08x" diff --git a/hw/sh4/trace.h b/hw/sh4/trace.h new file mode 100644 index 0000000000..e2c13323b7 --- /dev/null +++ b/hw/sh4/trace.h @@ -0,0 +1 @@ +#include "trace/trace-hw_sh4.h" diff --git a/hw/timer/sh_timer.c b/hw/timer/sh_timer.c index cc7c1897a8..e1b6145df8 100644 --- a/hw/timer/sh_timer.c +++ b/hw/timer/sh_timer.c @@ -15,8 +15,7 @@ #include "hw/sh4/sh.h" #include "hw/timer/tmu012.h" #include "hw/ptimer.h" - -//#define DEBUG_TIMER +#include "trace.h" #define TIMER_TCR_TPSC (7 << 0) #define TIMER_TCR_CKEG (3 << 3) @@ -203,10 +202,7 @@ static void sh_timer_start_stop(void *opaque, int enable) { sh_timer_state *s = (sh_timer_state *)opaque; -#ifdef DEBUG_TIMER - printf("sh_timer_start_stop %d (%d)\n", enable, s->enabled); -#endif - + trace_sh_timer_start_stop(enable, s->enabled); ptimer_transaction_begin(s->timer); if (s->enabled && !enable) { ptimer_stop(s->timer); @@ -216,10 +212,6 @@ static void sh_timer_start_stop(void *opaque, int enable) } ptimer_transaction_commit(s->timer); s->enabled = !!enable; - -#ifdef DEBUG_TIMER - printf("sh_timer_start_stop done %d\n", s->enabled); -#endif } static void sh_timer_tick(void *opaque) @@ -269,10 +261,7 @@ static uint64_t tmu012_read(void *opaque, hwaddr offset, { tmu012_state *s = (tmu012_state *)opaque; -#ifdef DEBUG_TIMER - printf("tmu012_read 0x%lx\n", (unsigned long) offset); -#endif - + trace_sh_timer_read(offset); if (offset >= 0x20) { if (!(s->feat & TMU012_FEAT_3CHAN)) { hw_error("tmu012_write: Bad channel offset %x\n", (int)offset); @@ -302,10 +291,7 @@ static void tmu012_write(void *opaque, hwaddr offset, { tmu012_state *s = (tmu012_state *)opaque; -#ifdef DEBUG_TIMER - printf("tmu012_write 0x%lx 0x%08x\n", (unsigned long) offset, value); -#endif - + trace_sh_timer_write(offset, value); if (offset >= 0x20) { if (!(s->feat & TMU012_FEAT_3CHAN)) { hw_error("tmu012_write: Bad channel offset %x\n", (int)offset); diff --git a/hw/timer/trace-events b/hw/timer/trace-events index d0edcd2a80..3eccef8385 100644 --- a/hw/timer/trace-events +++ b/hw/timer/trace-events @@ -94,3 +94,8 @@ sifive_pwm_set_alarm(uint64_t alarm, uint64_t now) "Setting alarm to: 0x%" PRIx6 sifive_pwm_interrupt(int num) "Interrupt %d" sifive_pwm_read(uint64_t offset) "Read at address: 0x%" PRIx64 sifive_pwm_write(uint64_t data, uint64_t offset) "Write 0x%" PRIx64 " at address: 0x%" PRIx64 + +# sh_timer.c +sh_timer_start_stop(int enable, int current) "%d (%d)" +sh_timer_read(uint64_t offset) "tmu012_read 0x%" PRIx64 +sh_timer_write(uint64_t offset, uint64_t value) "tmu012_write 0x%" PRIx64 " 0x%08" PRIx64 diff --git a/meson.build b/meson.build index 2c5b53cbe2..b092728397 100644 --- a/meson.build +++ b/meson.build @@ -2459,6 +2459,7 @@ if have_system 'hw/s390x', 'hw/scsi', 'hw/sd', + 'hw/sh4', 'hw/sparc', 'hw/sparc64', 'hw/ssi', -- cgit 1.4.1 From 5d9b737e5144baff1c3a4205ff57d974a347c204 Mon Sep 17 00:00:00 2001 From: BALATON Zoltan Date: Fri, 29 Oct 2021 23:02:09 +0200 Subject: hw/timer/sh_timer: Rename sh_timer_state to SHTimerState MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit According to coding style types should be camel case, also remove unneded casts from void *. Signed-off-by: BALATON Zoltan Reviewed-by: Philippe Mathieu-Daudé Message-Id: Signed-off-by: Philippe Mathieu-Daudé --- hw/timer/sh_timer.c | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) (limited to 'hw/timer/sh_timer.c') diff --git a/hw/timer/sh_timer.c b/hw/timer/sh_timer.c index e1b6145df8..2038adfb0a 100644 --- a/hw/timer/sh_timer.c +++ b/hw/timer/sh_timer.c @@ -45,11 +45,11 @@ typedef struct { int feat; int enabled; qemu_irq irq; -} sh_timer_state; +} SHTimerState; /* Check all active timers, and schedule the next timer interrupt. */ -static void sh_timer_update(sh_timer_state *s) +static void sh_timer_update(SHTimerState *s) { int new_level = s->int_level && (s->tcr & TIMER_TCR_UNIE); @@ -62,7 +62,7 @@ static void sh_timer_update(sh_timer_state *s) static uint32_t sh_timer_read(void *opaque, hwaddr offset) { - sh_timer_state *s = (sh_timer_state *)opaque; + SHTimerState *s = opaque; switch (offset >> 2) { case OFFSET_TCOR: @@ -85,7 +85,7 @@ static uint32_t sh_timer_read(void *opaque, hwaddr offset) static void sh_timer_write(void *opaque, hwaddr offset, uint32_t value) { - sh_timer_state *s = (sh_timer_state *)opaque; + SHTimerState *s = opaque; int freq; switch (offset >> 2) { @@ -200,7 +200,7 @@ static void sh_timer_write(void *opaque, hwaddr offset, static void sh_timer_start_stop(void *opaque, int enable) { - sh_timer_state *s = (sh_timer_state *)opaque; + SHTimerState *s = opaque; trace_sh_timer_start_stop(enable, s->enabled); ptimer_transaction_begin(s->timer); @@ -216,14 +216,14 @@ static void sh_timer_start_stop(void *opaque, int enable) static void sh_timer_tick(void *opaque) { - sh_timer_state *s = (sh_timer_state *)opaque; + SHTimerState *s = opaque; s->int_level = s->enabled; sh_timer_update(s); } static void *sh_timer_init(uint32_t freq, int feat, qemu_irq irq) { - sh_timer_state *s; + SHTimerState *s; s = g_malloc0(sizeof(*s)); s->freq = freq; @@ -259,7 +259,7 @@ typedef struct { static uint64_t tmu012_read(void *opaque, hwaddr offset, unsigned size) { - tmu012_state *s = (tmu012_state *)opaque; + tmu012_state *s = opaque; trace_sh_timer_read(offset); if (offset >= 0x20) { @@ -289,7 +289,7 @@ static uint64_t tmu012_read(void *opaque, hwaddr offset, static void tmu012_write(void *opaque, hwaddr offset, uint64_t value, unsigned size) { - tmu012_state *s = (tmu012_state *)opaque; + tmu012_state *s = opaque; trace_sh_timer_write(offset, value); if (offset >= 0x20) { -- cgit 1.4.1 From f64ccec414e72754921c25de6395d7e3b10a0c9e Mon Sep 17 00:00:00 2001 From: BALATON Zoltan Date: Fri, 29 Oct 2021 23:02:09 +0200 Subject: hw/timer/sh_timer: Do not wrap lines that are not too long MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit It's more readable to keep things on one line if it fits the length limit. Signed-off-by: BALATON Zoltan Reviewed-by: Philippe Mathieu-Daudé Message-Id: <97bc2a38991f33fd0c8cc2e4d0a3a29b20c47d1f.1635541329.git.balaton@eik.bme.hu> Signed-off-by: Philippe Mathieu-Daudé --- hw/timer/sh_timer.c | 9 +++------ 1 file changed, 3 insertions(+), 6 deletions(-) (limited to 'hw/timer/sh_timer.c') diff --git a/hw/timer/sh_timer.c b/hw/timer/sh_timer.c index 2038adfb0a..250ad41b48 100644 --- a/hw/timer/sh_timer.c +++ b/hw/timer/sh_timer.c @@ -82,8 +82,7 @@ static uint32_t sh_timer_read(void *opaque, hwaddr offset) } } -static void sh_timer_write(void *opaque, hwaddr offset, - uint32_t value) +static void sh_timer_write(void *opaque, hwaddr offset, uint32_t value) { SHTimerState *s = opaque; int freq; @@ -256,8 +255,7 @@ typedef struct { int feat; } tmu012_state; -static uint64_t tmu012_read(void *opaque, hwaddr offset, - unsigned size) +static uint64_t tmu012_read(void *opaque, hwaddr offset, unsigned size) { tmu012_state *s = opaque; @@ -336,8 +334,7 @@ static const MemoryRegionOps tmu012_ops = { .endianness = DEVICE_NATIVE_ENDIAN, }; -void tmu012_init(MemoryRegion *sysmem, hwaddr base, - int feat, uint32_t freq, +void tmu012_init(MemoryRegion *sysmem, hwaddr base, int feat, uint32_t freq, qemu_irq ch0_irq, qemu_irq ch1_irq, qemu_irq ch2_irq0, qemu_irq ch2_irq1) { -- cgit 1.4.1 From 65307c7792a50bffe036423ec21107f4fb9c74e3 Mon Sep 17 00:00:00 2001 From: BALATON Zoltan Date: Sat, 30 Oct 2021 01:27:40 +0200 Subject: hw/timer/sh_timer: Fix timer memory region size MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The timer unit only has registers that fit in a region 0x30 bytes long. No need to have the timer region larger than that. Signed-off-by: BALATON Zoltan Reviewed-by: Philippe Mathieu-Daudé Message-Id: Signed-off-by: Philippe Mathieu-Daudé --- hw/timer/sh_timer.c | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) (limited to 'hw/timer/sh_timer.c') diff --git a/hw/timer/sh_timer.c b/hw/timer/sh_timer.c index 250ad41b48..587fa9414a 100644 --- a/hw/timer/sh_timer.c +++ b/hw/timer/sh_timer.c @@ -350,15 +350,14 @@ void tmu012_init(MemoryRegion *sysmem, hwaddr base, int feat, uint32_t freq, ch2_irq0); /* ch2_irq1 not supported */ } - memory_region_init_io(&s->iomem, NULL, &tmu012_ops, s, - "timer", 0x100000000ULL); + memory_region_init_io(&s->iomem, NULL, &tmu012_ops, s, "timer", 0x30); memory_region_init_alias(&s->iomem_p4, NULL, "timer-p4", - &s->iomem, 0, 0x1000); + &s->iomem, 0, memory_region_size(&s->iomem)); memory_region_add_subregion(sysmem, P4ADDR(base), &s->iomem_p4); memory_region_init_alias(&s->iomem_a7, NULL, "timer-a7", - &s->iomem, 0, 0x1000); + &s->iomem, 0, memory_region_size(&s->iomem)); memory_region_add_subregion(sysmem, A7ADDR(base), &s->iomem_a7); /* ??? Save/restore. */ } -- cgit 1.4.1 From 46e44759fc24a05e338cd37a735b4aad5422e717 Mon Sep 17 00:00:00 2001 From: BALATON Zoltan Date: Fri, 29 Oct 2021 23:02:09 +0200 Subject: hw/timer/sh_timer: Remove use of hw_error MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The hw_error function calls abort and is not meant to be used by devices. Use qemu_log_mask instead to log and ignore invalid accesses. Also fix format strings to allow dropping type casts of hwaddr and use __func__ instead of hard coding function name in the message which were wrong in two cases. Signed-off-by: BALATON Zoltan Reviewed-by: Philippe Mathieu-Daudé Message-Id: Signed-off-by: Philippe Mathieu-Daudé --- hw/timer/sh_timer.c | 40 +++++++++++++++++++++++++--------------- 1 file changed, 25 insertions(+), 15 deletions(-) (limited to 'hw/timer/sh_timer.c') diff --git a/hw/timer/sh_timer.c b/hw/timer/sh_timer.c index 587fa9414a..c72c327bfa 100644 --- a/hw/timer/sh_timer.c +++ b/hw/timer/sh_timer.c @@ -10,7 +10,7 @@ #include "qemu/osdep.h" #include "exec/memory.h" -#include "hw/hw.h" +#include "qemu/log.h" #include "hw/irq.h" #include "hw/sh4/sh.h" #include "hw/timer/tmu012.h" @@ -75,11 +75,10 @@ static uint32_t sh_timer_read(void *opaque, hwaddr offset) if (s->feat & TIMER_FEAT_CAPT) { return s->tcpr; } - /* fall through */ - default: - hw_error("sh_timer_read: Bad offset %x\n", (int)offset); - return 0; } + qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIx "\n", + __func__, offset); + return 0; } static void sh_timer_write(void *opaque, hwaddr offset, uint32_t value) @@ -134,7 +133,8 @@ static void sh_timer_write(void *opaque, hwaddr offset, uint32_t value) } /* fallthrough */ default: - hw_error("sh_timer_write: Reserved TPSC value\n"); + qemu_log_mask(LOG_GUEST_ERROR, + "%s: Reserved TPSC value\n", __func__); } switch ((value & TIMER_TCR_CKEG) >> 3) { case 0: @@ -147,7 +147,8 @@ static void sh_timer_write(void *opaque, hwaddr offset, uint32_t value) } /* fallthrough */ default: - hw_error("sh_timer_write: Reserved CKEG value\n"); + qemu_log_mask(LOG_GUEST_ERROR, + "%s: Reserved CKEG value\n", __func__); } switch ((value & TIMER_TCR_ICPE) >> 6) { case 0: @@ -159,7 +160,8 @@ static void sh_timer_write(void *opaque, hwaddr offset, uint32_t value) } /* fallthrough */ default: - hw_error("sh_timer_write: Reserved ICPE value\n"); + qemu_log_mask(LOG_GUEST_ERROR, + "%s: Reserved ICPE value\n", __func__); } if ((value & TIMER_TCR_UNF) == 0) { s->int_level = 0; @@ -168,13 +170,15 @@ static void sh_timer_write(void *opaque, hwaddr offset, uint32_t value) value &= ~TIMER_TCR_UNF; if ((value & TIMER_TCR_ICPF) && (!(s->feat & TIMER_FEAT_CAPT))) { - hw_error("sh_timer_write: Reserved ICPF value\n"); + qemu_log_mask(LOG_GUEST_ERROR, + "%s: Reserved ICPF value\n", __func__); } value &= ~TIMER_TCR_ICPF; /* capture not supported */ if (value & TIMER_TCR_RESERVED) { - hw_error("sh_timer_write: Reserved TCR bits set\n"); + qemu_log_mask(LOG_GUEST_ERROR, + "%s: Reserved TCR bits set\n", __func__); } s->tcr = value; ptimer_set_limit(s->timer, s->tcor, 0); @@ -192,7 +196,8 @@ static void sh_timer_write(void *opaque, hwaddr offset, uint32_t value) } /* fallthrough */ default: - hw_error("sh_timer_write: Bad offset %x\n", (int)offset); + qemu_log_mask(LOG_GUEST_ERROR, + "%s: Bad offset 0x%" HWADDR_PRIx "\n", __func__, offset); } sh_timer_update(s); } @@ -262,7 +267,9 @@ static uint64_t tmu012_read(void *opaque, hwaddr offset, unsigned size) trace_sh_timer_read(offset); if (offset >= 0x20) { if (!(s->feat & TMU012_FEAT_3CHAN)) { - hw_error("tmu012_write: Bad channel offset %x\n", (int)offset); + qemu_log_mask(LOG_GUEST_ERROR, + "%s: Bad channel offset 0x%" HWADDR_PRIx "\n", + __func__, offset); } return sh_timer_read(s->timer[2], offset - 0x20); } @@ -280,7 +287,8 @@ static uint64_t tmu012_read(void *opaque, hwaddr offset, unsigned size) return s->tocr; } - hw_error("tmu012_write: Bad offset %x\n", (int)offset); + qemu_log_mask(LOG_GUEST_ERROR, + "%s: Bad offset 0x%" HWADDR_PRIx "\n", __func__, offset); return 0; } @@ -292,7 +300,9 @@ static void tmu012_write(void *opaque, hwaddr offset, trace_sh_timer_write(offset, value); if (offset >= 0x20) { if (!(s->feat & TMU012_FEAT_3CHAN)) { - hw_error("tmu012_write: Bad channel offset %x\n", (int)offset); + qemu_log_mask(LOG_GUEST_ERROR, + "%s: Bad channel offset 0x%" HWADDR_PRIx "\n", + __func__, offset); } sh_timer_write(s->timer[2], offset - 0x20, value); return; @@ -315,7 +325,7 @@ static void tmu012_write(void *opaque, hwaddr offset, sh_timer_start_stop(s->timer[2], value & (1 << 2)); } else { if (value & (1 << 2)) { - hw_error("tmu012_write: Bad channel\n"); + qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad channel\n", __func__); } } -- cgit 1.4.1