From 99df7dce8ae81e4a42dac98094ccca3a32dcf8f8 Mon Sep 17 00:00:00 2001 From: Andreas Färber Date: Mon, 26 Aug 2013 05:15:23 +0200 Subject: cpu: Move can_do_io field from CPU_COMMON to CPUState MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Rename can_do_io() to cpu_can_do_io() and change argument to CPUState. Signed-off-by: Andreas Färber --- include/exec/exec-all.h | 21 +++++++++++++-------- 1 file changed, 13 insertions(+), 8 deletions(-) (limited to 'include/exec/exec-all.h') diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index a387922df4..2179329916 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -380,20 +380,25 @@ extern int singlestep; /* cpu-exec.c */ extern volatile sig_atomic_t exit_request; -/* Deterministic execution requires that IO only be performed on the last - instruction of a TB so that interrupts take effect immediately. */ -static inline int can_do_io(CPUArchState *env) +/** + * cpu_can_do_io: + * @cpu: The CPU for which to check IO. + * + * Deterministic execution requires that IO only be performed on the last + * instruction of a TB so that interrupts take effect immediately. + * + * Returns: %true if memory-mapped IO is safe, %false otherwise. + */ +static inline bool cpu_can_do_io(CPUState *cpu) { - CPUState *cpu = ENV_GET_CPU(env); - if (!use_icount) { - return 1; + return true; } /* If not executing code then assume we are ok. */ if (cpu->current_tb == NULL) { - return 1; + return true; } - return env->can_do_io != 0; + return cpu->can_do_io != 0; } #endif -- cgit 1.4.1 From d5a11fefef1eeed86a8f06021067ba9990729a5a Mon Sep 17 00:00:00 2001 From: Andreas Färber Date: Tue, 27 Aug 2013 00:28:06 +0200 Subject: exec: Change tlb_fill() argument to CPUState MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Andreas Färber --- include/exec/exec-all.h | 2 +- include/exec/softmmu_template.h | 8 ++++---- target-alpha/mem_helper.c | 8 +++++--- target-arm/op_helper.c | 12 +++++++----- target-cris/op_helper.c | 7 ++++--- target-i386/mem_helper.c | 12 +++++++----- target-lm32/op_helper.c | 13 ++++++++----- target-m68k/op_helper.c | 8 +++++--- target-microblaze/op_helper.c | 13 ++++++++----- target-mips/op_helper.c | 7 ++++--- target-moxie/helper.c | 7 ++++--- target-openrisc/mmu_helper.c | 8 +++++--- target-ppc/mmu_helper.c | 9 +++++---- target-s390x/mem_helper.c | 8 +++++--- target-sh4/op_helper.c | 8 +++++--- target-sparc/ldst_helper.c | 8 +++++--- target-unicore32/op_helper.c | 8 +++++--- target-xtensa/op_helper.c | 6 ++++-- 18 files changed, 91 insertions(+), 61 deletions(-) (limited to 'include/exec/exec-all.h') diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index 2179329916..c8c3a1198b 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -332,7 +332,7 @@ bool io_mem_read(struct MemoryRegion *mr, hwaddr addr, bool io_mem_write(struct MemoryRegion *mr, hwaddr addr, uint64_t value, unsigned size); -void tlb_fill(CPUArchState *env1, target_ulong addr, int is_write, int mmu_idx, +void tlb_fill(CPUState *cpu, target_ulong addr, int is_write, int mmu_idx, uintptr_t retaddr); uint8_t helper_ldb_cmmu(CPUArchState *env, target_ulong addr, int mmu_idx); diff --git a/include/exec/softmmu_template.h b/include/exec/softmmu_template.h index ac825d251c..8603933dcb 100644 --- a/include/exec/softmmu_template.h +++ b/include/exec/softmmu_template.h @@ -158,7 +158,7 @@ WORD_TYPE helper_le_ld_name(CPUArchState *env, target_ulong addr, int mmu_idx, do_unaligned_access(env, addr, READ_ACCESS_TYPE, mmu_idx, retaddr); } #endif - tlb_fill(env, addr, READ_ACCESS_TYPE, mmu_idx, retaddr); + tlb_fill(ENV_GET_CPU(env), addr, READ_ACCESS_TYPE, mmu_idx, retaddr); tlb_addr = env->tlb_table[mmu_idx][index].ADDR_READ; } @@ -240,7 +240,7 @@ WORD_TYPE helper_be_ld_name(CPUArchState *env, target_ulong addr, int mmu_idx, do_unaligned_access(env, addr, READ_ACCESS_TYPE, mmu_idx, retaddr); } #endif - tlb_fill(env, addr, READ_ACCESS_TYPE, mmu_idx, retaddr); + tlb_fill(ENV_GET_CPU(env), addr, READ_ACCESS_TYPE, mmu_idx, retaddr); tlb_addr = env->tlb_table[mmu_idx][index].ADDR_READ; } @@ -360,7 +360,7 @@ void helper_le_st_name(CPUArchState *env, target_ulong addr, DATA_TYPE val, do_unaligned_access(env, addr, 1, mmu_idx, retaddr); } #endif - tlb_fill(env, addr, 1, mmu_idx, retaddr); + tlb_fill(ENV_GET_CPU(env), addr, 1, mmu_idx, retaddr); tlb_addr = env->tlb_table[mmu_idx][index].addr_write; } @@ -436,7 +436,7 @@ void helper_be_st_name(CPUArchState *env, target_ulong addr, DATA_TYPE val, do_unaligned_access(env, addr, 1, mmu_idx, retaddr); } #endif - tlb_fill(env, addr, 1, mmu_idx, retaddr); + tlb_fill(ENV_GET_CPU(env), addr, 1, mmu_idx, retaddr); tlb_addr = env->tlb_table[mmu_idx][index].addr_write; } diff --git a/target-alpha/mem_helper.c b/target-alpha/mem_helper.c index 23878bad80..3447f828ed 100644 --- a/target-alpha/mem_helper.c +++ b/target-alpha/mem_helper.c @@ -152,14 +152,16 @@ void alpha_cpu_unassigned_access(CPUState *cs, hwaddr addr, NULL, it means that the function was called in C code (i.e. not from generated code or from helper.c) */ /* XXX: fix it to restore all registers */ -void tlb_fill(CPUAlphaState *env, target_ulong addr, int is_write, +void tlb_fill(CPUState *cs, target_ulong addr, int is_write, int mmu_idx, uintptr_t retaddr) { - AlphaCPU *cpu = alpha_env_get_cpu(env); int ret; - ret = alpha_cpu_handle_mmu_fault(CPU(cpu), addr, is_write, mmu_idx); + ret = alpha_cpu_handle_mmu_fault(cs, addr, is_write, mmu_idx); if (unlikely(ret != 0)) { + AlphaCPU *cpu = ALPHA_CPU(cs); + CPUAlphaState *env = &cpu->env; + if (retaddr) { cpu_restore_state(env, retaddr); } diff --git a/target-arm/op_helper.c b/target-arm/op_helper.c index 931536ea4f..932f5e218d 100644 --- a/target-arm/op_helper.c +++ b/target-arm/op_helper.c @@ -72,17 +72,19 @@ uint32_t HELPER(neon_tbl)(CPUARMState *env, uint32_t ireg, uint32_t def, #include "exec/softmmu_template.h" /* try to fill the TLB and return an exception if error. If retaddr is - NULL, it means that the function was called in C code (i.e. not - from generated code or from helper.c) */ -void tlb_fill(CPUARMState *env, target_ulong addr, int is_write, int mmu_idx, + * NULL, it means that the function was called in C code (i.e. not + * from generated code or from helper.c) + */ +void tlb_fill(CPUState *cs, target_ulong addr, int is_write, int mmu_idx, uintptr_t retaddr) { - ARMCPU *cpu = arm_env_get_cpu(env); - CPUState *cs = CPU(cpu); int ret; ret = arm_cpu_handle_mmu_fault(cs, addr, is_write, mmu_idx); if (unlikely(ret)) { + ARMCPU *cpu = ARM_CPU(cs); + CPUARMState *env = &cpu->env; + if (retaddr) { /* now we have a real cpu fault */ cpu_restore_state(env, retaddr); diff --git a/target-cris/op_helper.c b/target-cris/op_helper.c index 9b20b94d9b..68a5caa2a7 100644 --- a/target-cris/op_helper.c +++ b/target-cris/op_helper.c @@ -54,15 +54,16 @@ /* Try to fill the TLB and return an exception if error. If retaddr is NULL, it means that the function was called in C code (i.e. not from generated code or from helper.c) */ -void tlb_fill(CPUCRISState *env, target_ulong addr, int is_write, int mmu_idx, +void tlb_fill(CPUState *cs, target_ulong addr, int is_write, int mmu_idx, uintptr_t retaddr) { - CRISCPU *cpu = cris_env_get_cpu(env); + CRISCPU *cpu = CRIS_CPU(cs); + CPUCRISState *env = &cpu->env; int ret; D_LOG("%s pc=%x tpc=%x ra=%p\n", __func__, env->pc, env->pregs[PR_EDA], (void *)retaddr); - ret = cris_cpu_handle_mmu_fault(CPU(cpu), addr, is_write, mmu_idx); + ret = cris_cpu_handle_mmu_fault(cs, addr, is_write, mmu_idx); if (unlikely(ret)) { if (retaddr) { /* now we have a real cpu fault */ diff --git a/target-i386/mem_helper.c b/target-i386/mem_helper.c index c0d3b45552..2f0691be8f 100644 --- a/target-i386/mem_helper.c +++ b/target-i386/mem_helper.c @@ -129,18 +129,20 @@ void helper_boundl(CPUX86State *env, target_ulong a0, int v) #if !defined(CONFIG_USER_ONLY) /* try to fill the TLB and return an exception if error. If retaddr is - NULL, it means that the function was called in C code (i.e. not - from generated code or from helper.c) */ + * NULL, it means that the function was called in C code (i.e. not + * from generated code or from helper.c) + */ /* XXX: fix it to restore all registers */ -void tlb_fill(CPUX86State *env, target_ulong addr, int is_write, int mmu_idx, +void tlb_fill(CPUState *cs, target_ulong addr, int is_write, int mmu_idx, uintptr_t retaddr) { - X86CPU *cpu = x86_env_get_cpu(env); - CPUState *cs = CPU(cpu); int ret; ret = x86_cpu_handle_mmu_fault(cs, addr, is_write, mmu_idx); if (ret) { + X86CPU *cpu = X86_CPU(cs); + CPUX86State *env = &cpu->env; + if (retaddr) { /* now we have a real cpu fault */ cpu_restore_state(env, retaddr); diff --git a/target-lm32/op_helper.c b/target-lm32/op_helper.c index 3b513a7edb..7fc9191e19 100644 --- a/target-lm32/op_helper.c +++ b/target-lm32/op_helper.c @@ -150,16 +150,19 @@ uint32_t HELPER(rcsr_jrx)(CPULM32State *env) } /* Try to fill the TLB and return an exception if error. If retaddr is - NULL, it means that the function was called in C code (i.e. not - from generated code or from helper.c) */ -void tlb_fill(CPULM32State *env, target_ulong addr, int is_write, int mmu_idx, + * NULL, it means that the function was called in C code (i.e. not + * from generated code or from helper.c) + */ +void tlb_fill(CPUState *cs, target_ulong addr, int is_write, int mmu_idx, uintptr_t retaddr) { - LM32CPU *cpu = lm32_env_get_cpu(env); int ret; - ret = lm32_cpu_handle_mmu_fault(CPU(cpu), addr, is_write, mmu_idx); + ret = lm32_cpu_handle_mmu_fault(cs, addr, is_write, mmu_idx); if (unlikely(ret)) { + LM32CPU *cpu = LM32_CPU(cs); + CPULM32State *env = &cpu->env; + if (retaddr) { /* now we have a real cpu fault */ cpu_restore_state(env, retaddr); diff --git a/target-m68k/op_helper.c b/target-m68k/op_helper.c index 930d7c8d04..b1745b8796 100644 --- a/target-m68k/op_helper.c +++ b/target-m68k/op_helper.c @@ -53,14 +53,16 @@ extern int semihosting_enabled; /* Try to fill the TLB and return an exception if error. If retaddr is NULL, it means that the function was called in C code (i.e. not from generated code or from helper.c) */ -void tlb_fill(CPUM68KState *env, target_ulong addr, int is_write, int mmu_idx, +void tlb_fill(CPUState *cs, target_ulong addr, int is_write, int mmu_idx, uintptr_t retaddr) { - M68kCPU *cpu = m68k_env_get_cpu(env); int ret; - ret = m68k_cpu_handle_mmu_fault(CPU(cpu), addr, is_write, mmu_idx); + ret = m68k_cpu_handle_mmu_fault(cs, addr, is_write, mmu_idx); if (unlikely(ret)) { + M68kCPU *cpu = M68K_CPU(cs); + CPUM68KState *env = &cpu->env; + if (retaddr) { /* now we have a real cpu fault */ cpu_restore_state(env, retaddr); diff --git a/target-microblaze/op_helper.c b/target-microblaze/op_helper.c index 318185a5df..9e394114c8 100644 --- a/target-microblaze/op_helper.c +++ b/target-microblaze/op_helper.c @@ -39,16 +39,19 @@ #include "exec/softmmu_template.h" /* Try to fill the TLB and return an exception if error. If retaddr is - NULL, it means that the function was called in C code (i.e. not - from generated code or from helper.c) */ -void tlb_fill(CPUMBState *env, target_ulong addr, int is_write, int mmu_idx, + * NULL, it means that the function was called in C code (i.e. not + * from generated code or from helper.c) + */ +void tlb_fill(CPUState *cs, target_ulong addr, int is_write, int mmu_idx, uintptr_t retaddr) { - MicroBlazeCPU *cpu = mb_env_get_cpu(env); int ret; - ret = mb_cpu_handle_mmu_fault(CPU(cpu), addr, is_write, mmu_idx); + ret = mb_cpu_handle_mmu_fault(cs, addr, is_write, mmu_idx); if (unlikely(ret)) { + MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs); + CPUMBState *env = &cpu->env; + if (retaddr) { /* now we have a real cpu fault */ cpu_restore_state(env, retaddr); diff --git a/target-mips/op_helper.c b/target-mips/op_helper.c index 5a4a656f3d..8c050fc247 100644 --- a/target-mips/op_helper.c +++ b/target-mips/op_helper.c @@ -2145,15 +2145,16 @@ static void do_unaligned_access(CPUMIPSState *env, target_ulong addr, do_raise_exception(env, (is_write == 1) ? EXCP_AdES : EXCP_AdEL, retaddr); } -void tlb_fill(CPUMIPSState *env, target_ulong addr, int is_write, int mmu_idx, +void tlb_fill(CPUState *cs, target_ulong addr, int is_write, int mmu_idx, uintptr_t retaddr) { - MIPSCPU *cpu = mips_env_get_cpu(env); - CPUState *cs = CPU(cpu); int ret; ret = mips_cpu_handle_mmu_fault(cs, addr, is_write, mmu_idx); if (ret) { + MIPSCPU *cpu = MIPS_CPU(cs); + CPUMIPSState *env = &cpu->env; + do_raise_exception_err(env, cs->exception_index, env->error_code, retaddr); } diff --git a/target-moxie/helper.c b/target-moxie/helper.c index 3b14f3735e..06a4c728ee 100644 --- a/target-moxie/helper.c +++ b/target-moxie/helper.c @@ -46,13 +46,14 @@ /* Try to fill the TLB and return an exception if error. If retaddr is NULL, it means that the function was called in C code (i.e. not from generated code or from helper.c) */ -void tlb_fill(CPUMoxieState *env, target_ulong addr, int is_write, int mmu_idx, +void tlb_fill(CPUState *cs, target_ulong addr, int is_write, int mmu_idx, uintptr_t retaddr) { - MoxieCPU *cpu = moxie_env_get_cpu(env); + MoxieCPU *cpu = MOXIE_CPU(cs); + CPUMoxieState *env = &cpu->env; int ret; - ret = moxie_cpu_handle_mmu_fault(CPU(cpu), addr, is_write, mmu_idx); + ret = moxie_cpu_handle_mmu_fault(cs, addr, is_write, mmu_idx); if (unlikely(ret)) { if (retaddr) { cpu_restore_state(env, retaddr); diff --git a/target-openrisc/mmu_helper.c b/target-openrisc/mmu_helper.c index b023a5fb98..e3fe6c7127 100644 --- a/target-openrisc/mmu_helper.c +++ b/target-openrisc/mmu_helper.c @@ -36,15 +36,17 @@ #define SHIFT 3 #include "exec/softmmu_template.h" -void tlb_fill(CPUOpenRISCState *env, target_ulong addr, int is_write, +void tlb_fill(CPUState *cs, target_ulong addr, int is_write, int mmu_idx, uintptr_t retaddr) { - OpenRISCCPU *cpu = openrisc_env_get_cpu(env); int ret; - ret = openrisc_cpu_handle_mmu_fault(CPU(cpu), addr, is_write, mmu_idx); + ret = openrisc_cpu_handle_mmu_fault(cs, addr, is_write, mmu_idx); if (ret) { + OpenRISCCPU *cpu = OPENRISC_CPU(cs); + CPUOpenRISCState *env = &cpu->env; + if (retaddr) { /* now we have a real cpu fault. */ cpu_restore_state(env, retaddr); diff --git a/target-ppc/mmu_helper.c b/target-ppc/mmu_helper.c index b6abd974e3..c0421848b1 100644 --- a/target-ppc/mmu_helper.c +++ b/target-ppc/mmu_helper.c @@ -2893,11 +2893,12 @@ void helper_booke206_tlbflush(CPUPPCState *env, uint32_t type) NULL, it means that the function was called in C code (i.e. not from generated code or from helper.c) */ /* XXX: fix it to restore all registers */ -void tlb_fill(CPUPPCState *env, target_ulong addr, int is_write, int mmu_idx, +void tlb_fill(CPUState *cs, target_ulong addr, int is_write, int mmu_idx, uintptr_t retaddr) { - CPUState *cpu = CPU(ppc_env_get_cpu(env)); - PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); + PowerPCCPU *cpu = POWERPC_CPU(cs); + PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs); + CPUPPCState *env = &cpu->env; int ret; if (pcc->handle_mmu_fault) { @@ -2910,6 +2911,6 @@ void tlb_fill(CPUPPCState *env, target_ulong addr, int is_write, int mmu_idx, /* now we have a real cpu fault */ cpu_restore_state(env, retaddr); } - helper_raise_exception_err(env, cpu->exception_index, env->error_code); + helper_raise_exception_err(env, cs->exception_index, env->error_code); } } diff --git a/target-s390x/mem_helper.c b/target-s390x/mem_helper.c index 411c32692a..1e74e4d7e4 100644 --- a/target-s390x/mem_helper.c +++ b/target-s390x/mem_helper.c @@ -44,14 +44,16 @@ NULL, it means that the function was called in C code (i.e. not from generated code or from helper.c) */ /* XXX: fix it to restore all registers */ -void tlb_fill(CPUS390XState *env, target_ulong addr, int is_write, int mmu_idx, +void tlb_fill(CPUState *cs, target_ulong addr, int is_write, int mmu_idx, uintptr_t retaddr) { - S390CPU *cpu = s390_env_get_cpu(env); int ret; - ret = s390_cpu_handle_mmu_fault(CPU(cpu), addr, is_write, mmu_idx); + ret = s390_cpu_handle_mmu_fault(cs, addr, is_write, mmu_idx); if (unlikely(ret != 0)) { + S390CPU *cpu = S390_CPU(cs); + CPUS390XState *env = &cpu->env; + if (likely(retaddr)) { /* now we have a real cpu fault */ cpu_restore_state(env, retaddr); diff --git a/target-sh4/op_helper.c b/target-sh4/op_helper.c index 03633f0ee8..6e527cfcf3 100644 --- a/target-sh4/op_helper.c +++ b/target-sh4/op_helper.c @@ -38,15 +38,17 @@ #define SHIFT 3 #include "exec/softmmu_template.h" -void tlb_fill(CPUSH4State *env, target_ulong addr, int is_write, int mmu_idx, +void tlb_fill(CPUState *cs, target_ulong addr, int is_write, int mmu_idx, uintptr_t retaddr) { - SuperHCPU *cpu = sh_env_get_cpu(env); int ret; - ret = superh_cpu_handle_mmu_fault(CPU(cpu), addr, is_write, mmu_idx); + ret = superh_cpu_handle_mmu_fault(cs, addr, is_write, mmu_idx); if (ret) { /* now we have a real cpu fault */ + SuperHCPU *cpu = SUPERH_CPU(cs); + CPUSH4State *env = &cpu->env; + if (retaddr) { cpu_restore_state(env, retaddr); } diff --git a/target-sparc/ldst_helper.c b/target-sparc/ldst_helper.c index e1475d0b0f..32d0bfda18 100644 --- a/target-sparc/ldst_helper.c +++ b/target-sparc/ldst_helper.c @@ -2438,14 +2438,16 @@ static void QEMU_NORETURN do_unaligned_access(CPUSPARCState *env, NULL, it means that the function was called in C code (i.e. not from generated code or from helper.c) */ /* XXX: fix it to restore all registers */ -void tlb_fill(CPUSPARCState *env, target_ulong addr, int is_write, int mmu_idx, +void tlb_fill(CPUState *cs, target_ulong addr, int is_write, int mmu_idx, uintptr_t retaddr) { - SPARCCPU *cpu = sparc_env_get_cpu(env); int ret; - ret = sparc_cpu_handle_mmu_fault(CPU(cpu), addr, is_write, mmu_idx); + ret = sparc_cpu_handle_mmu_fault(cs, addr, is_write, mmu_idx); if (ret) { + SPARCCPU *cpu = SPARC_CPU(cs); + CPUSPARCState *env = &cpu->env; + if (retaddr) { cpu_restore_state(env, retaddr); } diff --git a/target-unicore32/op_helper.c b/target-unicore32/op_helper.c index cd2cbef34f..3efc6a80a4 100644 --- a/target-unicore32/op_helper.c +++ b/target-unicore32/op_helper.c @@ -257,14 +257,16 @@ uint32_t HELPER(ror_cc)(CPUUniCore32State *env, uint32_t x, uint32_t i) #define SHIFT 3 #include "exec/softmmu_template.h" -void tlb_fill(CPUUniCore32State *env, target_ulong addr, int is_write, +void tlb_fill(CPUState *cs, target_ulong addr, int is_write, int mmu_idx, uintptr_t retaddr) { - UniCore32CPU *cpu = uc32_env_get_cpu(env); int ret; - ret = uc32_cpu_handle_mmu_fault(CPU(cpu), addr, is_write, mmu_idx); + ret = uc32_cpu_handle_mmu_fault(cs, addr, is_write, mmu_idx); if (unlikely(ret)) { + UniCore32CPU *cpu = UNICORE32_CPU(cs); + CPUUniCore32State *env = &cpu->env; + if (retaddr) { /* now we have a real cpu fault */ cpu_restore_state(env, retaddr); diff --git a/target-xtensa/op_helper.c b/target-xtensa/op_helper.c index a314ed0b9d..1c80e310ab 100644 --- a/target-xtensa/op_helper.c +++ b/target-xtensa/op_helper.c @@ -60,9 +60,11 @@ static void do_unaligned_access(CPUXtensaState *env, } } -void tlb_fill(CPUXtensaState *env, - target_ulong vaddr, int is_write, int mmu_idx, uintptr_t retaddr) +void tlb_fill(CPUState *cs, + target_ulong vaddr, int is_write, int mmu_idx, uintptr_t retaddr) { + XtensaCPU *cpu = XTENSA_CPU(cs); + CPUXtensaState *env = &cpu->env; uint32_t paddr; uint32_t page_size; unsigned access; -- cgit 1.4.1 From 5638d180d6c469fc4c56127a3c717e8b9f27d925 Mon Sep 17 00:00:00 2001 From: Andreas Färber Date: Tue, 27 Aug 2013 17:52:12 +0200 Subject: cpu-exec: Change cpu_loop_exit() argument to CPUState MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Andreas Färber --- cpu-exec.c | 14 ++++++-------- exec.c | 2 +- include/exec/exec-all.h | 2 +- target-alpha/helper.c | 4 ++-- target-alpha/mem_helper.c | 4 ++-- target-arm/op_helper.c | 8 ++++---- target-cris/op_helper.c | 4 ++-- target-i386/excp_helper.c | 2 +- target-i386/misc_helper.c | 7 +++---- target-i386/seg_helper.c | 2 +- target-i386/svm_helper.c | 8 ++++---- target-lm32/op_helper.c | 6 +++--- target-m68k/op_helper.c | 6 +++--- target-microblaze/op_helper.c | 4 ++-- target-mips/op_helper.c | 4 ++-- target-moxie/helper.c | 6 +++--- target-openrisc/exception.c | 2 +- target-openrisc/mmu_helper.c | 2 +- target-ppc/excp_helper.c | 2 +- target-s390x/cc_helper.c | 2 +- target-s390x/mem_helper.c | 6 +++--- target-s390x/misc_helper.c | 10 +++++----- target-sh4/op_helper.c | 4 ++-- target-sparc/helper.c | 6 +++--- target-sparc/ldst_helper.c | 2 +- target-unicore32/op_helper.c | 4 ++-- target-xtensa/op_helper.c | 4 ++-- user-exec.c | 4 ++-- 28 files changed, 64 insertions(+), 67 deletions(-) (limited to 'include/exec/exec-all.h') diff --git a/cpu-exec.c b/cpu-exec.c index d7c21d35e5..192620f37b 100644 --- a/cpu-exec.c +++ b/cpu-exec.c @@ -23,10 +23,8 @@ #include "qemu/atomic.h" #include "sysemu/qtest.h" -void cpu_loop_exit(CPUArchState *env) +void cpu_loop_exit(CPUState *cpu) { - CPUState *cpu = ENV_GET_CPU(env); - cpu->current_tb = NULL; siglongjmp(cpu->jmp_env, 1); } @@ -325,7 +323,7 @@ int cpu_exec(CPUArchState *env) if (interrupt_request & CPU_INTERRUPT_DEBUG) { cpu->interrupt_request &= ~CPU_INTERRUPT_DEBUG; cpu->exception_index = EXCP_DEBUG; - cpu_loop_exit(env); + cpu_loop_exit(cpu); } #if defined(TARGET_ARM) || defined(TARGET_SPARC) || defined(TARGET_MIPS) || \ defined(TARGET_PPC) || defined(TARGET_ALPHA) || defined(TARGET_CRIS) || \ @@ -334,7 +332,7 @@ int cpu_exec(CPUArchState *env) cpu->interrupt_request &= ~CPU_INTERRUPT_HALT; cpu->halted = 1; cpu->exception_index = EXCP_HLT; - cpu_loop_exit(env); + cpu_loop_exit(cpu); } #endif #if defined(TARGET_I386) @@ -349,7 +347,7 @@ int cpu_exec(CPUArchState *env) 0); do_cpu_init(x86_cpu); cpu->exception_index = EXCP_HALTED; - cpu_loop_exit(env); + cpu_loop_exit(cpu); } else if (interrupt_request & CPU_INTERRUPT_SIPI) { do_cpu_sipi(x86_cpu); } else if (env->hflags2 & HF2_GIF_MASK) { @@ -601,7 +599,7 @@ int cpu_exec(CPUArchState *env) if (unlikely(cpu->exit_request)) { cpu->exit_request = 0; cpu->exception_index = EXCP_INTERRUPT; - cpu_loop_exit(env); + cpu_loop_exit(cpu); } spin_lock(&tcg_ctx.tb_ctx.tb_lock); tb = tb_find_fast(env); @@ -672,7 +670,7 @@ int cpu_exec(CPUArchState *env) } cpu->exception_index = EXCP_INTERRUPT; next_tb = 0; - cpu_loop_exit(env); + cpu_loop_exit(cpu); } break; } diff --git a/exec.c b/exec.c index 6d9e13a0a6..5f7c47244f 100644 --- a/exec.c +++ b/exec.c @@ -1608,7 +1608,7 @@ static void check_watchpoint(int offset, int len_mask, int flags) tb_check_watchpoint(env); if (wp->flags & BP_STOP_BEFORE_ACCESS) { cpu->exception_index = EXCP_DEBUG; - cpu_loop_exit(env); + cpu_loop_exit(cpu); } else { cpu_get_tb_cpu_state(env, &pc, &cs_base, &cpu_flags); tb_gen_code(env, pc, cs_base, cpu_flags, 1); diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index c8c3a1198b..80277eac32 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -89,7 +89,7 @@ TranslationBlock *tb_gen_code(CPUArchState *env, target_ulong pc, target_ulong cs_base, int flags, int cflags); void cpu_exec_init(CPUArchState *env); -void QEMU_NORETURN cpu_loop_exit(CPUArchState *env1); +void QEMU_NORETURN cpu_loop_exit(CPUState *cpu); int page_unprotect(target_ulong address, uintptr_t pc, void *puc); void tb_invalidate_phys_page_range(tb_page_addr_t start, tb_page_addr_t end, int is_cpu_write_access); diff --git a/target-alpha/helper.c b/target-alpha/helper.c index 14f59a27a8..45f73e0ea2 100644 --- a/target-alpha/helper.c +++ b/target-alpha/helper.c @@ -513,7 +513,7 @@ void QEMU_NORETURN helper_excp(CPUAlphaState *env, int excp, int error) cs->exception_index = excp; env->error_code = error; - cpu_loop_exit(env); + cpu_loop_exit(cs); } /* This may be called from any of the helpers to set up EXCEPTION_INDEX. */ @@ -528,7 +528,7 @@ void QEMU_NORETURN dynamic_excp(CPUAlphaState *env, uintptr_t retaddr, if (retaddr) { cpu_restore_state(env, retaddr); } - cpu_loop_exit(env); + cpu_loop_exit(cs); } void QEMU_NORETURN arith_excp(CPUAlphaState *env, uintptr_t retaddr, diff --git a/target-alpha/mem_helper.c b/target-alpha/mem_helper.c index 3447f828ed..1957c566b9 100644 --- a/target-alpha/mem_helper.c +++ b/target-alpha/mem_helper.c @@ -116,7 +116,7 @@ static void do_unaligned_access(CPUAlphaState *env, target_ulong addr, env->trap_arg2 = (insn >> 21) & 31; /* dest regno */ cs->exception_index = EXCP_UNALIGN; env->error_code = 0; - cpu_loop_exit(env); + cpu_loop_exit(cs); } void alpha_cpu_unassigned_access(CPUState *cs, hwaddr addr, @@ -166,7 +166,7 @@ void tlb_fill(CPUState *cs, target_ulong addr, int is_write, cpu_restore_state(env, retaddr); } /* Exception index and error code are already set */ - cpu_loop_exit(env); + cpu_loop_exit(cs); } } #endif /* CONFIG_USER_ONLY */ diff --git a/target-arm/op_helper.c b/target-arm/op_helper.c index 932f5e218d..f8e535e8ce 100644 --- a/target-arm/op_helper.c +++ b/target-arm/op_helper.c @@ -28,7 +28,7 @@ static void raise_exception(CPUARMState *env, int tt) CPUState *cs = CPU(cpu); cs->exception_index = tt; - cpu_loop_exit(env); + cpu_loop_exit(cs); } uint32_t HELPER(neon_tbl)(CPUARMState *env, uint32_t ireg, uint32_t def, @@ -229,7 +229,7 @@ void HELPER(wfi)(CPUARMState *env) cs->exception_index = EXCP_HLT; cs->halted = 1; - cpu_loop_exit(env); + cpu_loop_exit(cs); } void HELPER(wfe)(CPUARMState *env) @@ -240,7 +240,7 @@ void HELPER(wfe)(CPUARMState *env) * level loop */ cs->exception_index = EXCP_YIELD; - cpu_loop_exit(env); + cpu_loop_exit(cs); } void HELPER(exception)(CPUARMState *env, uint32_t excp) @@ -248,7 +248,7 @@ void HELPER(exception)(CPUARMState *env, uint32_t excp) CPUState *cs = CPU(arm_env_get_cpu(env)); cs->exception_index = excp; - cpu_loop_exit(env); + cpu_loop_exit(cs); } uint32_t HELPER(cpsr_read)(CPUARMState *env) diff --git a/target-cris/op_helper.c b/target-cris/op_helper.c index 68a5caa2a7..d80b6c966d 100644 --- a/target-cris/op_helper.c +++ b/target-cris/op_helper.c @@ -72,7 +72,7 @@ void tlb_fill(CPUState *cs, target_ulong addr, int is_write, int mmu_idx, helper_top_evaluate_flags(env); } } - cpu_loop_exit(env); + cpu_loop_exit(cs); } } @@ -83,7 +83,7 @@ void helper_raise_exception(CPUCRISState *env, uint32_t index) CPUState *cs = CPU(cris_env_get_cpu(env)); cs->exception_index = index; - cpu_loop_exit(env); + cpu_loop_exit(cs); } void helper_tlb_flush_pid(CPUCRISState *env, uint32_t pid) diff --git a/target-i386/excp_helper.c b/target-i386/excp_helper.c index ec76eba760..f337fd20fb 100644 --- a/target-i386/excp_helper.c +++ b/target-i386/excp_helper.c @@ -108,7 +108,7 @@ static void QEMU_NORETURN raise_interrupt2(CPUX86State *env, int intno, env->error_code = error_code; env->exception_is_int = is_int; env->exception_next_eip = env->eip + next_eip_addend; - cpu_loop_exit(env); + cpu_loop_exit(cs); } /* shortcuts to generate exceptions */ diff --git a/target-i386/misc_helper.c b/target-i386/misc_helper.c index 582ad34ffe..8c6b9bfce2 100644 --- a/target-i386/misc_helper.c +++ b/target-i386/misc_helper.c @@ -569,11 +569,10 @@ void helper_rdmsr(CPUX86State *env) static void do_pause(X86CPU *cpu) { CPUState *cs = CPU(cpu); - CPUX86State *env = &cpu->env; /* Just let another CPU run. */ cs->exception_index = EXCP_INTERRUPT; - cpu_loop_exit(env); + cpu_loop_exit(cs); } static void do_hlt(X86CPU *cpu) @@ -584,7 +583,7 @@ static void do_hlt(X86CPU *cpu) env->hflags &= ~HF_INHIBIT_IRQ_MASK; /* needed if sti is just before */ cs->halted = 1; cs->exception_index = EXCP_HLT; - cpu_loop_exit(env); + cpu_loop_exit(cs); } void helper_hlt(CPUX86State *env, int next_eip_addend) @@ -642,5 +641,5 @@ void helper_debug(CPUX86State *env) CPUState *cs = CPU(x86_env_get_cpu(env)); cs->exception_index = EXCP_DEBUG; - cpu_loop_exit(env); + cpu_loop_exit(cs); } diff --git a/target-i386/seg_helper.c b/target-i386/seg_helper.c index c8fd572d99..4e134e4338 100644 --- a/target-i386/seg_helper.c +++ b/target-i386/seg_helper.c @@ -939,7 +939,7 @@ void helper_syscall(CPUX86State *env, int next_eip_addend) cs->exception_index = EXCP_SYSCALL; env->exception_next_eip = env->eip + next_eip_addend; - cpu_loop_exit(env); + cpu_loop_exit(cs); } #else void helper_syscall(CPUX86State *env, int next_eip_addend) diff --git a/target-i386/svm_helper.c b/target-i386/svm_helper.c index 5e0504d7f0..de2c2eebe0 100644 --- a/target-i386/svm_helper.c +++ b/target-i386/svm_helper.c @@ -334,7 +334,7 @@ void helper_vmrun(CPUX86State *env, int aflag, int next_eip_addend) env->exception_is_int = 0; env->exception_next_eip = env->eip; qemu_log_mask(CPU_LOG_TB_IN_ASM, "NMI"); - cpu_loop_exit(env); + cpu_loop_exit(cs); break; case SVM_EVTINJ_TYPE_EXEPT: cs->exception_index = vector; @@ -342,7 +342,7 @@ void helper_vmrun(CPUX86State *env, int aflag, int next_eip_addend) env->exception_is_int = 0; env->exception_next_eip = -1; qemu_log_mask(CPU_LOG_TB_IN_ASM, "EXEPT"); - cpu_loop_exit(env); + cpu_loop_exit(cs); break; case SVM_EVTINJ_TYPE_SOFT: cs->exception_index = vector; @@ -350,7 +350,7 @@ void helper_vmrun(CPUX86State *env, int aflag, int next_eip_addend) env->exception_is_int = 1; env->exception_next_eip = env->eip; qemu_log_mask(CPU_LOG_TB_IN_ASM, "SOFT"); - cpu_loop_exit(env); + cpu_loop_exit(cs); break; } qemu_log_mask(CPU_LOG_TB_IN_ASM, " %#x %#x\n", cs->exception_index, @@ -772,7 +772,7 @@ void helper_vmexit(CPUX86State *env, uint32_t exit_code, uint64_t exit_info_1) env->error_code = 0; env->old_exception = -1; - cpu_loop_exit(env); + cpu_loop_exit(cs); } void cpu_vmexit(CPUX86State *env, uint32_t exit_code, uint64_t exit_info_1) diff --git a/target-lm32/op_helper.c b/target-lm32/op_helper.c index 7fc9191e19..f0859aab6d 100644 --- a/target-lm32/op_helper.c +++ b/target-lm32/op_helper.c @@ -28,7 +28,7 @@ void raise_exception(CPULM32State *env, int index) CPUState *cs = CPU(lm32_env_get_cpu(env)); cs->exception_index = index; - cpu_loop_exit(env); + cpu_loop_exit(cs); } void HELPER(raise_exception)(CPULM32State *env, uint32_t index) @@ -42,7 +42,7 @@ void HELPER(hlt)(CPULM32State *env) cs->halted = 1; cs->exception_index = EXCP_HLT; - cpu_loop_exit(env); + cpu_loop_exit(cs); } void HELPER(ill)(CPULM32State *env) @@ -167,7 +167,7 @@ void tlb_fill(CPUState *cs, target_ulong addr, int is_write, int mmu_idx, /* now we have a real cpu fault */ cpu_restore_state(env, retaddr); } - cpu_loop_exit(env); + cpu_loop_exit(cs); } } #endif diff --git a/target-m68k/op_helper.c b/target-m68k/op_helper.c index b1745b8796..d6268cd6b9 100644 --- a/target-m68k/op_helper.c +++ b/target-m68k/op_helper.c @@ -67,7 +67,7 @@ void tlb_fill(CPUState *cs, target_ulong addr, int is_write, int mmu_idx, /* now we have a real cpu fault */ cpu_restore_state(env, retaddr); } - cpu_loop_exit(env); + cpu_loop_exit(cs); } } @@ -114,7 +114,7 @@ static void do_interrupt_all(CPUM68KState *env, int is_hw) } cs->halted = 1; cs->exception_index = EXCP_HLT; - cpu_loop_exit(env); + cpu_loop_exit(cs); return; } if (cs->exception_index >= EXCP_TRAP0 @@ -170,7 +170,7 @@ static void raise_exception(CPUM68KState *env, int tt) CPUState *cs = CPU(m68k_env_get_cpu(env)); cs->exception_index = tt; - cpu_loop_exit(env); + cpu_loop_exit(cs); } void HELPER(raise_exception)(CPUM68KState *env, uint32_t tt) diff --git a/target-microblaze/op_helper.c b/target-microblaze/op_helper.c index 9e394114c8..f47613241d 100644 --- a/target-microblaze/op_helper.c +++ b/target-microblaze/op_helper.c @@ -56,7 +56,7 @@ void tlb_fill(CPUState *cs, target_ulong addr, int is_write, int mmu_idx, /* now we have a real cpu fault */ cpu_restore_state(env, retaddr); } - cpu_loop_exit(env); + cpu_loop_exit(cs); } } #endif @@ -101,7 +101,7 @@ void helper_raise_exception(CPUMBState *env, uint32_t index) CPUState *cs = CPU(mb_env_get_cpu(env)); cs->exception_index = index; - cpu_loop_exit(env); + cpu_loop_exit(cs); } void helper_debug(CPUMBState *env) diff --git a/target-mips/op_helper.c b/target-mips/op_helper.c index 8c050fc247..c65350187f 100644 --- a/target-mips/op_helper.c +++ b/target-mips/op_helper.c @@ -51,7 +51,7 @@ static inline void QEMU_NORETURN do_raise_exception_err(CPUMIPSState *env, cpu_restore_state(env, pc); } - cpu_loop_exit(env); + cpu_loop_exit(cs); } static inline void QEMU_NORETURN do_raise_exception(CPUMIPSState *env, @@ -280,7 +280,7 @@ static inline hwaddr do_translate_address(CPUMIPSState *env, lladdr = cpu_mips_translate_address(env, address, rw); if (lladdr == -1LL) { - cpu_loop_exit(env); + cpu_loop_exit(CPU(mips_env_get_cpu(env))); } else { return lladdr; } diff --git a/target-moxie/helper.c b/target-moxie/helper.c index 06a4c728ee..3994c0910d 100644 --- a/target-moxie/helper.c +++ b/target-moxie/helper.c @@ -59,7 +59,7 @@ void tlb_fill(CPUState *cs, target_ulong addr, int is_write, int mmu_idx, cpu_restore_state(env, retaddr); } } - cpu_loop_exit(env); + cpu_loop_exit(cs); } void helper_raise_exception(CPUMoxieState *env, int ex) @@ -74,7 +74,7 @@ void helper_raise_exception(CPUMoxieState *env, int ex) env->sregs[5] = env->pc; /* Jump the the exception handline routine. */ env->pc = env->sregs[1]; - cpu_loop_exit(env); + cpu_loop_exit(cs); } uint32_t helper_div(CPUMoxieState *env, uint32_t a, uint32_t b) @@ -104,7 +104,7 @@ void helper_debug(CPUMoxieState *env) CPUState *cs = CPU(moxie_env_get_cpu(env)); cs->exception_index = EXCP_DEBUG; - cpu_loop_exit(env); + cpu_loop_exit(cs); } #if defined(CONFIG_USER_ONLY) diff --git a/target-openrisc/exception.c b/target-openrisc/exception.c index b96f3f8963..74652a58f6 100644 --- a/target-openrisc/exception.c +++ b/target-openrisc/exception.c @@ -25,5 +25,5 @@ void QEMU_NORETURN raise_exception(OpenRISCCPU *cpu, uint32_t excp) CPUState *cs = CPU(cpu); cs->exception_index = excp; - cpu_loop_exit(&cpu->env); + cpu_loop_exit(cs); } diff --git a/target-openrisc/mmu_helper.c b/target-openrisc/mmu_helper.c index e3fe6c7127..5f7f6f5ac4 100644 --- a/target-openrisc/mmu_helper.c +++ b/target-openrisc/mmu_helper.c @@ -52,7 +52,7 @@ void tlb_fill(CPUState *cs, target_ulong addr, int is_write, cpu_restore_state(env, retaddr); } /* Raise Exception. */ - cpu_loop_exit(env); + cpu_loop_exit(cs); } } #endif diff --git a/target-ppc/excp_helper.c b/target-ppc/excp_helper.c index a58655b5c7..4a587303a8 100644 --- a/target-ppc/excp_helper.c +++ b/target-ppc/excp_helper.c @@ -823,7 +823,7 @@ void helper_raise_exception_err(CPUPPCState *env, uint32_t exception, #endif cs->exception_index = exception; env->error_code = error_code; - cpu_loop_exit(env); + cpu_loop_exit(cs); } void helper_raise_exception(CPUPPCState *env, uint32_t exception) diff --git a/target-s390x/cc_helper.c b/target-s390x/cc_helper.c index a6d60bf885..d845f20de5 100644 --- a/target-s390x/cc_helper.c +++ b/target-s390x/cc_helper.c @@ -548,7 +548,7 @@ uint32_t HELPER(calc_cc)(CPUS390XState *env, uint32_t cc_op, uint64_t src, void HELPER(load_psw)(CPUS390XState *env, uint64_t mask, uint64_t addr) { load_psw(env, mask, addr); - cpu_loop_exit(env); + cpu_loop_exit(CPU(s390_env_get_cpu(env))); } void HELPER(sacf)(CPUS390XState *env, uint64_t a1) diff --git a/target-s390x/mem_helper.c b/target-s390x/mem_helper.c index 1e74e4d7e4..e89fcac4e2 100644 --- a/target-s390x/mem_helper.c +++ b/target-s390x/mem_helper.c @@ -58,7 +58,7 @@ void tlb_fill(CPUState *cs, target_ulong addr, int is_write, int mmu_idx, /* now we have a real cpu fault */ cpu_restore_state(env, retaddr); } - cpu_loop_exit(env); + cpu_loop_exit(cs); } } @@ -971,12 +971,12 @@ static uint32_t mvc_asc(CPUS390XState *env, int64_t l, uint64_t a1, } if (mmu_translate(env, a1 & TARGET_PAGE_MASK, 1, mode1, &dest, &flags)) { - cpu_loop_exit(env); + cpu_loop_exit(CPU(s390_env_get_cpu(env))); } dest |= a1 & ~TARGET_PAGE_MASK; if (mmu_translate(env, a2 & TARGET_PAGE_MASK, 0, mode2, &src, &flags)) { - cpu_loop_exit(env); + cpu_loop_exit(CPU(s390_env_get_cpu(env))); } src |= a2 & ~TARGET_PAGE_MASK; diff --git a/target-s390x/misc_helper.c b/target-s390x/misc_helper.c index 69da9e56a9..2beec61a2b 100644 --- a/target-s390x/misc_helper.c +++ b/target-s390x/misc_helper.c @@ -61,7 +61,7 @@ void QEMU_NORETURN runtime_exception(CPUS390XState *env, int excp, env->int_pgm_ilen = t = get_ilen(t); env->psw.addr += 2 * t; - cpu_loop_exit(env); + cpu_loop_exit(cs); } /* Raise an exception statically from a TB. */ @@ -71,7 +71,7 @@ void HELPER(exception)(CPUS390XState *env, uint32_t excp) HELPER_LOG("%s: exception %d\n", __func__, excp); cs->exception_index = excp; - cpu_loop_exit(env); + cpu_loop_exit(cs); } #ifndef CONFIG_USER_ONLY @@ -93,7 +93,7 @@ void program_interrupt(CPUS390XState *env, uint32_t code, int ilen) env->int_pgm_code = code; env->int_pgm_ilen = ilen; cs->exception_index = EXCP_PGM; - cpu_loop_exit(env); + cpu_loop_exit(cs); } } @@ -456,11 +456,11 @@ uint32_t HELPER(sigp)(CPUS390XState *env, uint64_t order_code, uint32_t r1, #if !defined(CONFIG_USER_ONLY) case SIGP_RESTART: qemu_system_reset_request(); - cpu_loop_exit(env); + cpu_loop_exit(CPU(s390_env_get_cpu(env))); break; case SIGP_STOP: qemu_system_shutdown_request(); - cpu_loop_exit(env); + cpu_loop_exit(CPU(s390_env_get_cpu(env))); break; #endif default: diff --git a/target-sh4/op_helper.c b/target-sh4/op_helper.c index 6e527cfcf3..271401f699 100644 --- a/target-sh4/op_helper.c +++ b/target-sh4/op_helper.c @@ -52,7 +52,7 @@ void tlb_fill(CPUState *cs, target_ulong addr, int is_write, int mmu_idx, if (retaddr) { cpu_restore_state(env, retaddr); } - cpu_loop_exit(env); + cpu_loop_exit(cs); } } @@ -77,7 +77,7 @@ static inline void QEMU_NORETURN raise_exception(CPUSH4State *env, int index, if (retaddr) { cpu_restore_state(env, retaddr); } - cpu_loop_exit(env); + cpu_loop_exit(cs); } void helper_raise_illegal_instruction(CPUSH4State *env) diff --git a/target-sparc/helper.c b/target-sparc/helper.c index a393ef0a48..fb5f6ecd38 100644 --- a/target-sparc/helper.c +++ b/target-sparc/helper.c @@ -27,7 +27,7 @@ void helper_raise_exception(CPUSPARCState *env, int tt) CPUState *cs = CPU(sparc_env_get_cpu(env)); cs->exception_index = tt; - cpu_loop_exit(env); + cpu_loop_exit(cs); } void helper_debug(CPUSPARCState *env) @@ -35,7 +35,7 @@ void helper_debug(CPUSPARCState *env) CPUState *cs = CPU(sparc_env_get_cpu(env)); cs->exception_index = EXCP_DEBUG; - cpu_loop_exit(env); + cpu_loop_exit(cs); } #ifdef TARGET_SPARC64 @@ -239,6 +239,6 @@ void helper_power_down(CPUSPARCState *env) cs->exception_index = EXCP_HLT; env->pc = env->npc; env->npc = env->pc + 4; - cpu_loop_exit(env); + cpu_loop_exit(cs); } #endif diff --git a/target-sparc/ldst_helper.c b/target-sparc/ldst_helper.c index 32d0bfda18..8302bb14c2 100644 --- a/target-sparc/ldst_helper.c +++ b/target-sparc/ldst_helper.c @@ -2451,7 +2451,7 @@ void tlb_fill(CPUState *cs, target_ulong addr, int is_write, int mmu_idx, if (retaddr) { cpu_restore_state(env, retaddr); } - cpu_loop_exit(env); + cpu_loop_exit(cs); } } #endif diff --git a/target-unicore32/op_helper.c b/target-unicore32/op_helper.c index 3efc6a80a4..c2bf834c27 100644 --- a/target-unicore32/op_helper.c +++ b/target-unicore32/op_helper.c @@ -19,7 +19,7 @@ void HELPER(exception)(CPUUniCore32State *env, uint32_t excp) CPUState *cs = CPU(uc32_env_get_cpu(env)); cs->exception_index = excp; - cpu_loop_exit(env); + cpu_loop_exit(cs); } static target_ulong asr_read(CPUUniCore32State *env) @@ -271,7 +271,7 @@ void tlb_fill(CPUState *cs, target_ulong addr, int is_write, /* now we have a real cpu fault */ cpu_restore_state(env, retaddr); } - cpu_loop_exit(env); + cpu_loop_exit(cs); } } #endif diff --git a/target-xtensa/op_helper.c b/target-xtensa/op_helper.c index 1c80e310ab..42653784cd 100644 --- a/target-xtensa/op_helper.c +++ b/target-xtensa/op_helper.c @@ -105,7 +105,7 @@ void HELPER(exception)(CPUXtensaState *env, uint32_t excp) if (excp == EXCP_DEBUG) { env->exception_taken = 0; } - cpu_loop_exit(env); + cpu_loop_exit(cs); } void HELPER(exception_cause)(CPUXtensaState *env, uint32_t pc, uint32_t cause) @@ -391,7 +391,7 @@ void HELPER(waiti)(CPUXtensaState *env, uint32_t pc, uint32_t intlevel) (intlevel << PS_INTLEVEL_SHIFT); check_interrupts(env); if (env->pending_irq_level) { - cpu_loop_exit(env); + cpu_loop_exit(CPU(xtensa_env_get_cpu(env))); return; } diff --git a/user-exec.c b/user-exec.c index dbb9c8d0a7..e149c9732f 100644 --- a/user-exec.c +++ b/user-exec.c @@ -40,12 +40,12 @@ static void exception_action(CPUArchState *env1) { -#if defined(TARGET_I386) CPUState *cpu = ENV_GET_CPU(env1); +#if defined(TARGET_I386) raise_exception_err(env1, cpu->exception_index, env1->error_code); #else - cpu_loop_exit(env1); + cpu_loop_exit(cpu); #endif } -- cgit 1.4.1 From 3f38f309b22d9a30b5b427501eb3d522c439482e Mon Sep 17 00:00:00 2001 From: Andreas Färber Date: Sun, 1 Sep 2013 16:51:34 +0200 Subject: translate-all: Change cpu_restore_state() argument to CPUState MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This lets us drop some local variables in tlb_fill() functions. Signed-off-by: Andreas Färber --- hw/i386/kvmvapic.c | 2 +- include/exec/exec-all.h | 2 +- target-alpha/helper.c | 2 +- target-alpha/mem_helper.c | 7 ++----- target-arm/op_helper.c | 2 +- target-cris/op_helper.c | 2 +- target-i386/helper.c | 2 +- target-i386/mem_helper.c | 2 +- target-lm32/op_helper.c | 5 +---- target-m68k/op_helper.c | 5 +---- target-microblaze/op_helper.c | 5 +---- target-mips/op_helper.c | 2 +- target-moxie/helper.c | 6 ++---- target-openrisc/mmu_helper.c | 5 +---- target-ppc/mmu_helper.c | 2 +- target-s390x/mem_helper.c | 5 +---- target-s390x/misc_helper.c | 2 +- target-sh4/op_helper.c | 7 ++----- target-sparc/helper.c | 20 ++++++++++++++------ target-sparc/ldst_helper.c | 8 +++----- target-unicore32/op_helper.c | 5 +---- target-xtensa/op_helper.c | 6 ++++-- translate-all.c | 3 ++- user-exec.c | 2 +- 24 files changed, 46 insertions(+), 63 deletions(-) (limited to 'include/exec/exec-all.h') diff --git a/hw/i386/kvmvapic.c b/hw/i386/kvmvapic.c index 6cf5d41155..39d516a46e 100644 --- a/hw/i386/kvmvapic.c +++ b/hw/i386/kvmvapic.c @@ -406,7 +406,7 @@ static void patch_instruction(VAPICROMState *s, X86CPU *cpu, target_ulong ip) } if (!kvm_enabled()) { - cpu_restore_state(env, cs->mem_io_pc); + cpu_restore_state(cs, cs->mem_io_pc); cpu_get_tb_cpu_state(env, ¤t_pc, ¤t_cs_base, ¤t_flags); } diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index 80277eac32..cf5cd7100f 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -80,7 +80,7 @@ void restore_state_to_opc(CPUArchState *env, struct TranslationBlock *tb, void cpu_gen_init(void); int cpu_gen_code(CPUArchState *env, struct TranslationBlock *tb, int *gen_code_size_ptr); -bool cpu_restore_state(CPUArchState *env, uintptr_t searched_pc); +bool cpu_restore_state(CPUState *cpu, uintptr_t searched_pc); void page_size_init(void); void QEMU_NORETURN cpu_resume_from_signal(CPUArchState *env1, void *puc); diff --git a/target-alpha/helper.c b/target-alpha/helper.c index 45f73e0ea2..305dd67b84 100644 --- a/target-alpha/helper.c +++ b/target-alpha/helper.c @@ -526,7 +526,7 @@ void QEMU_NORETURN dynamic_excp(CPUAlphaState *env, uintptr_t retaddr, cs->exception_index = excp; env->error_code = error; if (retaddr) { - cpu_restore_state(env, retaddr); + cpu_restore_state(cs, retaddr); } cpu_loop_exit(cs); } diff --git a/target-alpha/mem_helper.c b/target-alpha/mem_helper.c index 1957c566b9..5964bdcda8 100644 --- a/target-alpha/mem_helper.c +++ b/target-alpha/mem_helper.c @@ -105,7 +105,7 @@ static void do_unaligned_access(CPUAlphaState *env, target_ulong addr, uint32_t insn; if (retaddr) { - cpu_restore_state(env, retaddr); + cpu_restore_state(cs, retaddr); } pc = env->pc; @@ -159,11 +159,8 @@ void tlb_fill(CPUState *cs, target_ulong addr, int is_write, ret = alpha_cpu_handle_mmu_fault(cs, addr, is_write, mmu_idx); if (unlikely(ret != 0)) { - AlphaCPU *cpu = ALPHA_CPU(cs); - CPUAlphaState *env = &cpu->env; - if (retaddr) { - cpu_restore_state(env, retaddr); + cpu_restore_state(cs, retaddr); } /* Exception index and error code are already set */ cpu_loop_exit(cs); diff --git a/target-arm/op_helper.c b/target-arm/op_helper.c index f8e535e8ce..21ff58e754 100644 --- a/target-arm/op_helper.c +++ b/target-arm/op_helper.c @@ -87,7 +87,7 @@ void tlb_fill(CPUState *cs, target_ulong addr, int is_write, int mmu_idx, if (retaddr) { /* now we have a real cpu fault */ - cpu_restore_state(env, retaddr); + cpu_restore_state(cs, retaddr); } raise_exception(env, cs->exception_index); } diff --git a/target-cris/op_helper.c b/target-cris/op_helper.c index d80b6c966d..d28bd61778 100644 --- a/target-cris/op_helper.c +++ b/target-cris/op_helper.c @@ -67,7 +67,7 @@ void tlb_fill(CPUState *cs, target_ulong addr, int is_write, int mmu_idx, if (unlikely(ret)) { if (retaddr) { /* now we have a real cpu fault */ - if (cpu_restore_state(env, retaddr)) { + if (cpu_restore_state(cs, retaddr)) { /* Evaluate flags after retranslation. */ helper_top_evaluate_flags(env); } diff --git a/target-i386/helper.c b/target-i386/helper.c index 59736d7a4f..cb29aa4b0e 100644 --- a/target-i386/helper.c +++ b/target-i386/helper.c @@ -1263,7 +1263,7 @@ void cpu_report_tpr_access(CPUX86State *env, TPRAccess access) cpu_interrupt(cs, CPU_INTERRUPT_TPR); } else { - cpu_restore_state(env, cs->mem_io_pc); + cpu_restore_state(cs, cs->mem_io_pc); apic_handle_tpr_access_report(cpu->apic_state, env->eip, access); } diff --git a/target-i386/mem_helper.c b/target-i386/mem_helper.c index 2f0691be8f..b3b811bc8c 100644 --- a/target-i386/mem_helper.c +++ b/target-i386/mem_helper.c @@ -145,7 +145,7 @@ void tlb_fill(CPUState *cs, target_ulong addr, int is_write, int mmu_idx, if (retaddr) { /* now we have a real cpu fault */ - cpu_restore_state(env, retaddr); + cpu_restore_state(cs, retaddr); } raise_exception_err(env, cs->exception_index, env->error_code); } diff --git a/target-lm32/op_helper.c b/target-lm32/op_helper.c index f0859aab6d..2f36b7b053 100644 --- a/target-lm32/op_helper.c +++ b/target-lm32/op_helper.c @@ -160,12 +160,9 @@ void tlb_fill(CPUState *cs, target_ulong addr, int is_write, int mmu_idx, ret = lm32_cpu_handle_mmu_fault(cs, addr, is_write, mmu_idx); if (unlikely(ret)) { - LM32CPU *cpu = LM32_CPU(cs); - CPULM32State *env = &cpu->env; - if (retaddr) { /* now we have a real cpu fault */ - cpu_restore_state(env, retaddr); + cpu_restore_state(cs, retaddr); } cpu_loop_exit(cs); } diff --git a/target-m68k/op_helper.c b/target-m68k/op_helper.c index d6268cd6b9..06302b1071 100644 --- a/target-m68k/op_helper.c +++ b/target-m68k/op_helper.c @@ -60,12 +60,9 @@ void tlb_fill(CPUState *cs, target_ulong addr, int is_write, int mmu_idx, ret = m68k_cpu_handle_mmu_fault(cs, addr, is_write, mmu_idx); if (unlikely(ret)) { - M68kCPU *cpu = M68K_CPU(cs); - CPUM68KState *env = &cpu->env; - if (retaddr) { /* now we have a real cpu fault */ - cpu_restore_state(env, retaddr); + cpu_restore_state(cs, retaddr); } cpu_loop_exit(cs); } diff --git a/target-microblaze/op_helper.c b/target-microblaze/op_helper.c index f47613241d..f8fb7f9169 100644 --- a/target-microblaze/op_helper.c +++ b/target-microblaze/op_helper.c @@ -49,12 +49,9 @@ void tlb_fill(CPUState *cs, target_ulong addr, int is_write, int mmu_idx, ret = mb_cpu_handle_mmu_fault(cs, addr, is_write, mmu_idx); if (unlikely(ret)) { - MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs); - CPUMBState *env = &cpu->env; - if (retaddr) { /* now we have a real cpu fault */ - cpu_restore_state(env, retaddr); + cpu_restore_state(cs, retaddr); } cpu_loop_exit(cs); } diff --git a/target-mips/op_helper.c b/target-mips/op_helper.c index c65350187f..de5a22329a 100644 --- a/target-mips/op_helper.c +++ b/target-mips/op_helper.c @@ -48,7 +48,7 @@ static inline void QEMU_NORETURN do_raise_exception_err(CPUMIPSState *env, if (pc) { /* now we have a real cpu fault */ - cpu_restore_state(env, pc); + cpu_restore_state(cs, pc); } cpu_loop_exit(cs); diff --git a/target-moxie/helper.c b/target-moxie/helper.c index 3994c0910d..04b36b78b5 100644 --- a/target-moxie/helper.c +++ b/target-moxie/helper.c @@ -49,14 +49,12 @@ void tlb_fill(CPUState *cs, target_ulong addr, int is_write, int mmu_idx, uintptr_t retaddr) { - MoxieCPU *cpu = MOXIE_CPU(cs); - CPUMoxieState *env = &cpu->env; int ret; ret = moxie_cpu_handle_mmu_fault(cs, addr, is_write, mmu_idx); if (unlikely(ret)) { if (retaddr) { - cpu_restore_state(env, retaddr); + cpu_restore_state(cs, retaddr); } } cpu_loop_exit(cs); @@ -70,7 +68,7 @@ void helper_raise_exception(CPUMoxieState *env, int ex) /* Stash the exception type. */ env->sregs[2] = ex; /* Stash the address where the exception occurred. */ - cpu_restore_state(env, GETPC()); + cpu_restore_state(cs, GETPC()); env->sregs[5] = env->pc; /* Jump the the exception handline routine. */ env->pc = env->sregs[1]; diff --git a/target-openrisc/mmu_helper.c b/target-openrisc/mmu_helper.c index 5f7f6f5ac4..fb457c76af 100644 --- a/target-openrisc/mmu_helper.c +++ b/target-openrisc/mmu_helper.c @@ -44,12 +44,9 @@ void tlb_fill(CPUState *cs, target_ulong addr, int is_write, ret = openrisc_cpu_handle_mmu_fault(cs, addr, is_write, mmu_idx); if (ret) { - OpenRISCCPU *cpu = OPENRISC_CPU(cs); - CPUOpenRISCState *env = &cpu->env; - if (retaddr) { /* now we have a real cpu fault. */ - cpu_restore_state(env, retaddr); + cpu_restore_state(cs, retaddr); } /* Raise Exception. */ cpu_loop_exit(cs); diff --git a/target-ppc/mmu_helper.c b/target-ppc/mmu_helper.c index c0421848b1..2a94f3d67f 100644 --- a/target-ppc/mmu_helper.c +++ b/target-ppc/mmu_helper.c @@ -2909,7 +2909,7 @@ void tlb_fill(CPUState *cs, target_ulong addr, int is_write, int mmu_idx, if (unlikely(ret != 0)) { if (likely(retaddr)) { /* now we have a real cpu fault */ - cpu_restore_state(env, retaddr); + cpu_restore_state(cs, retaddr); } helper_raise_exception_err(env, cs->exception_index, env->error_code); } diff --git a/target-s390x/mem_helper.c b/target-s390x/mem_helper.c index e89fcac4e2..e1c2ac04d1 100644 --- a/target-s390x/mem_helper.c +++ b/target-s390x/mem_helper.c @@ -51,12 +51,9 @@ void tlb_fill(CPUState *cs, target_ulong addr, int is_write, int mmu_idx, ret = s390_cpu_handle_mmu_fault(cs, addr, is_write, mmu_idx); if (unlikely(ret != 0)) { - S390CPU *cpu = S390_CPU(cs); - CPUS390XState *env = &cpu->env; - if (likely(retaddr)) { /* now we have a real cpu fault */ - cpu_restore_state(env, retaddr); + cpu_restore_state(cs, retaddr); } cpu_loop_exit(cs); } diff --git a/target-s390x/misc_helper.c b/target-s390x/misc_helper.c index 2beec61a2b..942b5f7487 100644 --- a/target-s390x/misc_helper.c +++ b/target-s390x/misc_helper.c @@ -54,7 +54,7 @@ void QEMU_NORETURN runtime_exception(CPUS390XState *env, int excp, env->int_pgm_code = excp; /* Use the (ultimate) callers address to find the insn that trapped. */ - cpu_restore_state(env, retaddr); + cpu_restore_state(cs, retaddr); /* Advance past the insn. */ t = cpu_ldub_code(env, env->psw.addr); diff --git a/target-sh4/op_helper.c b/target-sh4/op_helper.c index 271401f699..b3ce7bad53 100644 --- a/target-sh4/op_helper.c +++ b/target-sh4/op_helper.c @@ -46,11 +46,8 @@ void tlb_fill(CPUState *cs, target_ulong addr, int is_write, int mmu_idx, ret = superh_cpu_handle_mmu_fault(cs, addr, is_write, mmu_idx); if (ret) { /* now we have a real cpu fault */ - SuperHCPU *cpu = SUPERH_CPU(cs); - CPUSH4State *env = &cpu->env; - if (retaddr) { - cpu_restore_state(env, retaddr); + cpu_restore_state(cs, retaddr); } cpu_loop_exit(cs); } @@ -75,7 +72,7 @@ static inline void QEMU_NORETURN raise_exception(CPUSH4State *env, int index, cs->exception_index = index; if (retaddr) { - cpu_restore_state(env, retaddr); + cpu_restore_state(cs, retaddr); } cpu_loop_exit(cs); } diff --git a/target-sparc/helper.c b/target-sparc/helper.c index fb5f6ecd38..f3c7fbf993 100644 --- a/target-sparc/helper.c +++ b/target-sparc/helper.c @@ -71,6 +71,7 @@ void helper_tick_set_limit(void *opaque, uint64_t limit) static target_ulong helper_udiv_common(CPUSPARCState *env, target_ulong a, target_ulong b, int cc) { + SPARCCPU *cpu = sparc_env_get_cpu(env); int overflow = 0; uint64_t x0; uint32_t x1; @@ -79,7 +80,7 @@ static target_ulong helper_udiv_common(CPUSPARCState *env, target_ulong a, x1 = (b & 0xffffffff); if (x1 == 0) { - cpu_restore_state(env, GETPC()); + cpu_restore_state(CPU(cpu), GETPC()); helper_raise_exception(env, TT_DIV_ZERO); } @@ -110,6 +111,7 @@ target_ulong helper_udiv_cc(CPUSPARCState *env, target_ulong a, target_ulong b) static target_ulong helper_sdiv_common(CPUSPARCState *env, target_ulong a, target_ulong b, int cc) { + SPARCCPU *cpu = sparc_env_get_cpu(env); int overflow = 0; int64_t x0; int32_t x1; @@ -118,7 +120,7 @@ static target_ulong helper_sdiv_common(CPUSPARCState *env, target_ulong a, x1 = (b & 0xffffffff); if (x1 == 0) { - cpu_restore_state(env, GETPC()); + cpu_restore_state(CPU(cpu), GETPC()); helper_raise_exception(env, TT_DIV_ZERO); } @@ -151,7 +153,9 @@ int64_t helper_sdivx(CPUSPARCState *env, int64_t a, int64_t b) { if (b == 0) { /* Raise divide by zero trap. */ - cpu_restore_state(env, GETPC()); + SPARCCPU *cpu = sparc_env_get_cpu(env); + + cpu_restore_state(CPU(cpu), GETPC()); helper_raise_exception(env, TT_DIV_ZERO); } else if (b == -1) { /* Avoid overflow trap with i386 divide insn. */ @@ -165,7 +169,9 @@ uint64_t helper_udivx(CPUSPARCState *env, uint64_t a, uint64_t b) { if (b == 0) { /* Raise divide by zero trap. */ - cpu_restore_state(env, GETPC()); + SPARCCPU *cpu = sparc_env_get_cpu(env); + + cpu_restore_state(CPU(cpu), GETPC()); helper_raise_exception(env, TT_DIV_ZERO); } return a / b; @@ -175,6 +181,7 @@ uint64_t helper_udivx(CPUSPARCState *env, uint64_t a, uint64_t b) target_ulong helper_taddcctv(CPUSPARCState *env, target_ulong src1, target_ulong src2) { + SPARCCPU *cpu = sparc_env_get_cpu(env); target_ulong dst; /* Tag overflow occurs if either input has bits 0 or 1 set. */ @@ -197,13 +204,14 @@ target_ulong helper_taddcctv(CPUSPARCState *env, target_ulong src1, return dst; tag_overflow: - cpu_restore_state(env, GETPC()); + cpu_restore_state(CPU(cpu), GETPC()); helper_raise_exception(env, TT_TOVF); } target_ulong helper_tsubcctv(CPUSPARCState *env, target_ulong src1, target_ulong src2) { + SPARCCPU *cpu = sparc_env_get_cpu(env); target_ulong dst; /* Tag overflow occurs if either input has bits 0 or 1 set. */ @@ -226,7 +234,7 @@ target_ulong helper_tsubcctv(CPUSPARCState *env, target_ulong src1, return dst; tag_overflow: - cpu_restore_state(env, GETPC()); + cpu_restore_state(CPU(cpu), GETPC()); helper_raise_exception(env, TT_TOVF); } diff --git a/target-sparc/ldst_helper.c b/target-sparc/ldst_helper.c index 8302bb14c2..1f6df49e88 100644 --- a/target-sparc/ldst_helper.c +++ b/target-sparc/ldst_helper.c @@ -2424,12 +2424,13 @@ static void QEMU_NORETURN do_unaligned_access(CPUSPARCState *env, target_ulong addr, int is_write, int is_user, uintptr_t retaddr) { + SPARCCPU *cpu = sparc_env_get_cpu(env); #ifdef DEBUG_UNALIGNED printf("Unaligned access to 0x" TARGET_FMT_lx " from 0x" TARGET_FMT_lx "\n", addr, env->pc); #endif if (retaddr) { - cpu_restore_state(env, retaddr); + cpu_restore_state(CPU(cpu), retaddr); } helper_raise_exception(env, TT_UNALIGNED); } @@ -2445,11 +2446,8 @@ void tlb_fill(CPUState *cs, target_ulong addr, int is_write, int mmu_idx, ret = sparc_cpu_handle_mmu_fault(cs, addr, is_write, mmu_idx); if (ret) { - SPARCCPU *cpu = SPARC_CPU(cs); - CPUSPARCState *env = &cpu->env; - if (retaddr) { - cpu_restore_state(env, retaddr); + cpu_restore_state(cs, retaddr); } cpu_loop_exit(cs); } diff --git a/target-unicore32/op_helper.c b/target-unicore32/op_helper.c index c2bf834c27..4c6950d506 100644 --- a/target-unicore32/op_helper.c +++ b/target-unicore32/op_helper.c @@ -264,12 +264,9 @@ void tlb_fill(CPUState *cs, target_ulong addr, int is_write, ret = uc32_cpu_handle_mmu_fault(cs, addr, is_write, mmu_idx); if (unlikely(ret)) { - UniCore32CPU *cpu = UNICORE32_CPU(cs); - CPUUniCore32State *env = &cpu->env; - if (retaddr) { /* now we have a real cpu fault */ - cpu_restore_state(env, retaddr); + cpu_restore_state(cs, retaddr); } cpu_loop_exit(cs); } diff --git a/target-xtensa/op_helper.c b/target-xtensa/op_helper.c index 42653784cd..8233443eb0 100644 --- a/target-xtensa/op_helper.c +++ b/target-xtensa/op_helper.c @@ -52,9 +52,11 @@ static void do_unaligned_access(CPUXtensaState *env, static void do_unaligned_access(CPUXtensaState *env, target_ulong addr, int is_write, int is_user, uintptr_t retaddr) { + XtensaCPU *cpu = xtensa_env_get_cpu(env); + if (xtensa_option_enabled(env->config, XTENSA_OPTION_UNALIGNED_EXCEPTION) && !xtensa_option_enabled(env->config, XTENSA_OPTION_HW_ALIGNMENT)) { - cpu_restore_state(env, retaddr); + cpu_restore_state(CPU(cpu), retaddr); HELPER(exception_cause_vaddr)(env, env->pc, LOAD_STORE_ALIGNMENT_CAUSE, addr); } @@ -80,7 +82,7 @@ void tlb_fill(CPUState *cs, paddr & TARGET_PAGE_MASK, access, mmu_idx, page_size); } else { - cpu_restore_state(env, retaddr); + cpu_restore_state(cs, retaddr); HELPER(exception_cause_vaddr)(env, env->pc, ret, vaddr); } } diff --git a/translate-all.c b/translate-all.c index c067011684..70d8229451 100644 --- a/translate-all.c +++ b/translate-all.c @@ -253,8 +253,9 @@ static int cpu_restore_state_from_tb(TranslationBlock *tb, CPUArchState *env, return 0; } -bool cpu_restore_state(CPUArchState *env, uintptr_t retaddr) +bool cpu_restore_state(CPUState *cpu, uintptr_t retaddr) { + CPUArchState *env = cpu->env_ptr; TranslationBlock *tb; tb = tb_find_pc(retaddr); diff --git a/user-exec.c b/user-exec.c index e149c9732f..75c6d5486b 100644 --- a/user-exec.c +++ b/user-exec.c @@ -117,7 +117,7 @@ static inline int handle_cpu_signal(uintptr_t pc, unsigned long address, return 1; /* the MMU fault was handled without causing real CPU fault */ } /* now we have a real cpu fault */ - cpu_restore_state(env, pc); + cpu_restore_state(cpu, pc); /* we restore the process signal mask as the sigreturn should do it (XXX: use sigsetjmp) */ -- cgit 1.4.1 From 90b40a696a6bcfac88529930d4d1e1599878dae3 Mon Sep 17 00:00:00 2001 From: Andreas Färber Date: Sun, 1 Sep 2013 17:21:47 +0200 Subject: translate-all: Change cpu_io_recompile() argument to CPUState MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Andreas Färber --- include/exec/exec-all.h | 2 +- include/exec/softmmu_template.h | 4 ++-- translate-all.c | 4 ++-- 3 files changed, 5 insertions(+), 5 deletions(-) (limited to 'include/exec/exec-all.h') diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index cf5cd7100f..727dc3c4a4 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -84,7 +84,7 @@ bool cpu_restore_state(CPUState *cpu, uintptr_t searched_pc); void page_size_init(void); void QEMU_NORETURN cpu_resume_from_signal(CPUArchState *env1, void *puc); -void QEMU_NORETURN cpu_io_recompile(CPUArchState *env, uintptr_t retaddr); +void QEMU_NORETURN cpu_io_recompile(CPUState *cpu, uintptr_t retaddr); TranslationBlock *tb_gen_code(CPUArchState *env, target_ulong pc, target_ulong cs_base, int flags, int cflags); diff --git a/include/exec/softmmu_template.h b/include/exec/softmmu_template.h index 8603933dcb..73ed7cf921 100644 --- a/include/exec/softmmu_template.h +++ b/include/exec/softmmu_template.h @@ -128,7 +128,7 @@ static inline DATA_TYPE glue(io_read, SUFFIX)(CPUArchState *env, physaddr = (physaddr & TARGET_PAGE_MASK) + addr; cpu->mem_io_pc = retaddr; if (mr != &io_mem_rom && mr != &io_mem_notdirty && !cpu_can_do_io(cpu)) { - cpu_io_recompile(env, retaddr); + cpu_io_recompile(cpu, retaddr); } cpu->mem_io_vaddr = addr; @@ -334,7 +334,7 @@ static inline void glue(io_write, SUFFIX)(CPUArchState *env, physaddr = (physaddr & TARGET_PAGE_MASK) + addr; if (mr != &io_mem_rom && mr != &io_mem_notdirty && !cpu_can_do_io(cpu)) { - cpu_io_recompile(env, retaddr); + cpu_io_recompile(cpu, retaddr); } cpu->mem_io_vaddr = addr; diff --git a/translate-all.c b/translate-all.c index 82d5fa40b3..83c7907b8f 100644 --- a/translate-all.c +++ b/translate-all.c @@ -1419,9 +1419,9 @@ CPUInterruptHandler cpu_interrupt_handler = tcg_handle_interrupt; /* in deterministic execution mode, instructions doing device I/Os must be at the end of the TB */ -void cpu_io_recompile(CPUArchState *env, uintptr_t retaddr) +void cpu_io_recompile(CPUState *cpu, uintptr_t retaddr) { - CPUState *cpu = ENV_GET_CPU(env); + CPUArchState *env = cpu->env_ptr; TranslationBlock *tb; uint32_t n, cflags; target_ulong pc, cs_base; -- cgit 1.4.1 From 648f034c6cd81c64d93a1cfd7bb262006f560649 Mon Sep 17 00:00:00 2001 From: Andreas Färber Date: Sun, 1 Sep 2013 17:43:17 +0200 Subject: translate-all: Change tb_gen_code() argument to CPUState MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Andreas Färber --- cpu-exec.c | 4 ++-- exec.c | 2 +- hw/i386/kvmvapic.c | 2 +- include/exec/exec-all.h | 2 +- translate-all.c | 9 +++++---- 5 files changed, 10 insertions(+), 9 deletions(-) (limited to 'include/exec/exec-all.h') diff --git a/cpu-exec.c b/cpu-exec.c index 192620f37b..c689ef9882 100644 --- a/cpu-exec.c +++ b/cpu-exec.c @@ -103,7 +103,7 @@ static void cpu_exec_nocache(CPUArchState *env, int max_cycles, if (max_cycles > CF_COUNT_MASK) max_cycles = CF_COUNT_MASK; - tb = tb_gen_code(env, orig_tb->pc, orig_tb->cs_base, orig_tb->flags, + tb = tb_gen_code(cpu, orig_tb->pc, orig_tb->cs_base, orig_tb->flags, max_cycles); cpu->current_tb = tb; /* execute the generated code */ @@ -156,7 +156,7 @@ static TranslationBlock *tb_find_slow(CPUArchState *env, } not_found: /* if no translated code available, then translate it now */ - tb = tb_gen_code(env, pc, cs_base, flags, 0); + tb = tb_gen_code(cpu, pc, cs_base, flags, 0); found: /* Move the last found TB to the head of the list */ diff --git a/exec.c b/exec.c index 7f945818f9..6f8b2ca7b8 100644 --- a/exec.c +++ b/exec.c @@ -1611,7 +1611,7 @@ static void check_watchpoint(int offset, int len_mask, int flags) cpu_loop_exit(cpu); } else { cpu_get_tb_cpu_state(env, &pc, &cs_base, &cpu_flags); - tb_gen_code(env, pc, cs_base, cpu_flags, 1); + tb_gen_code(cpu, pc, cs_base, cpu_flags, 1); cpu_resume_from_signal(env, NULL); } } diff --git a/hw/i386/kvmvapic.c b/hw/i386/kvmvapic.c index 39d516a46e..2a9d87a5d8 100644 --- a/hw/i386/kvmvapic.c +++ b/hw/i386/kvmvapic.c @@ -448,7 +448,7 @@ static void patch_instruction(VAPICROMState *s, X86CPU *cpu, target_ulong ip) if (!kvm_enabled()) { cs->current_tb = NULL; - tb_gen_code(env, current_pc, current_cs_base, current_flags, 1); + tb_gen_code(cs, current_pc, current_cs_base, current_flags, 1); cpu_resume_from_signal(env, NULL); } } diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index 727dc3c4a4..a3e7faa416 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -85,7 +85,7 @@ void page_size_init(void); void QEMU_NORETURN cpu_resume_from_signal(CPUArchState *env1, void *puc); void QEMU_NORETURN cpu_io_recompile(CPUState *cpu, uintptr_t retaddr); -TranslationBlock *tb_gen_code(CPUArchState *env, +TranslationBlock *tb_gen_code(CPUState *cpu, target_ulong pc, target_ulong cs_base, int flags, int cflags); void cpu_exec_init(CPUArchState *env); diff --git a/translate-all.c b/translate-all.c index 83c7907b8f..a7130a5a43 100644 --- a/translate-all.c +++ b/translate-all.c @@ -938,10 +938,11 @@ static void build_page_bitmap(PageDesc *p) } } -TranslationBlock *tb_gen_code(CPUArchState *env, +TranslationBlock *tb_gen_code(CPUState *cpu, target_ulong pc, target_ulong cs_base, int flags, int cflags) { + CPUArchState *env = cpu->env_ptr; TranslationBlock *tb; uint8_t *tc_ptr; tb_page_addr_t phys_pc, phys_page2; @@ -1111,7 +1112,7 @@ void tb_invalidate_phys_page_range(tb_page_addr_t start, tb_page_addr_t end, modifying the memory. It will ensure that it cannot modify itself */ cpu->current_tb = NULL; - tb_gen_code(env, current_pc, current_cs_base, current_flags, 1); + tb_gen_code(cpu, current_pc, current_cs_base, current_flags, 1); cpu_resume_from_signal(env, NULL); } #endif @@ -1208,7 +1209,7 @@ static void tb_invalidate_phys_page(tb_page_addr_t addr, modifying the memory. It will ensure that it cannot modify itself */ cpu->current_tb = NULL; - tb_gen_code(env, current_pc, current_cs_base, current_flags, 1); + tb_gen_code(cpu, current_pc, current_cs_base, current_flags, 1); if (locked) { mmap_unlock(); } @@ -1469,7 +1470,7 @@ void cpu_io_recompile(CPUState *cpu, uintptr_t retaddr) tb_phys_invalidate(tb, -1); /* FIXME: In theory this could raise an exception. In practice we have already translated the block once so it's probably ok. */ - tb_gen_code(env, pc, cs_base, flags, cflags); + tb_gen_code(cpu, pc, cs_base, flags, cflags); /* TODO: If env->pc != tb->pc (i.e. the faulting instruction was not the first in the TB) then we end up generating a whole new TB and repeating the fault, which is horribly inefficient. -- cgit 1.4.1 From 0ea8cb8895a9f9adea89fb202984dcd9e890e504 Mon Sep 17 00:00:00 2001 From: Andreas Färber Date: Tue, 3 Sep 2013 02:12:23 +0200 Subject: cpu-exec: Change cpu_resume_from_signal() argument to CPUState MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Andreas Färber --- cpu-exec.c | 4 +--- exec.c | 2 +- hw/i386/kvmvapic.c | 2 +- include/exec/exec-all.h | 2 +- target-i386/helper.c | 2 +- target-lm32/helper.c | 2 +- target-xtensa/helper.c | 2 +- translate-all.c | 6 +++--- user-exec.c | 3 +-- 9 files changed, 11 insertions(+), 14 deletions(-) (limited to 'include/exec/exec-all.h') diff --git a/cpu-exec.c b/cpu-exec.c index c689ef9882..0914d3c85c 100644 --- a/cpu-exec.c +++ b/cpu-exec.c @@ -33,10 +33,8 @@ void cpu_loop_exit(CPUState *cpu) restored in a state compatible with the CPU emulator */ #if defined(CONFIG_SOFTMMU) -void cpu_resume_from_signal(CPUArchState *env, void *puc) +void cpu_resume_from_signal(CPUState *cpu, void *puc) { - CPUState *cpu = ENV_GET_CPU(env); - /* XXX: restore cpu registers saved in host registers */ cpu->exception_index = -1; diff --git a/exec.c b/exec.c index 03ae5fe661..7b377cdb70 100644 --- a/exec.c +++ b/exec.c @@ -1608,7 +1608,7 @@ static void check_watchpoint(int offset, int len_mask, int flags) } else { cpu_get_tb_cpu_state(env, &pc, &cs_base, &cpu_flags); tb_gen_code(cpu, pc, cs_base, cpu_flags, 1); - cpu_resume_from_signal(env, NULL); + cpu_resume_from_signal(cpu, NULL); } } } else { diff --git a/hw/i386/kvmvapic.c b/hw/i386/kvmvapic.c index 2a9d87a5d8..a1c3d1cb85 100644 --- a/hw/i386/kvmvapic.c +++ b/hw/i386/kvmvapic.c @@ -449,7 +449,7 @@ static void patch_instruction(VAPICROMState *s, X86CPU *cpu, target_ulong ip) if (!kvm_enabled()) { cs->current_tb = NULL; tb_gen_code(cs, current_pc, current_cs_base, current_flags, 1); - cpu_resume_from_signal(env, NULL); + cpu_resume_from_signal(cs, NULL); } } diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index a3e7faa416..01b8eba9bc 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -83,7 +83,7 @@ int cpu_gen_code(CPUArchState *env, struct TranslationBlock *tb, bool cpu_restore_state(CPUState *cpu, uintptr_t searched_pc); void page_size_init(void); -void QEMU_NORETURN cpu_resume_from_signal(CPUArchState *env1, void *puc); +void QEMU_NORETURN cpu_resume_from_signal(CPUState *cpu, void *puc); void QEMU_NORETURN cpu_io_recompile(CPUState *cpu, uintptr_t retaddr); TranslationBlock *tb_gen_code(CPUState *cpu, target_ulong pc, target_ulong cs_base, int flags, diff --git a/target-i386/helper.c b/target-i386/helper.c index ad61062de3..8c70d62af5 100644 --- a/target-i386/helper.c +++ b/target-i386/helper.c @@ -1102,7 +1102,7 @@ void breakpoint_handler(CPUX86State *env) if (check_hw_breakpoints(env, false)) { raise_exception(env, EXCP01_DB); } else { - cpu_resume_from_signal(env, NULL); + cpu_resume_from_signal(cs, NULL); } } } else { diff --git a/target-lm32/helper.c b/target-lm32/helper.c index 8be5bed2b4..7de783b91d 100644 --- a/target-lm32/helper.c +++ b/target-lm32/helper.c @@ -135,7 +135,7 @@ void lm32_debug_excp_handler(CPULM32State *env) if (check_watchpoints(env)) { raise_exception(env, EXCP_WATCHPOINT); } else { - cpu_resume_from_signal(env, NULL); + cpu_resume_from_signal(cs, NULL); } } } else { diff --git a/target-xtensa/helper.c b/target-xtensa/helper.c index 8a9cb0a825..94dcd9442e 100644 --- a/target-xtensa/helper.c +++ b/target-xtensa/helper.c @@ -92,7 +92,7 @@ void xtensa_breakpoint_handler(CPUXtensaState *env) if (cause) { debug_exception_env(env, cause); } - cpu_resume_from_signal(env, NULL); + cpu_resume_from_signal(cs, NULL); } } } diff --git a/translate-all.c b/translate-all.c index df85f9f8c5..0aa4f76432 100644 --- a/translate-all.c +++ b/translate-all.c @@ -1113,7 +1113,7 @@ void tb_invalidate_phys_page_range(tb_page_addr_t start, tb_page_addr_t end, itself */ cpu->current_tb = NULL; tb_gen_code(cpu, current_pc, current_cs_base, current_flags, 1); - cpu_resume_from_signal(env, NULL); + cpu_resume_from_signal(cpu, NULL); } #endif } @@ -1213,7 +1213,7 @@ static void tb_invalidate_phys_page(tb_page_addr_t addr, if (locked) { mmap_unlock(); } - cpu_resume_from_signal(env, puc); + cpu_resume_from_signal(cpu, puc); } #endif } @@ -1476,7 +1476,7 @@ void cpu_io_recompile(CPUState *cpu, uintptr_t retaddr) repeating the fault, which is horribly inefficient. Better would be to execute just this insn uncached, or generate a second new TB. */ - cpu_resume_from_signal(env, NULL); + cpu_resume_from_signal(cpu, NULL); } void tb_flush_jmp_cache(CPUState *cpu, target_ulong addr) diff --git a/user-exec.c b/user-exec.c index 75c6d5486b..3b795c1550 100644 --- a/user-exec.c +++ b/user-exec.c @@ -52,9 +52,8 @@ static void exception_action(CPUArchState *env1) /* exit the current TB from a signal handler. The host registers are restored in a state compatible with the CPU emulator */ -void cpu_resume_from_signal(CPUArchState *env1, void *puc) +void cpu_resume_from_signal(CPUState *cpu, void *puc) { - CPUState *cpu = ENV_GET_CPU(env1); #ifdef __linux__ struct ucontext *uc = puc; #elif defined(__OpenBSD__) -- cgit 1.4.1 From 31b030d4abc5bea89c2b33b39d3b302836f6b6ee Mon Sep 17 00:00:00 2001 From: Andreas Färber Date: Wed, 4 Sep 2013 01:29:02 +0200 Subject: cputlb: Change tlb_flush_page() argument to CPUState MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Andreas Färber --- cputlb.c | 4 +-- exec.c | 7 ++---- include/exec/exec-all.h | 4 +-- target-alpha/sys_helper.c | 2 +- target-arm/helper.c | 14 ++++++++--- target-cris/mmu.c | 3 ++- target-cris/op_helper.c | 12 ++++++--- target-i386/misc_helper.c | 4 ++- target-i386/svm_helper.c | 3 ++- target-microblaze/mmu.c | 3 ++- target-mips/helper.c | 8 ++++-- target-openrisc/sys_helper.c | 4 +-- target-ppc/mmu_helper.c | 58 +++++++++++++++++++++++++------------------- target-s390x/mem_helper.c | 6 ++--- target-s390x/misc_helper.c | 6 +++-- target-sh4/helper.c | 19 +++++++++------ target-sparc/ldst_helper.c | 9 ++++--- target-xtensa/op_helper.c | 10 +++++--- 18 files changed, 106 insertions(+), 70 deletions(-) (limited to 'include/exec/exec-all.h') diff --git a/cputlb.c b/cputlb.c index 22810536f5..9a12248004 100644 --- a/cputlb.c +++ b/cputlb.c @@ -77,9 +77,9 @@ static inline void tlb_flush_entry(CPUTLBEntry *tlb_entry, target_ulong addr) } } -void tlb_flush_page(CPUArchState *env, target_ulong addr) +void tlb_flush_page(CPUState *cpu, target_ulong addr) { - CPUState *cpu = ENV_GET_CPU(env); + CPUArchState *env = cpu->env_ptr; int i; int mmu_idx; diff --git a/exec.c b/exec.c index 5224b31e9f..c03193266a 100644 --- a/exec.c +++ b/exec.c @@ -543,7 +543,6 @@ int cpu_watchpoint_insert(CPUState *cpu, vaddr addr, vaddr len, int cpu_watchpoint_insert(CPUState *cpu, vaddr addr, vaddr len, int flags, CPUWatchpoint **watchpoint) { - CPUArchState *env = cpu->env_ptr; vaddr len_mask = ~(len - 1); CPUWatchpoint *wp; @@ -567,7 +566,7 @@ int cpu_watchpoint_insert(CPUState *cpu, vaddr addr, vaddr len, QTAILQ_INSERT_TAIL(&cpu->watchpoints, wp, entry); } - tlb_flush_page(env, addr); + tlb_flush_page(cpu, addr); if (watchpoint) *watchpoint = wp; @@ -594,11 +593,9 @@ int cpu_watchpoint_remove(CPUState *cpu, vaddr addr, vaddr len, /* Remove a specific watchpoint by reference. */ void cpu_watchpoint_remove_by_ref(CPUState *cpu, CPUWatchpoint *watchpoint) { - CPUArchState *env = cpu->env_ptr; - QTAILQ_REMOVE(&cpu->watchpoints, watchpoint, entry); - tlb_flush_page(env, watchpoint->vaddr); + tlb_flush_page(cpu, watchpoint->vaddr); g_free(watchpoint); } diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index 01b8eba9bc..33633a2fae 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -98,14 +98,14 @@ void tb_invalidate_phys_range(tb_page_addr_t start, tb_page_addr_t end, #if !defined(CONFIG_USER_ONLY) void tcg_cpu_address_space_init(CPUState *cpu, AddressSpace *as); /* cputlb.c */ -void tlb_flush_page(CPUArchState *env, target_ulong addr); +void tlb_flush_page(CPUState *cpu, target_ulong addr); void tlb_flush(CPUArchState *env, int flush_global); void tlb_set_page(CPUArchState *env, target_ulong vaddr, hwaddr paddr, int prot, int mmu_idx, target_ulong size); void tb_invalidate_phys_addr(AddressSpace *as, hwaddr addr); #else -static inline void tlb_flush_page(CPUArchState *env, target_ulong addr) +static inline void tlb_flush_page(CPUState *cpu, target_ulong addr) { } diff --git a/target-alpha/sys_helper.c b/target-alpha/sys_helper.c index 035810c27c..5f7d7dde0e 100644 --- a/target-alpha/sys_helper.c +++ b/target-alpha/sys_helper.c @@ -69,7 +69,7 @@ void helper_tbia(CPUAlphaState *env) void helper_tbis(CPUAlphaState *env, uint64_t p) { - tlb_flush_page(env, p); + tlb_flush_page(CPU(alpha_env_get_cpu(env)), p); } void helper_tb_flush(CPUAlphaState *env) diff --git a/target-arm/helper.c b/target-arm/helper.c index 0a9c6fc5e2..1fda6be295 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -342,7 +342,9 @@ static void tlbimva_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { /* Invalidate single TLB entry by MVA and ASID (TLBIMVA) */ - tlb_flush_page(env, value & TARGET_PAGE_MASK); + ARMCPU *cpu = arm_env_get_cpu(env); + + tlb_flush_page(CPU(cpu), value & TARGET_PAGE_MASK); } static void tlbiasid_write(CPUARMState *env, const ARMCPRegInfo *ri, @@ -356,7 +358,9 @@ static void tlbimvaa_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { /* Invalidate single entry by MVA, all ASIDs (TLBIMVAA) */ - tlb_flush_page(env, value & TARGET_PAGE_MASK); + ARMCPU *cpu = arm_env_get_cpu(env); + + tlb_flush_page(CPU(cpu), value & TARGET_PAGE_MASK); } static const ARMCPRegInfo cp_reginfo[] = { @@ -1686,16 +1690,18 @@ static void tlbi_aa64_va_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { /* Invalidate by VA (AArch64 version) */ + ARMCPU *cpu = arm_env_get_cpu(env); uint64_t pageaddr = value << 12; - tlb_flush_page(env, pageaddr); + tlb_flush_page(CPU(cpu), pageaddr); } static void tlbi_aa64_vaa_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { /* Invalidate by VA, all ASIDs (AArch64 version) */ + ARMCPU *cpu = arm_env_get_cpu(env); uint64_t pageaddr = value << 12; - tlb_flush_page(env, pageaddr); + tlb_flush_page(CPU(cpu), pageaddr); } static void tlbi_aa64_asid_write(CPUARMState *env, const ARMCPRegInfo *ri, diff --git a/target-cris/mmu.c b/target-cris/mmu.c index 512e28b481..1c95a415f2 100644 --- a/target-cris/mmu.c +++ b/target-cris/mmu.c @@ -290,6 +290,7 @@ static int cris_mmu_translate_page(struct cris_mmu_result *res, void cris_mmu_flush_pid(CPUCRISState *env, uint32_t pid) { + CRISCPU *cpu = cris_env_get_cpu(env); target_ulong vaddr; unsigned int idx; uint32_t lo, hi; @@ -315,7 +316,7 @@ void cris_mmu_flush_pid(CPUCRISState *env, uint32_t pid) vaddr = tlb_vpn << TARGET_PAGE_BITS; D_LOG("flush pid=%x vaddr=%x\n", pid, vaddr); - tlb_flush_page(env, vaddr); + tlb_flush_page(CPU(cpu), vaddr); } } } diff --git a/target-cris/op_helper.c b/target-cris/op_helper.c index d28bd61778..bd9a583f9a 100644 --- a/target-cris/op_helper.c +++ b/target-cris/op_helper.c @@ -98,8 +98,11 @@ void helper_tlb_flush_pid(CPUCRISState *env, uint32_t pid) void helper_spc_write(CPUCRISState *env, uint32_t new_spc) { #if !defined(CONFIG_USER_ONLY) - tlb_flush_page(env, env->pregs[PR_SPC]); - tlb_flush_page(env, new_spc); + CRISCPU *cpu = cris_env_get_cpu(env); + CPUState *cs = CPU(cpu); + + tlb_flush_page(cs, env->pregs[PR_SPC]); + tlb_flush_page(cs, new_spc); #endif } @@ -114,6 +117,9 @@ void helper_dump(uint32_t a0, uint32_t a1, uint32_t a2) void helper_movl_sreg_reg(CPUCRISState *env, uint32_t sreg, uint32_t reg) { +#if !defined(CONFIG_USER_ONLY) + CRISCPU *cpu = cris_env_get_cpu(env); +#endif uint32_t srs; srs = env->pregs[PR_SRS]; srs &= 3; @@ -155,7 +161,7 @@ void helper_movl_sreg_reg(CPUCRISState *env, uint32_t sreg, uint32_t reg) D_LOG("tlb flush vaddr=%x v=%d pc=%x\n", vaddr, tlb_v, env->pc); if (tlb_v) { - tlb_flush_page(env, vaddr); + tlb_flush_page(CPU(cpu), vaddr); } } } diff --git a/target-i386/misc_helper.c b/target-i386/misc_helper.c index 8c6b9bfce2..1e2da1ed68 100644 --- a/target-i386/misc_helper.c +++ b/target-i386/misc_helper.c @@ -221,8 +221,10 @@ void helper_lmsw(CPUX86State *env, target_ulong t0) void helper_invlpg(CPUX86State *env, target_ulong addr) { + X86CPU *cpu = x86_env_get_cpu(env); + cpu_svm_check_intercept_param(env, SVM_EXIT_INVLPG, 0); - tlb_flush_page(env, addr); + tlb_flush_page(CPU(cpu), addr); } void helper_rdtsc(CPUX86State *env) diff --git a/target-i386/svm_helper.c b/target-i386/svm_helper.c index de2c2eebe0..6e7c3b7224 100644 --- a/target-i386/svm_helper.c +++ b/target-i386/svm_helper.c @@ -469,6 +469,7 @@ void helper_skinit(CPUX86State *env) void helper_invlpga(CPUX86State *env, int aflag) { + X86CPU *cpu = x86_env_get_cpu(env); target_ulong addr; cpu_svm_check_intercept_param(env, SVM_EXIT_INVLPGA, 0); @@ -481,7 +482,7 @@ void helper_invlpga(CPUX86State *env, int aflag) /* XXX: could use the ASID to see if it is needed to do the flush */ - tlb_flush_page(env, addr); + tlb_flush_page(CPU(cpu), addr); } void helper_svm_check_intercept_param(CPUX86State *env, uint32_t type, diff --git a/target-microblaze/mmu.c b/target-microblaze/mmu.c index 73bf8059be..7ee1be046c 100644 --- a/target-microblaze/mmu.c +++ b/target-microblaze/mmu.c @@ -34,6 +34,7 @@ static unsigned int tlb_decode_size(unsigned int f) static void mmu_flush_idx(CPUMBState *env, unsigned int idx) { + CPUState *cs = CPU(mb_env_get_cpu(env)); struct microblaze_mmu *mmu = &env->mmu; unsigned int tlb_size; uint32_t tlb_tag, end, t; @@ -47,7 +48,7 @@ static void mmu_flush_idx(CPUMBState *env, unsigned int idx) end = tlb_tag + tlb_size; while (tlb_tag < end) { - tlb_flush_page(env, tlb_tag); + tlb_flush_page(cs, tlb_tag); tlb_tag += TARGET_PAGE_SIZE; } } diff --git a/target-mips/helper.c b/target-mips/helper.c index 698c3d1adb..f3879eddda 100644 --- a/target-mips/helper.c +++ b/target-mips/helper.c @@ -653,6 +653,8 @@ void mips_cpu_do_interrupt(CPUState *cs) #if !defined(CONFIG_USER_ONLY) void r4k_invalidate_tlb (CPUMIPSState *env, int idx, int use_extra) { + MIPSCPU *cpu = mips_env_get_cpu(env); + CPUState *cs; r4k_tlb_t *tlb; target_ulong addr; target_ulong end; @@ -678,6 +680,7 @@ void r4k_invalidate_tlb (CPUMIPSState *env, int idx, int use_extra) /* 1k pages are not supported. */ mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1); if (tlb->V0) { + cs = CPU(cpu); addr = tlb->VPN & ~mask; #if defined(TARGET_MIPS64) if (addr >= (0xFFFFFFFF80000000ULL & env->SEGMask)) { @@ -686,11 +689,12 @@ void r4k_invalidate_tlb (CPUMIPSState *env, int idx, int use_extra) #endif end = addr | (mask >> 1); while (addr < end) { - tlb_flush_page (env, addr); + tlb_flush_page(cs, addr); addr += TARGET_PAGE_SIZE; } } if (tlb->V1) { + cs = CPU(cpu); addr = (tlb->VPN & ~mask) | ((mask >> 1) + 1); #if defined(TARGET_MIPS64) if (addr >= (0xFFFFFFFF80000000ULL & env->SEGMask)) { @@ -699,7 +703,7 @@ void r4k_invalidate_tlb (CPUMIPSState *env, int idx, int use_extra) #endif end = addr | mask; while (addr - 1 < end) { - tlb_flush_page (env, addr); + tlb_flush_page(cs, addr); addr += TARGET_PAGE_SIZE; } } diff --git a/target-openrisc/sys_helper.c b/target-openrisc/sys_helper.c index be06c4565b..f1ff3adca9 100644 --- a/target-openrisc/sys_helper.c +++ b/target-openrisc/sys_helper.c @@ -84,7 +84,7 @@ void HELPER(mtspr)(CPUOpenRISCState *env, case TO_SPR(1, 512) ... TO_SPR(1, 512+DTLB_SIZE-1): /* DTLBW0MR 0-127 */ idx = spr - TO_SPR(1, 512); if (!(rb & 1)) { - tlb_flush_page(env, env->tlb->dtlb[0][idx].mr & TARGET_PAGE_MASK); + tlb_flush_page(cs, env->tlb->dtlb[0][idx].mr & TARGET_PAGE_MASK); } env->tlb->dtlb[0][idx].mr = rb; break; @@ -103,7 +103,7 @@ void HELPER(mtspr)(CPUOpenRISCState *env, case TO_SPR(2, 512) ... TO_SPR(2, 512+ITLB_SIZE-1): /* ITLBW0MR 0-127 */ idx = spr - TO_SPR(2, 512); if (!(rb & 1)) { - tlb_flush_page(env, env->tlb->itlb[0][idx].mr & TARGET_PAGE_MASK); + tlb_flush_page(cs, env->tlb->itlb[0][idx].mr & TARGET_PAGE_MASK); } env->tlb->itlb[0][idx].mr = rb; break; diff --git a/target-ppc/mmu_helper.c b/target-ppc/mmu_helper.c index 845a7252b3..8dc262cfd1 100644 --- a/target-ppc/mmu_helper.c +++ b/target-ppc/mmu_helper.c @@ -252,6 +252,7 @@ static inline void ppc6xx_tlb_invalidate_virt2(CPUPPCState *env, int is_code, int match_epn) { #if !defined(FLUSH_ALL_TLBS) + CPUState *cs = CPU(ppc_env_get_cpu(env)); ppc6xx_tlb_t *tlb; int way, nr; @@ -263,7 +264,7 @@ static inline void ppc6xx_tlb_invalidate_virt2(CPUPPCState *env, LOG_SWTLB("TLB invalidate %d/%d " TARGET_FMT_lx "\n", nr, env->nb_tlb, eaddr); pte_invalidate(&tlb->pte0); - tlb_flush_page(env, tlb->EPN); + tlb_flush_page(cs, tlb->EPN); } } #else @@ -657,6 +658,7 @@ static inline void ppc4xx_tlb_invalidate_virt(CPUPPCState *env, target_ulong eaddr, uint32_t pid) { #if !defined(FLUSH_ALL_TLBS) + CPUState *cs = CPU(ppc_env_get_cpu(env)); ppcemb_tlb_t *tlb; hwaddr raddr; target_ulong page, end; @@ -667,7 +669,7 @@ static inline void ppc4xx_tlb_invalidate_virt(CPUPPCState *env, if (ppcemb_tlb_check(env, tlb, &raddr, eaddr, pid, 0, i) == 0) { end = tlb->EPN + tlb->size; for (page = tlb->EPN; page < end; page += TARGET_PAGE_SIZE) { - tlb_flush_page(env, page); + tlb_flush_page(cs, page); } tlb->prot &= ~PAGE_VALID; break; @@ -1727,6 +1729,7 @@ static int cpu_ppc_handle_mmu_fault(CPUPPCState *env, target_ulong address, static inline void do_invalidate_BAT(CPUPPCState *env, target_ulong BATu, target_ulong mask) { + CPUState *cs = CPU(ppc_env_get_cpu(env)); target_ulong base, end, page; base = BATu & ~0x0001FFFF; @@ -1734,7 +1737,7 @@ static inline void do_invalidate_BAT(CPUPPCState *env, target_ulong BATu, LOG_BATS("Flush BAT from " TARGET_FMT_lx " to " TARGET_FMT_lx " (" TARGET_FMT_lx ")\n", base, end, mask); for (page = base; page != end; page += TARGET_PAGE_SIZE) { - tlb_flush_page(env, page); + tlb_flush_page(cs, page); } LOG_BATS("Flush done\n"); } @@ -1941,6 +1944,7 @@ void ppc_tlb_invalidate_one(CPUPPCState *env, target_ulong addr) { #if !defined(FLUSH_ALL_TLBS) PowerPCCPU *cpu = ppc_env_get_cpu(env); + CPUState *cs; addr &= TARGET_PAGE_MASK; switch (env->mmu_model) { @@ -1974,25 +1978,26 @@ void ppc_tlb_invalidate_one(CPUPPCState *env, target_ulong addr) case POWERPC_MMU_601: /* tlbie invalidate TLBs for all segments */ addr &= ~((target_ulong)-1ULL << 28); + cs = CPU(cpu); /* XXX: this case should be optimized, * giving a mask to tlb_flush_page */ - tlb_flush_page(env, addr | (0x0 << 28)); - tlb_flush_page(env, addr | (0x1 << 28)); - tlb_flush_page(env, addr | (0x2 << 28)); - tlb_flush_page(env, addr | (0x3 << 28)); - tlb_flush_page(env, addr | (0x4 << 28)); - tlb_flush_page(env, addr | (0x5 << 28)); - tlb_flush_page(env, addr | (0x6 << 28)); - tlb_flush_page(env, addr | (0x7 << 28)); - tlb_flush_page(env, addr | (0x8 << 28)); - tlb_flush_page(env, addr | (0x9 << 28)); - tlb_flush_page(env, addr | (0xA << 28)); - tlb_flush_page(env, addr | (0xB << 28)); - tlb_flush_page(env, addr | (0xC << 28)); - tlb_flush_page(env, addr | (0xD << 28)); - tlb_flush_page(env, addr | (0xE << 28)); - tlb_flush_page(env, addr | (0xF << 28)); + tlb_flush_page(cs, addr | (0x0 << 28)); + tlb_flush_page(cs, addr | (0x1 << 28)); + tlb_flush_page(cs, addr | (0x2 << 28)); + tlb_flush_page(cs, addr | (0x3 << 28)); + tlb_flush_page(cs, addr | (0x4 << 28)); + tlb_flush_page(cs, addr | (0x5 << 28)); + tlb_flush_page(cs, addr | (0x6 << 28)); + tlb_flush_page(cs, addr | (0x7 << 28)); + tlb_flush_page(cs, addr | (0x8 << 28)); + tlb_flush_page(cs, addr | (0x9 << 28)); + tlb_flush_page(cs, addr | (0xA << 28)); + tlb_flush_page(cs, addr | (0xB << 28)); + tlb_flush_page(cs, addr | (0xC << 28)); + tlb_flush_page(cs, addr | (0xD << 28)); + tlb_flush_page(cs, addr | (0xE << 28)); + tlb_flush_page(cs, addr | (0xF << 28)); break; #if defined(TARGET_PPC64) case POWERPC_MMU_64B: @@ -2325,6 +2330,7 @@ void helper_4xx_tlbwe_hi(CPUPPCState *env, target_ulong entry, target_ulong val) { PowerPCCPU *cpu = ppc_env_get_cpu(env); + CPUState *cs = CPU(cpu); ppcemb_tlb_t *tlb; target_ulong page, end; @@ -2338,7 +2344,7 @@ void helper_4xx_tlbwe_hi(CPUPPCState *env, target_ulong entry, LOG_SWTLB("%s: invalidate old TLB %d start " TARGET_FMT_lx " end " TARGET_FMT_lx "\n", __func__, (int)entry, tlb->EPN, end); for (page = tlb->EPN; page < end; page += TARGET_PAGE_SIZE) { - tlb_flush_page(env, page); + tlb_flush_page(cs, page); } } tlb->size = booke_tlb_to_page_size((val >> PPC4XX_TLBHI_SIZE_SHIFT) @@ -2348,7 +2354,7 @@ void helper_4xx_tlbwe_hi(CPUPPCState *env, target_ulong entry, * of the ppc or ppc64 one */ if ((val & PPC4XX_TLBHI_V) && tlb->size < TARGET_PAGE_SIZE) { - cpu_abort(CPU(cpu), "TLB size " TARGET_FMT_lu " < %u " + cpu_abort(cs, "TLB size " TARGET_FMT_lu " < %u " "are not supported (%d)\n", tlb->size, TARGET_PAGE_SIZE, (int)((val >> 7) & 0x7)); } @@ -2357,7 +2363,7 @@ void helper_4xx_tlbwe_hi(CPUPPCState *env, target_ulong entry, tlb->prot |= PAGE_VALID; if (val & PPC4XX_TLBHI_E) { /* XXX: TO BE FIXED */ - cpu_abort(CPU(cpu), + cpu_abort(cs, "Little-endian TLB entries are not supported by now\n"); } } else { @@ -2377,7 +2383,7 @@ void helper_4xx_tlbwe_hi(CPUPPCState *env, target_ulong entry, LOG_SWTLB("%s: invalidate TLB %d start " TARGET_FMT_lx " end " TARGET_FMT_lx "\n", __func__, (int)entry, tlb->EPN, end); for (page = tlb->EPN; page < end; page += TARGET_PAGE_SIZE) { - tlb_flush_page(env, page); + tlb_flush_page(cs, page); } } } @@ -2666,7 +2672,7 @@ void helper_booke206_tlbwe(CPUPPCState *env) } if (booke206_tlb_to_page_size(env, tlb) == TARGET_PAGE_SIZE) { - tlb_flush_page(env, tlb->mas2 & MAS2_EPN_MASK); + tlb_flush_page(CPU(cpu), tlb->mas2 & MAS2_EPN_MASK); } else { tlb_flush(env, 1); } @@ -2775,6 +2781,8 @@ static inline void booke206_invalidate_ea_tlb(CPUPPCState *env, int tlbn, void helper_booke206_tlbivax(CPUPPCState *env, target_ulong address) { + PowerPCCPU *cpu = ppc_env_get_cpu(env); + if (address & 0x4) { /* flush all entries */ if (address & 0x8) { @@ -2794,7 +2802,7 @@ void helper_booke206_tlbivax(CPUPPCState *env, target_ulong address) } else { /* flush TLB0 entries */ booke206_invalidate_ea_tlb(env, 0, address); - tlb_flush_page(env, address & MAS2_EPN_MASK); + tlb_flush_page(CPU(cpu), address & MAS2_EPN_MASK); } } diff --git a/target-s390x/mem_helper.c b/target-s390x/mem_helper.c index 21632848ac..607501890c 100644 --- a/target-s390x/mem_helper.c +++ b/target-s390x/mem_helper.c @@ -1027,13 +1027,13 @@ void HELPER(ipte)(CPUS390XState *env, uint64_t pte_addr, uint64_t vaddr) /* XXX we exploit the fact that Linux passes the exact virtual address here - it's not obliged to! */ - tlb_flush_page(env, page); + tlb_flush_page(cs, page); /* XXX 31-bit hack */ if (page & 0x80000000) { - tlb_flush_page(env, page & ~0x80000000); + tlb_flush_page(cs, page & ~0x80000000); } else { - tlb_flush_page(env, page | 0x80000000); + tlb_flush_page(cs, page | 0x80000000); } } diff --git a/target-s390x/misc_helper.c b/target-s390x/misc_helper.c index 942b5f7487..294b3ed4fb 100644 --- a/target-s390x/misc_helper.c +++ b/target-s390x/misc_helper.c @@ -237,11 +237,13 @@ uint64_t HELPER(diag)(CPUS390XState *env, uint32_t num, uint64_t mem, /* Set Prefix */ void HELPER(spx)(CPUS390XState *env, uint64_t a1) { + CPUState *cs = CPU(s390_env_get_cpu(env)); uint32_t prefix = a1 & 0x7fffe000; + env->psa = prefix; qemu_log("prefix: %#x\n", prefix); - tlb_flush_page(env, 0); - tlb_flush_page(env, TARGET_PAGE_SIZE); + tlb_flush_page(cs, 0); + tlb_flush_page(cs, TARGET_PAGE_SIZE); } static inline uint64_t clock_value(CPUS390XState *env) diff --git a/target-sh4/helper.c b/target-sh4/helper.c index ba0f269f52..9eb258517f 100644 --- a/target-sh4/helper.c +++ b/target-sh4/helper.c @@ -304,7 +304,7 @@ static int copy_utlb_entry_itlb(CPUSH4State *env, int utlb) itlb = itlb_replacement(env); ientry = &env->itlb[itlb]; if (ientry->v) { - tlb_flush_page(env, ientry->vpn << 10); + tlb_flush_page(CPU(sh_env_get_cpu(env)), ientry->vpn << 10); } *ientry = env->utlb[utlb]; update_itlb_use(env, itlb); @@ -535,7 +535,7 @@ void cpu_load_tlb(CPUSH4State * env) if (entry->v) { /* Overwriting valid entry in utlb. */ target_ulong address = entry->vpn << 10; - tlb_flush_page(env, address); + tlb_flush_page(CPU(cpu), address); } /* Take values into cpu status from registers. */ @@ -611,7 +611,7 @@ void cpu_sh4_write_mmaped_itlb_addr(CPUSH4State *s, hwaddr addr, if (entry->v) { /* Overwriting valid entry in itlb. */ target_ulong address = entry->vpn << 10; - tlb_flush_page(s, address); + tlb_flush_page(CPU(sh_env_get_cpu(s)), address); } entry->asid = asid; entry->vpn = vpn; @@ -653,7 +653,7 @@ void cpu_sh4_write_mmaped_itlb_data(CPUSH4State *s, hwaddr addr, if (entry->v) { /* Overwriting valid entry in utlb. */ target_ulong address = entry->vpn << 10; - tlb_flush_page(s, address); + tlb_flush_page(CPU(sh_env_get_cpu(s)), address); } entry->ppn = (mem_value & 0x1ffffc00) >> 10; entry->v = (mem_value & 0x00000100) >> 8; @@ -737,16 +737,19 @@ void cpu_sh4_write_mmaped_utlb_addr(CPUSH4State *s, hwaddr addr, } } - if (needs_tlb_flush) - tlb_flush_page(s, vpn << 10); + if (needs_tlb_flush) { + tlb_flush_page(CPU(sh_env_get_cpu(s)), vpn << 10); + } } else { int index = (addr & 0x00003f00) >> 8; tlb_t * entry = &s->utlb[index]; if (entry->v) { + CPUState *cs = CPU(sh_env_get_cpu(s)); + /* Overwriting valid entry in utlb. */ target_ulong address = entry->vpn << 10; - tlb_flush_page(s, address); + tlb_flush_page(cs, address); } entry->asid = asid; entry->vpn = vpn; @@ -797,7 +800,7 @@ void cpu_sh4_write_mmaped_utlb_data(CPUSH4State *s, hwaddr addr, if (entry->v) { /* Overwriting valid entry in utlb. */ target_ulong address = entry->vpn << 10; - tlb_flush_page(s, address); + tlb_flush_page(CPU(sh_env_get_cpu(s)), address); } entry->ppn = (mem_value & 0x1ffffc00) >> 10; entry->v = (mem_value & 0x00000100) >> 8; diff --git a/target-sparc/ldst_helper.c b/target-sparc/ldst_helper.c index 1f6df49e88..36fe2de441 100644 --- a/target-sparc/ldst_helper.c +++ b/target-sparc/ldst_helper.c @@ -141,6 +141,7 @@ static void replace_tlb_entry(SparcTLBEntry *tlb, /* flush page range if translation is valid */ if (TTE_IS_VALID(tlb->tte)) { + CPUState *cs = CPU(sparc_env_get_cpu(env1)); mask = 0xffffffffffffe000ULL; mask <<= 3 * ((tlb->tte >> 61) & 3); @@ -149,7 +150,7 @@ static void replace_tlb_entry(SparcTLBEntry *tlb, va = tlb->tag & mask; for (offset = 0; offset < size; offset += TARGET_PAGE_SIZE) { - tlb_flush_page(env1, va + offset); + tlb_flush_page(cs, va + offset); } } @@ -716,7 +717,9 @@ uint64_t helper_ld_asi(CPUSPARCState *env, target_ulong addr, int asi, int size, void helper_st_asi(CPUSPARCState *env, target_ulong addr, uint64_t val, int asi, int size) { - CPUState *cs = CPU(sparc_env_get_cpu(env)); + SPARCCPU *cpu = sparc_env_get_cpu(env); + CPUState *cs = CPU(cpu); + helper_check_align(env, addr, size - 1); switch (asi) { case 2: /* SuperSparc MXCC registers and Leon3 cache control */ @@ -862,7 +865,7 @@ void helper_st_asi(CPUSPARCState *env, target_ulong addr, uint64_t val, int asi, DPRINTF_MMU("mmu flush level %d\n", mmulev); switch (mmulev) { case 0: /* flush page */ - tlb_flush_page(env, addr & 0xfffff000); + tlb_flush_page(CPU(cpu), addr & 0xfffff000); break; case 1: /* flush segment (256k) */ case 2: /* flush region (16M) */ diff --git a/target-xtensa/op_helper.c b/target-xtensa/op_helper.c index 07b00a4335..cae9cf4ad6 100644 --- a/target-xtensa/op_helper.c +++ b/target-xtensa/op_helper.c @@ -687,7 +687,7 @@ void HELPER(itlb)(CPUXtensaState *env, uint32_t v, uint32_t dtlb) uint32_t wi; xtensa_tlb_entry *entry = get_tlb_entry(env, v, dtlb, &wi); if (entry->variable && entry->asid) { - tlb_flush_page(env, entry->vaddr); + tlb_flush_page(CPU(xtensa_env_get_cpu(env)), entry->vaddr); entry->asid = 0; } } @@ -732,21 +732,23 @@ void xtensa_tlb_set_entry_mmu(const CPUXtensaState *env, void xtensa_tlb_set_entry(CPUXtensaState *env, bool dtlb, unsigned wi, unsigned ei, uint32_t vpn, uint32_t pte) { + XtensaCPU *cpu = xtensa_env_get_cpu(env); + CPUState *cs = CPU(cpu); xtensa_tlb_entry *entry = xtensa_tlb_get_entry(env, dtlb, wi, ei); if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) { if (entry->variable) { if (entry->asid) { - tlb_flush_page(env, entry->vaddr); + tlb_flush_page(cs, entry->vaddr); } xtensa_tlb_set_entry_mmu(env, entry, dtlb, wi, ei, vpn, pte); - tlb_flush_page(env, entry->vaddr); + tlb_flush_page(cs, entry->vaddr); } else { qemu_log("%s %d, %d, %d trying to set immutable entry\n", __func__, dtlb, wi, ei); } } else { - tlb_flush_page(env, entry->vaddr); + tlb_flush_page(cs, entry->vaddr); if (xtensa_option_enabled(env->config, XTENSA_OPTION_REGION_TRANSLATION)) { entry->paddr = pte & REGION_PAGE_MASK; -- cgit 1.4.1 From 00c8cb0a36f51a6866a83c08962d12a0eb21864b Mon Sep 17 00:00:00 2001 From: Andreas Färber Date: Wed, 4 Sep 2013 02:19:44 +0200 Subject: cputlb: Change tlb_flush() argument to CPUState MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Andreas Färber --- cputlb.c | 6 +++--- exec.c | 4 +--- hw/sh4/sh7750.c | 2 +- include/exec/exec-all.h | 4 ++-- target-alpha/cpu.c | 2 +- target-alpha/sys_helper.c | 2 +- target-arm/cpu.c | 2 +- target-arm/helper.c | 39 ++++++++++++++++++++++++--------- target-cris/cpu.c | 2 +- target-i386/cpu.c | 2 +- target-i386/helper.c | 17 ++++++++++----- target-i386/machine.c | 2 +- target-i386/svm_helper.c | 2 +- target-lm32/cpu.c | 2 +- target-m68k/cpu.c | 2 +- target-microblaze/cpu.c | 2 +- target-microblaze/mmu.c | 3 ++- target-mips/cpu.c | 2 +- target-mips/machine.c | 3 ++- target-mips/op_helper.c | 4 +++- target-moxie/cpu.c | 2 +- target-openrisc/cpu.c | 2 +- target-openrisc/interrupt.c | 2 +- target-openrisc/interrupt_helper.c | 2 +- target-openrisc/sys_helper.c | 2 +- target-ppc/excp_helper.c | 4 ++-- target-ppc/helper_regs.h | 2 +- target-ppc/misc_helper.c | 4 +++- target-ppc/mmu-hash64.c | 6 ++++-- target-ppc/mmu_helper.c | 44 ++++++++++++++++++++++++-------------- target-ppc/translate_init.c | 2 +- target-s390x/cpu.c | 4 ++-- target-s390x/mem_helper.c | 13 +++++++---- target-sh4/cpu.c | 2 +- target-sh4/helper.c | 2 +- target-sparc/cpu.c | 2 +- target-sparc/ldst_helper.c | 18 +++++++++------- target-sparc/machine.c | 3 ++- target-unicore32/cpu.c | 2 +- target-unicore32/helper.c | 4 +++- target-xtensa/op_helper.c | 4 +++- 41 files changed, 143 insertions(+), 87 deletions(-) (limited to 'include/exec/exec-all.h') diff --git a/cputlb.c b/cputlb.c index 9a12248004..b280e81c6f 100644 --- a/cputlb.c +++ b/cputlb.c @@ -46,9 +46,9 @@ int tlb_flush_count; * entries from the TLB at any time, so flushing more entries than * required is only an efficiency issue, not a correctness issue. */ -void tlb_flush(CPUArchState *env, int flush_global) +void tlb_flush(CPUState *cpu, int flush_global) { - CPUState *cpu = ENV_GET_CPU(env); + CPUArchState *env = cpu->env_ptr; #if defined(DEBUG_TLB) printf("tlb_flush:\n"); @@ -93,7 +93,7 @@ void tlb_flush_page(CPUState *cpu, target_ulong addr) TARGET_FMT_lx "/" TARGET_FMT_lx ")\n", env->tlb_flush_addr, env->tlb_flush_mask); #endif - tlb_flush(env, 1); + tlb_flush(cpu, 1); return; } /* must reset current TB so that interrupts cannot modify the diff --git a/exec.c b/exec.c index c03193266a..6a0bc94a0a 100644 --- a/exec.c +++ b/exec.c @@ -1834,14 +1834,12 @@ static void tcg_commit(MemoryListener *listener) reset the modified entries */ /* XXX: slow ! */ CPU_FOREACH(cpu) { - CPUArchState *env = cpu->env_ptr; - /* FIXME: Disentangle the cpu.h circular files deps so we can directly get the right CPU from listener. */ if (cpu->tcg_as_listener != listener) { continue; } - tlb_flush(env, 1); + tlb_flush(cpu, 1); } } diff --git a/hw/sh4/sh7750.c b/hw/sh4/sh7750.c index 1439ba44e5..4a39357529 100644 --- a/hw/sh4/sh7750.c +++ b/hw/sh4/sh7750.c @@ -416,7 +416,7 @@ static void sh7750_mem_writel(void *opaque, hwaddr addr, case SH7750_PTEH_A7: /* If asid changes, clear all registered tlb entries. */ if ((s->cpu->env.pteh & 0xff) != (mem_value & 0xff)) { - tlb_flush(&s->cpu->env, 1); + tlb_flush(CPU(s->cpu), 1); } s->cpu->env.pteh = mem_value; return; diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index 33633a2fae..4cc11bb652 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -99,7 +99,7 @@ void tb_invalidate_phys_range(tb_page_addr_t start, tb_page_addr_t end, void tcg_cpu_address_space_init(CPUState *cpu, AddressSpace *as); /* cputlb.c */ void tlb_flush_page(CPUState *cpu, target_ulong addr); -void tlb_flush(CPUArchState *env, int flush_global); +void tlb_flush(CPUState *cpu, int flush_global); void tlb_set_page(CPUArchState *env, target_ulong vaddr, hwaddr paddr, int prot, int mmu_idx, target_ulong size); @@ -109,7 +109,7 @@ static inline void tlb_flush_page(CPUState *cpu, target_ulong addr) { } -static inline void tlb_flush(CPUArchState *env, int flush_global) +static inline void tlb_flush(CPUState *cpu, int flush_global) { } #endif diff --git a/target-alpha/cpu.c b/target-alpha/cpu.c index 4d8263f37d..7ec46b90fc 100644 --- a/target-alpha/cpu.c +++ b/target-alpha/cpu.c @@ -258,7 +258,7 @@ static void alpha_cpu_initfn(Object *obj) cs->env_ptr = env; cpu_exec_init(env); - tlb_flush(env, 1); + tlb_flush(cs, 1); alpha_translate_init(); diff --git a/target-alpha/sys_helper.c b/target-alpha/sys_helper.c index 5f7d7dde0e..187ccf7297 100644 --- a/target-alpha/sys_helper.c +++ b/target-alpha/sys_helper.c @@ -64,7 +64,7 @@ void helper_call_pal(CPUAlphaState *env, uint64_t pc, uint64_t entry_ofs) void helper_tbia(CPUAlphaState *env) { - tlb_flush(env, 1); + tlb_flush(CPU(alpha_env_get_cpu(env)), 1); } void helper_tbis(CPUAlphaState *env, uint64_t p) diff --git a/target-arm/cpu.c b/target-arm/cpu.c index ecd0b7ecde..c32d8c4855 100644 --- a/target-arm/cpu.c +++ b/target-arm/cpu.c @@ -149,7 +149,7 @@ static void arm_cpu_reset(CPUState *s) &env->vfp.fp_status); set_float_detect_tininess(float_tininess_before_rounding, &env->vfp.standard_fp_status); - tlb_flush(env, 1); + tlb_flush(s, 1); /* Reset is a state change for some CPUARMState fields which we * bake assumptions about into translated code, so we need to * tb_flush(). diff --git a/target-arm/helper.c b/target-arm/helper.c index 1fda6be295..a9db2796c5 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -303,17 +303,21 @@ void init_cpreg_list(ARMCPU *cpu) static void dacr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { + ARMCPU *cpu = arm_env_get_cpu(env); + env->cp15.c3 = value; - tlb_flush(env, 1); /* Flush TLB as domain not tracked in TLB */ + tlb_flush(CPU(cpu), 1); /* Flush TLB as domain not tracked in TLB */ } static void fcse_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { + ARMCPU *cpu = arm_env_get_cpu(env); + if (env->cp15.c13_fcse != value) { /* Unlike real hardware the qemu TLB uses virtual addresses, * not modified virtual addresses, so this causes a TLB flush. */ - tlb_flush(env, 1); + tlb_flush(CPU(cpu), 1); env->cp15.c13_fcse = value; } } @@ -321,12 +325,14 @@ static void fcse_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) static void contextidr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { + ARMCPU *cpu = arm_env_get_cpu(env); + if (env->cp15.c13_context != value && !arm_feature(env, ARM_FEATURE_MPU)) { /* For VMSA (when not using the LPAE long descriptor page table * format) this register includes the ASID, so do a TLB flush. * For PMSA it is purely a process ID and no action is needed. */ - tlb_flush(env, 1); + tlb_flush(CPU(cpu), 1); } env->cp15.c13_context = value; } @@ -335,7 +341,9 @@ static void tlbiall_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { /* Invalidate all (TLBIALL) */ - tlb_flush(env, 1); + ARMCPU *cpu = arm_env_get_cpu(env); + + tlb_flush(CPU(cpu), 1); } static void tlbimva_write(CPUARMState *env, const ARMCPRegInfo *ri, @@ -351,7 +359,9 @@ static void tlbiasid_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { /* Invalidate by ASID (TLBIASID) */ - tlb_flush(env, value == 0); + ARMCPU *cpu = arm_env_get_cpu(env); + + tlb_flush(CPU(cpu), value == 0); } static void tlbimvaa_write(CPUARMState *env, const ARMCPRegInfo *ri, @@ -1352,11 +1362,13 @@ static void vmsa_ttbcr_raw_write(CPUARMState *env, const ARMCPRegInfo *ri, static void vmsa_ttbcr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { + ARMCPU *cpu = arm_env_get_cpu(env); + if (arm_feature(env, ARM_FEATURE_LPAE)) { /* With LPAE the TTBCR could result in a change of ASID * via the TTBCR.A1 bit, so do a TLB flush. */ - tlb_flush(env, 1); + tlb_flush(CPU(cpu), 1); } vmsa_ttbcr_raw_write(env, ri, value); } @@ -1371,8 +1383,10 @@ static void vmsa_ttbcr_reset(CPUARMState *env, const ARMCPRegInfo *ri) static void vmsa_tcr_el1_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { + ARMCPU *cpu = arm_env_get_cpu(env); + /* For AArch64 the A1 bit could result in a change of ASID, so TLB flush. */ - tlb_flush(env, 1); + tlb_flush(CPU(cpu), 1); env->cp15.c2_control = value; } @@ -1383,7 +1397,9 @@ static void vmsa_ttbr_write(CPUARMState *env, const ARMCPRegInfo *ri, * must flush the TLB. */ if (cpreg_field_is_64bit(ri)) { - tlb_flush(env, 1); + ARMCPU *cpu = arm_env_get_cpu(env); + + tlb_flush(CPU(cpu), 1); } raw_write(env, ri, value); } @@ -1708,8 +1724,9 @@ static void tlbi_aa64_asid_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { /* Invalidate by ASID (AArch64 version) */ + ARMCPU *cpu = arm_env_get_cpu(env); int asid = extract64(value, 48, 16); - tlb_flush(env, asid == 0); + tlb_flush(CPU(cpu), asid == 0); } static const ARMCPRegInfo v8_cp_reginfo[] = { @@ -1835,10 +1852,12 @@ static const ARMCPRegInfo v8_cp_reginfo[] = { static void sctlr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { + ARMCPU *cpu = arm_env_get_cpu(env); + env->cp15.c1_sys = value; /* ??? Lots of these bits are not implemented. */ /* This may enable/disable the MMU, so do a TLB flush. */ - tlb_flush(env, 1); + tlb_flush(CPU(cpu), 1); } static CPAccessResult ctr_el0_access(CPUARMState *env, const ARMCPRegInfo *ri) diff --git a/target-cris/cpu.c b/target-cris/cpu.c index 95b6a8889b..20d8809699 100644 --- a/target-cris/cpu.c +++ b/target-cris/cpu.c @@ -51,7 +51,7 @@ static void cris_cpu_reset(CPUState *s) vr = env->pregs[PR_VR]; memset(env, 0, offsetof(CPUCRISState, load_info)); env->pregs[PR_VR] = vr; - tlb_flush(env, 1); + tlb_flush(s, 1); #if defined(CONFIG_USER_ONLY) /* start in user mode with interrupts enabled. */ diff --git a/target-i386/cpu.c b/target-i386/cpu.c index 659ec9a11b..e7e62c5897 100644 --- a/target-i386/cpu.c +++ b/target-i386/cpu.c @@ -2412,7 +2412,7 @@ static void x86_cpu_reset(CPUState *s) memset(env, 0, offsetof(CPUX86State, pat)); - tlb_flush(env, 1); + tlb_flush(s, 1); env->old_exception = -1; diff --git a/target-i386/helper.c b/target-i386/helper.c index 8c70d62af5..54899a0542 100644 --- a/target-i386/helper.c +++ b/target-i386/helper.c @@ -385,22 +385,25 @@ void x86_cpu_set_a20(X86CPU *cpu, int a20_state) a20_state = (a20_state != 0); if (a20_state != ((env->a20_mask >> 20) & 1)) { + CPUState *cs = CPU(cpu); + #if defined(DEBUG_MMU) printf("A20 update: a20=%d\n", a20_state); #endif /* if the cpu is currently executing code, we must unlink it and all the potentially executing TB */ - cpu_interrupt(CPU(cpu), CPU_INTERRUPT_EXITTB); + cpu_interrupt(cs, CPU_INTERRUPT_EXITTB); /* when a20 is changed, all the MMU mappings are invalid, so we must flush everything */ - tlb_flush(env, 1); + tlb_flush(cs, 1); env->a20_mask = ~(1 << 20) | (a20_state << 20); } } void cpu_x86_update_cr0(CPUX86State *env, uint32_t new_cr0) { + X86CPU *cpu = x86_env_get_cpu(env); int pe_state; #if defined(DEBUG_MMU) @@ -408,7 +411,7 @@ void cpu_x86_update_cr0(CPUX86State *env, uint32_t new_cr0) #endif if ((new_cr0 & (CR0_PG_MASK | CR0_WP_MASK | CR0_PE_MASK)) != (env->cr[0] & (CR0_PG_MASK | CR0_WP_MASK | CR0_PE_MASK))) { - tlb_flush(env, 1); + tlb_flush(CPU(cpu), 1); } #ifdef TARGET_X86_64 @@ -444,24 +447,28 @@ void cpu_x86_update_cr0(CPUX86State *env, uint32_t new_cr0) the PDPT */ void cpu_x86_update_cr3(CPUX86State *env, target_ulong new_cr3) { + X86CPU *cpu = x86_env_get_cpu(env); + env->cr[3] = new_cr3; if (env->cr[0] & CR0_PG_MASK) { #if defined(DEBUG_MMU) printf("CR3 update: CR3=" TARGET_FMT_lx "\n", new_cr3); #endif - tlb_flush(env, 0); + tlb_flush(CPU(cpu), 0); } } void cpu_x86_update_cr4(CPUX86State *env, uint32_t new_cr4) { + X86CPU *cpu = x86_env_get_cpu(env); + #if defined(DEBUG_MMU) printf("CR4 update: CR4=%08x\n", (uint32_t)env->cr[4]); #endif if ((new_cr4 ^ env->cr[4]) & (CR4_PGE_MASK | CR4_PAE_MASK | CR4_PSE_MASK | CR4_SMEP_MASK | CR4_SMAP_MASK)) { - tlb_flush(env, 1); + tlb_flush(CPU(cpu), 1); } /* SSE handling */ if (!(env->features[FEAT_1_EDX] & CPUID_SSE)) { diff --git a/target-i386/machine.c b/target-i386/machine.c index ed159a8c06..24bc373b9c 100644 --- a/target-i386/machine.c +++ b/target-i386/machine.c @@ -325,7 +325,7 @@ static int cpu_post_load(void *opaque, int version_id) for (i = 0; i < DR7_MAX_BP; i++) { hw_breakpoint_insert(env, i); } - tlb_flush(env, 1); + tlb_flush(cs, 1); return 0; } diff --git a/target-i386/svm_helper.c b/target-i386/svm_helper.c index 6e7c3b7224..aa17ecdece 100644 --- a/target-i386/svm_helper.c +++ b/target-i386/svm_helper.c @@ -294,7 +294,7 @@ void helper_vmrun(CPUX86State *env, int aflag, int next_eip_addend) break; case TLB_CONTROL_FLUSH_ALL_ASID: /* FIXME: this is not 100% correct but should work for now */ - tlb_flush(env, 1); + tlb_flush(cs, 1); break; } diff --git a/target-lm32/cpu.c b/target-lm32/cpu.c index d0c66bc0f5..c5c20d74c4 100644 --- a/target-lm32/cpu.c +++ b/target-lm32/cpu.c @@ -128,7 +128,7 @@ static void lm32_cpu_reset(CPUState *s) memset(env, 0, offsetof(CPULM32State, eba)); lm32_cpu_init_cfg_reg(cpu); - tlb_flush(env, 1); + tlb_flush(s, 1); } static void lm32_cpu_realizefn(DeviceState *dev, Error **errp) diff --git a/target-m68k/cpu.c b/target-m68k/cpu.c index a88da20b46..c9cff19efc 100644 --- a/target-m68k/cpu.c +++ b/target-m68k/cpu.c @@ -58,7 +58,7 @@ static void m68k_cpu_reset(CPUState *s) env->cc_op = CC_OP_FLAGS; /* TODO: We should set PC from the interrupt vector. */ env->pc = 0; - tlb_flush(env, 1); + tlb_flush(s, 1); } /* CPU models */ diff --git a/target-microblaze/cpu.c b/target-microblaze/cpu.c index 3177fe6d12..8e0481186a 100644 --- a/target-microblaze/cpu.c +++ b/target-microblaze/cpu.c @@ -65,7 +65,7 @@ static void mb_cpu_reset(CPUState *s) memset(env, 0, sizeof(CPUMBState)); env->res_addr = RES_ADDR_NONE; - tlb_flush(env, 1); + tlb_flush(s, 1); /* Disable stack protector. */ env->shr = ~0; diff --git a/target-microblaze/mmu.c b/target-microblaze/mmu.c index 7ee1be046c..728da133da 100644 --- a/target-microblaze/mmu.c +++ b/target-microblaze/mmu.c @@ -219,6 +219,7 @@ uint32_t mmu_read(CPUMBState *env, uint32_t rn) void mmu_write(CPUMBState *env, uint32_t rn, uint32_t v) { + MicroBlazeCPU *cpu = mb_env_get_cpu(env); unsigned int i; D(qemu_log("%s rn=%d=%x old=%x\n", __func__, rn, v, env->mmu.regs[rn])); @@ -252,7 +253,7 @@ void mmu_write(CPUMBState *env, uint32_t rn, uint32_t v) /* Changes to the zone protection reg flush the QEMU TLB. Fortunately, these are very uncommon. */ if (v != env->mmu.regs[rn]) { - tlb_flush(env, 1); + tlb_flush(CPU(cpu), 1); } env->mmu.regs[rn] = v; break; diff --git a/target-mips/cpu.c b/target-mips/cpu.c index cf4d856d6b..ae37ae26c0 100644 --- a/target-mips/cpu.c +++ b/target-mips/cpu.c @@ -84,7 +84,7 @@ static void mips_cpu_reset(CPUState *s) mcc->parent_reset(s); memset(env, 0, offsetof(CPUMIPSState, mvp)); - tlb_flush(env, 1); + tlb_flush(s, 1); cpu_state_reset(env); } diff --git a/target-mips/machine.c b/target-mips/machine.c index 23504ba9ae..0a07db8540 100644 --- a/target-mips/machine.c +++ b/target-mips/machine.c @@ -191,6 +191,7 @@ static void load_fpu(QEMUFile *f, CPUMIPSFPUContext *fpu) int cpu_load(QEMUFile *f, void *opaque, int version_id) { CPUMIPSState *env = opaque; + MIPSCPU *cpu = mips_env_get_cpu(env); int i; if (version_id != 3) @@ -303,6 +304,6 @@ int cpu_load(QEMUFile *f, void *opaque, int version_id) load_fpu(f, &env->fpus[i]); /* XXX: ensure compatibility for halted bit ? */ - tlb_flush(env, 1); + tlb_flush(CPU(cpu), 1); return 0; } diff --git a/target-mips/op_helper.c b/target-mips/op_helper.c index 1a785c23d9..e56f038d71 100644 --- a/target-mips/op_helper.c +++ b/target-mips/op_helper.c @@ -1787,8 +1787,10 @@ target_ulong helper_yield(CPUMIPSState *env, target_ulong arg) /* TLB management */ static void cpu_mips_tlb_flush (CPUMIPSState *env, int flush_global) { + MIPSCPU *cpu = mips_env_get_cpu(env); + /* Flush qemu's TLB and discard all shadowed entries. */ - tlb_flush (env, flush_global); + tlb_flush(CPU(cpu), flush_global); env->tlb->tlb_in_use = env->tlb->nb_tlb; } diff --git a/target-moxie/cpu.c b/target-moxie/cpu.c index 14d1a24438..47b617f5cd 100644 --- a/target-moxie/cpu.c +++ b/target-moxie/cpu.c @@ -45,7 +45,7 @@ static void moxie_cpu_reset(CPUState *s) memset(env, 0, sizeof(CPUMoxieState)); env->pc = 0x1000; - tlb_flush(env, 1); + tlb_flush(s, 1); } static void moxie_cpu_realizefn(DeviceState *dev, Error **errp) diff --git a/target-openrisc/cpu.c b/target-openrisc/cpu.c index a00369bef5..08e724c126 100644 --- a/target-openrisc/cpu.c +++ b/target-openrisc/cpu.c @@ -47,7 +47,7 @@ static void openrisc_cpu_reset(CPUState *s) memset(&cpu->env, 0, offsetof(CPUOpenRISCState, irq)); #endif - tlb_flush(&cpu->env, 1); + tlb_flush(s, 1); /*tb_flush(&cpu->env); FIXME: Do we need it? */ cpu->env.pc = 0x100; diff --git a/target-openrisc/interrupt.c b/target-openrisc/interrupt.c index e312300853..3de567eee8 100644 --- a/target-openrisc/interrupt.c +++ b/target-openrisc/interrupt.c @@ -43,7 +43,7 @@ void openrisc_cpu_do_interrupt(CPUState *cs) /* For machine-state changed between user-mode and supervisor mode, we need flush TLB when we enter&exit EXCP. */ - tlb_flush(env, 1); + tlb_flush(cs, 1); env->esr = env->sr; env->sr &= ~SR_DME; diff --git a/target-openrisc/interrupt_helper.c b/target-openrisc/interrupt_helper.c index 844648f780..819405701d 100644 --- a/target-openrisc/interrupt_helper.c +++ b/target-openrisc/interrupt_helper.c @@ -51,7 +51,7 @@ void HELPER(rfe)(CPUOpenRISCState *env) } if (need_flush_tlb) { - tlb_flush(&cpu->env, 1); + tlb_flush(cs, 1); } #endif cs->interrupt_request |= CPU_INTERRUPT_EXITTB; diff --git a/target-openrisc/sys_helper.c b/target-openrisc/sys_helper.c index f1ff3adca9..fedcbed4f7 100644 --- a/target-openrisc/sys_helper.c +++ b/target-openrisc/sys_helper.c @@ -45,7 +45,7 @@ void HELPER(mtspr)(CPUOpenRISCState *env, case TO_SPR(0, 17): /* SR */ if ((env->sr & (SR_IME | SR_DME | SR_SM)) ^ (rb & (SR_IME | SR_DME | SR_SM))) { - tlb_flush(env, 1); + tlb_flush(cs, 1); } env->sr = rb; env->sr |= SR_FO; /* FO is const equal to 1 */ diff --git a/target-ppc/excp_helper.c b/target-ppc/excp_helper.c index a2226d1923..19bc6b66ba 100644 --- a/target-ppc/excp_helper.c +++ b/target-ppc/excp_helper.c @@ -616,7 +616,7 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int excp_model, int excp) } /* If we disactivated any translation, flush TLBs */ if (msr & ((1 << MSR_IR) | (1 << MSR_DR))) { - tlb_flush(env, 1); + tlb_flush(cs, 1); } #ifdef TARGET_PPC64 @@ -671,7 +671,7 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int excp_model, int excp) /* XXX: The BookE changes address space when switching modes, we should probably implement that as different MMU indexes, but for the moment we do it the slow way and flush all. */ - tlb_flush(env, 1); + tlb_flush(cs, 1); } } diff --git a/target-ppc/helper_regs.h b/target-ppc/helper_regs.h index c02e8da4e4..f7ec9c2b81 100644 --- a/target-ppc/helper_regs.h +++ b/target-ppc/helper_regs.h @@ -83,7 +83,7 @@ static inline int hreg_store_msr(CPUPPCState *env, target_ulong value, if (((value >> MSR_IR) & 1) != msr_ir || ((value >> MSR_DR) & 1) != msr_dr) { /* Flush all tlb when changing translation mode */ - tlb_flush(env, 1); + tlb_flush(cs, 1); excp = POWERPC_EXCP_NONE; cs->interrupt_request |= CPU_INTERRUPT_EXITTB; } diff --git a/target-ppc/misc_helper.c b/target-ppc/misc_helper.c index dc2ebfc452..2eb2fa6e20 100644 --- a/target-ppc/misc_helper.c +++ b/target-ppc/misc_helper.c @@ -62,10 +62,12 @@ void helper_store_hid0_601(CPUPPCState *env, target_ulong val) void helper_store_403_pbr(CPUPPCState *env, uint32_t num, target_ulong value) { + PowerPCCPU *cpu = ppc_env_get_cpu(env); + if (likely(env->pb[num] != value)) { env->pb[num] = value; /* Should be optimized */ - tlb_flush(env, 1); + tlb_flush(CPU(cpu), 1); } } diff --git a/target-ppc/mmu-hash64.c b/target-ppc/mmu-hash64.c index 98cfb35f69..3f405b3cc9 100644 --- a/target-ppc/mmu-hash64.c +++ b/target-ppc/mmu-hash64.c @@ -99,6 +99,7 @@ void dump_slb(FILE *f, fprintf_function cpu_fprintf, CPUPPCState *env) void helper_slbia(CPUPPCState *env) { + PowerPCCPU *cpu = ppc_env_get_cpu(env); int n, do_invalidate; do_invalidate = 0; @@ -116,12 +117,13 @@ void helper_slbia(CPUPPCState *env) } } if (do_invalidate) { - tlb_flush(env, 1); + tlb_flush(CPU(cpu), 1); } } void helper_slbie(CPUPPCState *env, target_ulong addr) { + PowerPCCPU *cpu = ppc_env_get_cpu(env); ppc_slb_t *slb; slb = slb_lookup(env, addr); @@ -136,7 +138,7 @@ void helper_slbie(CPUPPCState *env, target_ulong addr) * and we still don't have a tlb_flush_mask(env, n, mask) * in QEMU, we just invalidate all TLBs */ - tlb_flush(env, 1); + tlb_flush(CPU(cpu), 1); } } diff --git a/target-ppc/mmu_helper.c b/target-ppc/mmu_helper.c index 8dc262cfd1..653e50230e 100644 --- a/target-ppc/mmu_helper.c +++ b/target-ppc/mmu_helper.c @@ -231,6 +231,7 @@ static inline int ppc6xx_tlb_getnum(CPUPPCState *env, target_ulong eaddr, static inline void ppc6xx_tlb_invalidate_all(CPUPPCState *env) { + PowerPCCPU *cpu = ppc_env_get_cpu(env); ppc6xx_tlb_t *tlb; int nr, max; @@ -244,7 +245,7 @@ static inline void ppc6xx_tlb_invalidate_all(CPUPPCState *env) tlb = &env->tlb.tlb6[nr]; pte_invalidate(&tlb->pte0); } - tlb_flush(env, 1); + tlb_flush(CPU(cpu), 1); } static inline void ppc6xx_tlb_invalidate_virt2(CPUPPCState *env, @@ -644,6 +645,7 @@ static int ppcemb_tlb_search(CPUPPCState *env, target_ulong address, /* Helpers specific to PowerPC 40x implementations */ static inline void ppc4xx_tlb_invalidate_all(CPUPPCState *env) { + PowerPCCPU *cpu = ppc_env_get_cpu(env); ppcemb_tlb_t *tlb; int i; @@ -651,7 +653,7 @@ static inline void ppc4xx_tlb_invalidate_all(CPUPPCState *env) tlb = &env->tlb.tlbe[i]; tlb->prot &= ~PAGE_VALID; } - tlb_flush(env, 1); + tlb_flush(CPU(cpu), 1); } static inline void ppc4xx_tlb_invalidate_virt(CPUPPCState *env, @@ -862,6 +864,7 @@ static int mmubooke_get_physical_address(CPUPPCState *env, mmu_ctx_t *ctx, static void booke206_flush_tlb(CPUPPCState *env, int flags, const int check_iprot) { + PowerPCCPU *cpu = ppc_env_get_cpu(env); int tlb_size; int i, j; ppcmas_tlb_t *tlb = env->tlb.tlbm; @@ -878,7 +881,7 @@ static void booke206_flush_tlb(CPUPPCState *env, int flags, tlb += booke206_tlb_size(env, i); } - tlb_flush(env, 1); + tlb_flush(CPU(cpu), 1); } static hwaddr booke206_tlb_to_page_size(CPUPPCState *env, @@ -1918,7 +1921,7 @@ void ppc_tlb_invalidate_all(CPUPPCState *env) cpu_abort(CPU(cpu), "MPC8xx MMU model is not implemented\n"); break; case POWERPC_MMU_BOOKE: - tlb_flush(env, 1); + tlb_flush(CPU(cpu), 1); break; case POWERPC_MMU_BOOKE206: booke206_flush_tlb(env, -1, 0); @@ -1931,7 +1934,7 @@ void ppc_tlb_invalidate_all(CPUPPCState *env) case POWERPC_MMU_2_06a: case POWERPC_MMU_2_06d: #endif /* defined(TARGET_PPC64) */ - tlb_flush(env, 1); + tlb_flush(CPU(cpu), 1); break; default: /* XXX: TODO */ @@ -2009,7 +2012,7 @@ void ppc_tlb_invalidate_one(CPUPPCState *env, target_ulong addr) * and we still don't have a tlb_flush_mask(env, n, mask) in QEMU, * we just invalidate all TLBs */ - tlb_flush(env, 1); + tlb_flush(CPU(cpu), 1); break; #endif /* defined(TARGET_PPC64) */ default: @@ -2026,6 +2029,8 @@ void ppc_tlb_invalidate_one(CPUPPCState *env, target_ulong addr) /* Special registers manipulation */ void ppc_store_sdr1(CPUPPCState *env, target_ulong value) { + PowerPCCPU *cpu = ppc_env_get_cpu(env); + LOG_MMU("%s: " TARGET_FMT_lx "\n", __func__, value); assert(!env->external_htab); if (env->spr[SPR_SDR1] != value) { @@ -2048,7 +2053,7 @@ void ppc_store_sdr1(CPUPPCState *env, target_ulong value) env->htab_mask = ((value & SDR_32_HTABMASK) << 16) | 0xFFFF; env->htab_base = value & SDR_32_HTABORG; } - tlb_flush(env, 1); + tlb_flush(CPU(cpu), 1); } } @@ -2066,6 +2071,8 @@ target_ulong helper_load_sr(CPUPPCState *env, target_ulong sr_num) void helper_store_sr(CPUPPCState *env, target_ulong srnum, target_ulong value) { + PowerPCCPU *cpu = ppc_env_get_cpu(env); + LOG_MMU("%s: reg=%d " TARGET_FMT_lx " " TARGET_FMT_lx "\n", __func__, (int)srnum, value, env->sr[srnum]); #if defined(TARGET_PPC64) @@ -2098,11 +2105,11 @@ void helper_store_sr(CPUPPCState *env, target_ulong srnum, target_ulong value) page = (16 << 20) * srnum; end = page + (16 << 20); for (; page != end; page += TARGET_PAGE_SIZE) { - tlb_flush_page(env, page); + tlb_flush_page(CPU(cpu), page); } } #else - tlb_flush(env, 1); + tlb_flush(CPU(cpu), 1); #endif } } @@ -2424,6 +2431,7 @@ target_ulong helper_4xx_tlbsx(CPUPPCState *env, target_ulong address) void helper_440_tlbwe(CPUPPCState *env, uint32_t word, target_ulong entry, target_ulong value) { + PowerPCCPU *cpu = ppc_env_get_cpu(env); ppcemb_tlb_t *tlb; target_ulong EPN, RPN, size; int do_flush_tlbs; @@ -2459,13 +2467,13 @@ void helper_440_tlbwe(CPUPPCState *env, uint32_t word, target_ulong entry, } tlb->PID = env->spr[SPR_440_MMUCR] & 0x000000FF; if (do_flush_tlbs) { - tlb_flush(env, 1); + tlb_flush(CPU(cpu), 1); } break; case 1: RPN = value & 0xFFFFFC0F; if ((tlb->prot & PAGE_VALID) && tlb->RPN != RPN) { - tlb_flush(env, 1); + tlb_flush(CPU(cpu), 1); } tlb->RPN = RPN; break; @@ -2577,9 +2585,11 @@ static ppcmas_tlb_t *booke206_cur_tlb(CPUPPCState *env) void helper_booke_setpid(CPUPPCState *env, uint32_t pidn, target_ulong pid) { + PowerPCCPU *cpu = ppc_env_get_cpu(env); + env->spr[pidn] = pid; /* changing PIDs mean we're in a different address space now */ - tlb_flush(env, 1); + tlb_flush(CPU(cpu), 1); } void helper_booke206_tlbwe(CPUPPCState *env) @@ -2674,7 +2684,7 @@ void helper_booke206_tlbwe(CPUPPCState *env) if (booke206_tlb_to_page_size(env, tlb) == TARGET_PAGE_SIZE) { tlb_flush_page(CPU(cpu), tlb->mas2 & MAS2_EPN_MASK); } else { - tlb_flush(env, 1); + tlb_flush(CPU(cpu), 1); } } @@ -2798,7 +2808,7 @@ void helper_booke206_tlbivax(CPUPPCState *env, target_ulong address) if (address & 0x8) { /* flush TLB1 entries */ booke206_invalidate_ea_tlb(env, 1, address); - tlb_flush(env, 1); + tlb_flush(CPU(cpu), 1); } else { /* flush TLB0 entries */ booke206_invalidate_ea_tlb(env, 0, address); @@ -2814,6 +2824,7 @@ void helper_booke206_tlbilx0(CPUPPCState *env, target_ulong address) void helper_booke206_tlbilx1(CPUPPCState *env, target_ulong address) { + PowerPCCPU *cpu = ppc_env_get_cpu(env); int i, j; int tid = (env->spr[SPR_BOOKE_MAS6] & MAS6_SPID); ppcmas_tlb_t *tlb = env->tlb.tlbm; @@ -2830,11 +2841,12 @@ void helper_booke206_tlbilx1(CPUPPCState *env, target_ulong address) } tlb += booke206_tlb_size(env, i); } - tlb_flush(env, 1); + tlb_flush(CPU(cpu), 1); } void helper_booke206_tlbilx3(CPUPPCState *env, target_ulong address) { + PowerPCCPU *cpu = ppc_env_get_cpu(env); int i, j; ppcmas_tlb_t *tlb; int tid = (env->spr[SPR_BOOKE_MAS6] & MAS6_SPID); @@ -2870,7 +2882,7 @@ void helper_booke206_tlbilx3(CPUPPCState *env, target_ulong address) tlb->mas1 &= ~MAS1_VALID; } } - tlb_flush(env, 1); + tlb_flush(CPU(cpu), 1); } void helper_booke206_tlbflush(CPUPPCState *env, uint32_t type) diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c index 267a3765b4..6084f40f28 100644 --- a/target-ppc/translate_init.c +++ b/target-ppc/translate_init.c @@ -8435,7 +8435,7 @@ static void ppc_cpu_reset(CPUState *s) #endif /* TARGET_PPC64 */ /* Flush all TLBs */ - tlb_flush(env, 1); + tlb_flush(s, 1); } static void ppc_cpu_initfn(Object *obj) diff --git a/target-s390x/cpu.c b/target-s390x/cpu.c index ae78ebc5f7..dfd83e8aef 100644 --- a/target-s390x/cpu.c +++ b/target-s390x/cpu.c @@ -98,7 +98,7 @@ static void s390_cpu_reset(CPUState *s) #if !defined(CONFIG_USER_ONLY) s->halted = 1; #endif - tlb_flush(env, 1); + tlb_flush(s, 1); } /* S390CPUClass::initial_reset() */ @@ -153,7 +153,7 @@ static void s390_cpu_full_reset(CPUState *s) #if !defined(CONFIG_USER_ONLY) s->halted = 1; #endif - tlb_flush(env, 1); + tlb_flush(s, 1); } #if !defined(CONFIG_USER_ONLY) diff --git a/target-s390x/mem_helper.c b/target-s390x/mem_helper.c index 607501890c..d8ca3007f8 100644 --- a/target-s390x/mem_helper.c +++ b/target-s390x/mem_helper.c @@ -810,6 +810,7 @@ void HELPER(tr)(CPUS390XState *env, uint32_t len, uint64_t array, #if !defined(CONFIG_USER_ONLY) void HELPER(lctlg)(CPUS390XState *env, uint32_t r1, uint64_t a2, uint32_t r3) { + S390CPU *cpu = s390_env_get_cpu(env); int i; uint64_t src = a2; @@ -824,11 +825,12 @@ void HELPER(lctlg)(CPUS390XState *env, uint32_t r1, uint64_t a2, uint32_t r3) } } - tlb_flush(env, 1); + tlb_flush(CPU(cpu), 1); } void HELPER(lctl)(CPUS390XState *env, uint32_t r1, uint64_t a2, uint32_t r3) { + S390CPU *cpu = s390_env_get_cpu(env); int i; uint64_t src = a2; @@ -842,7 +844,7 @@ void HELPER(lctl)(CPUS390XState *env, uint32_t r1, uint64_t a2, uint32_t r3) } } - tlb_flush(env, 1); + tlb_flush(CPU(cpu), 1); } void HELPER(stctg)(CPUS390XState *env, uint32_t r1, uint64_t a2, uint32_t r3) @@ -935,6 +937,7 @@ uint32_t HELPER(rrbe)(CPUS390XState *env, uint64_t r2) /* compare and swap and purge */ uint32_t HELPER(csp)(CPUS390XState *env, uint32_t r1, uint64_t r2) { + S390CPU *cpu = s390_env_get_cpu(env); uint32_t cc; uint32_t o1 = env->regs[r1]; uint64_t a2 = r2 & ~3ULL; @@ -944,7 +947,7 @@ uint32_t HELPER(csp)(CPUS390XState *env, uint32_t r1, uint64_t r2) cpu_stl_data(env, a2, env->regs[(r1 + 1) & 15]); if (r2 & 0x3) { /* flush TLB / ALB */ - tlb_flush(env, 1); + tlb_flush(CPU(cpu), 1); } cc = 0; } else { @@ -1040,7 +1043,9 @@ void HELPER(ipte)(CPUS390XState *env, uint64_t pte_addr, uint64_t vaddr) /* flush local tlb */ void HELPER(ptlb)(CPUS390XState *env) { - tlb_flush(env, 1); + S390CPU *cpu = s390_env_get_cpu(env); + + tlb_flush(CPU(cpu), 1); } /* store using real address */ diff --git a/target-sh4/cpu.c b/target-sh4/cpu.c index 4e0e2179cc..e7f05212da 100644 --- a/target-sh4/cpu.c +++ b/target-sh4/cpu.c @@ -54,7 +54,7 @@ static void superh_cpu_reset(CPUState *s) scc->parent_reset(s); memset(env, 0, offsetof(CPUSH4State, id)); - tlb_flush(env, 1); + tlb_flush(s, 1); env->pc = 0xA0000000; #if defined(CONFIG_USER_ONLY) diff --git a/target-sh4/helper.c b/target-sh4/helper.c index 9eb258517f..88f69be216 100644 --- a/target-sh4/helper.c +++ b/target-sh4/helper.c @@ -585,7 +585,7 @@ void cpu_load_tlb(CPUSH4State * env) entry->v = 0; } - tlb_flush(s, 1); + tlb_flush(CPU(sh_env_get_cpu(s)), 1); } uint32_t cpu_sh4_read_mmaped_itlb_addr(CPUSH4State *s, diff --git a/target-sparc/cpu.c b/target-sparc/cpu.c index 8465a0b18a..d9f37e9b6a 100644 --- a/target-sparc/cpu.c +++ b/target-sparc/cpu.c @@ -34,7 +34,7 @@ static void sparc_cpu_reset(CPUState *s) scc->parent_reset(s); memset(env, 0, offsetof(CPUSPARCState, version)); - tlb_flush(env, 1); + tlb_flush(s, 1); env->cwp = 0; #ifndef TARGET_SPARC64 env->wim = 1; diff --git a/target-sparc/ldst_helper.c b/target-sparc/ldst_helper.c index 36fe2de441..ec14802573 100644 --- a/target-sparc/ldst_helper.c +++ b/target-sparc/ldst_helper.c @@ -871,7 +871,7 @@ void helper_st_asi(CPUSPARCState *env, target_ulong addr, uint64_t val, int asi, case 2: /* flush region (16M) */ case 3: /* flush context (4G) */ case 4: /* flush entire */ - tlb_flush(env, 1); + tlb_flush(CPU(cpu), 1); break; default: break; @@ -896,7 +896,7 @@ void helper_st_asi(CPUSPARCState *env, target_ulong addr, uint64_t val, int asi, disabled mode are invalid in normal mode */ if ((oldreg & (MMU_E | MMU_NF | env->def->mmu_bm)) != (env->mmuregs[reg] & (MMU_E | MMU_NF | env->def->mmu_bm))) { - tlb_flush(env, 1); + tlb_flush(CPU(cpu), 1); } break; case 1: /* Context Table Pointer Register */ @@ -907,7 +907,7 @@ void helper_st_asi(CPUSPARCState *env, target_ulong addr, uint64_t val, int asi, if (oldreg != env->mmuregs[reg]) { /* we flush when the MMU context changes because QEMU has no MMU context support */ - tlb_flush(env, 1); + tlb_flush(CPU(cpu), 1); } break; case 3: /* Synchronous Fault Status Register with Clear */ @@ -1663,7 +1663,9 @@ uint64_t helper_ld_asi(CPUSPARCState *env, target_ulong addr, int asi, int size, void helper_st_asi(CPUSPARCState *env, target_ulong addr, target_ulong val, int asi, int size) { - CPUState *cs = CPU(sparc_env_get_cpu(env)); + SPARCCPU *cpu = sparc_env_get_cpu(env); + CPUState *cs = CPU(cpu); + #ifdef DEBUG_ASI dump_asi("write", addr, asi, size, val); #endif @@ -1872,7 +1874,7 @@ void helper_st_asi(CPUSPARCState *env, target_ulong addr, target_ulong val, #ifdef DEBUG_MMU dump_mmu(stdout, fprintf, env); #endif - tlb_flush(env, 1); + tlb_flush(CPU(cpu), 1); } return; } @@ -1961,13 +1963,13 @@ void helper_st_asi(CPUSPARCState *env, target_ulong addr, target_ulong val, env->dmmu.mmu_primary_context = val; /* can be optimized to only flush MMU_USER_IDX and MMU_KERNEL_IDX entries */ - tlb_flush(env, 1); + tlb_flush(CPU(cpu), 1); break; case 2: /* Secondary context */ env->dmmu.mmu_secondary_context = val; /* can be optimized to only flush MMU_USER_SECONDARY_IDX and MMU_KERNEL_SECONDARY_IDX entries */ - tlb_flush(env, 1); + tlb_flush(CPU(cpu), 1); break; case 5: /* TSB access */ DPRINTF_MMU("dmmu TSB write: 0x%016" PRIx64 " -> 0x%016" @@ -2397,7 +2399,7 @@ void sparc_cpu_unassigned_access(CPUState *cs, hwaddr addr, /* flush neverland mappings created during no-fault mode, so the sequential MMU faults report proper fault types */ if (env->mmuregs[0] & MMU_NF) { - tlb_flush(env, 1); + tlb_flush(cs, 1); } } #else diff --git a/target-sparc/machine.c b/target-sparc/machine.c index a353dabdd9..3f3de4c65a 100644 --- a/target-sparc/machine.c +++ b/target-sparc/machine.c @@ -112,6 +112,7 @@ void cpu_save(QEMUFile *f, void *opaque) int cpu_load(QEMUFile *f, void *opaque, int version_id) { CPUSPARCState *env = opaque; + SPARCCPU *cpu = sparc_env_get_cpu(env); int i; uint32_t tmp; @@ -212,6 +213,6 @@ int cpu_load(QEMUFile *f, void *opaque, int version_id) qemu_get_be64s(f, &env->ssr); cpu_get_timer(f, env->hstick); #endif - tlb_flush(env, 1); + tlb_flush(CPU(cpu), 1); return 0; } diff --git a/target-unicore32/cpu.c b/target-unicore32/cpu.c index 24dec13985..2d2c429a35 100644 --- a/target-unicore32/cpu.c +++ b/target-unicore32/cpu.c @@ -121,7 +121,7 @@ static void uc32_cpu_initfn(Object *obj) env->regs[31] = 0x03000000; #endif - tlb_flush(env, 1); + tlb_flush(cs, 1); if (tcg_enabled() && !inited) { inited = true; diff --git a/target-unicore32/helper.c b/target-unicore32/helper.c index 195e1bfca9..169c85cb4d 100644 --- a/target-unicore32/helper.c +++ b/target-unicore32/helper.c @@ -50,6 +50,8 @@ uint32_t HELPER(clz)(uint32_t x) void helper_cp0_set(CPUUniCore32State *env, uint32_t val, uint32_t creg, uint32_t cop) { + UniCore32CPU *cpu = uc32_env_get_cpu(env); + /* * movc pp.nn, rn, #imm9 * rn: UCOP_REG_D @@ -118,7 +120,7 @@ void helper_cp0_set(CPUUniCore32State *env, uint32_t val, uint32_t creg, case 6: if ((cop <= 6) && (cop >= 2)) { /* invalid all tlb */ - tlb_flush(env, 1); + tlb_flush(CPU(cpu), 1); return; } break; diff --git a/target-xtensa/op_helper.c b/target-xtensa/op_helper.c index cae9cf4ad6..1eec89155c 100644 --- a/target-xtensa/op_helper.c +++ b/target-xtensa/op_helper.c @@ -487,10 +487,12 @@ void HELPER(check_atomctl)(CPUXtensaState *env, uint32_t pc, uint32_t vaddr) void HELPER(wsr_rasid)(CPUXtensaState *env, uint32_t v) { + XtensaCPU *cpu = xtensa_env_get_cpu(env); + v = (v & 0xffffff00) | 0x1; if (v != env->sregs[RASID]) { env->sregs[RASID] = v; - tlb_flush(env, 1); + tlb_flush(CPU(cpu), 1); } } -- cgit 1.4.1 From 0c591eb0a9d0593d71d7cb61f4184222ac14fdd2 Mon Sep 17 00:00:00 2001 From: Andreas Färber Date: Tue, 3 Sep 2013 13:59:37 +0200 Subject: cputlb: Change tlb_set_page() argument to CPUState MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Andreas Färber --- cputlb.c | 4 ++-- include/exec/exec-all.h | 2 +- target-alpha/helper.c | 2 +- target-arm/helper.c | 2 +- target-cris/helper.c | 2 +- target-i386/helper.c | 2 +- target-lm32/helper.c | 6 +++--- target-m68k/helper.c | 3 +-- target-microblaze/helper.c | 4 ++-- target-mips/helper.c | 2 +- target-moxie/helper.c | 2 +- target-openrisc/mmu.c | 2 +- target-ppc/mmu-hash32.c | 8 ++++---- target-ppc/mmu-hash64.c | 4 ++-- target-ppc/mmu_helper.c | 2 +- target-s390x/helper.c | 2 +- target-sh4/helper.c | 2 +- target-sparc/mmu_helper.c | 6 +++--- target-unicore32/softmmu.c | 2 +- target-xtensa/op_helper.c | 8 ++++---- 20 files changed, 33 insertions(+), 34 deletions(-) (limited to 'include/exec/exec-all.h') diff --git a/cputlb.c b/cputlb.c index b280e81c6f..7bd3573025 100644 --- a/cputlb.c +++ b/cputlb.c @@ -221,10 +221,11 @@ static void tlb_add_large_page(CPUArchState *env, target_ulong vaddr, /* Add a new TLB entry. At most one entry for a given virtual address is permitted. Only a single TARGET_PAGE_SIZE region is mapped, the supplied size is only used by tlb_flush_page. */ -void tlb_set_page(CPUArchState *env, target_ulong vaddr, +void tlb_set_page(CPUState *cpu, target_ulong vaddr, hwaddr paddr, int prot, int mmu_idx, target_ulong size) { + CPUArchState *env = cpu->env_ptr; MemoryRegionSection *section; unsigned int index; target_ulong address; @@ -232,7 +233,6 @@ void tlb_set_page(CPUArchState *env, target_ulong vaddr, uintptr_t addend; CPUTLBEntry *te; hwaddr iotlb, xlat, sz; - CPUState *cpu = ENV_GET_CPU(env); assert(size >= TARGET_PAGE_SIZE); if (size != TARGET_PAGE_SIZE) { diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index 4cc11bb652..502b7aa084 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -100,7 +100,7 @@ void tcg_cpu_address_space_init(CPUState *cpu, AddressSpace *as); /* cputlb.c */ void tlb_flush_page(CPUState *cpu, target_ulong addr); void tlb_flush(CPUState *cpu, int flush_global); -void tlb_set_page(CPUArchState *env, target_ulong vaddr, +void tlb_set_page(CPUState *cpu, target_ulong vaddr, hwaddr paddr, int prot, int mmu_idx, target_ulong size); void tb_invalidate_phys_addr(AddressSpace *as, hwaddr addr); diff --git a/target-alpha/helper.c b/target-alpha/helper.c index fdb033564c..cbd03c415b 100644 --- a/target-alpha/helper.c +++ b/target-alpha/helper.c @@ -345,7 +345,7 @@ int alpha_cpu_handle_mmu_fault(CPUState *cs, vaddr addr, int rw, return 1; } - tlb_set_page(env, addr & TARGET_PAGE_MASK, phys & TARGET_PAGE_MASK, + tlb_set_page(cs, addr & TARGET_PAGE_MASK, phys & TARGET_PAGE_MASK, prot, mmu_idx, TARGET_PAGE_SIZE); return 0; } diff --git a/target-arm/helper.c b/target-arm/helper.c index a9db2796c5..aa5f22d14f 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -3676,7 +3676,7 @@ int arm_cpu_handle_mmu_fault(CPUState *cs, vaddr address, /* Map a single [sub]page. */ phys_addr &= ~(hwaddr)0x3ff; address &= ~(uint32_t)0x3ff; - tlb_set_page (env, address, phys_addr, prot, mmu_idx, page_size); + tlb_set_page(cs, address, phys_addr, prot, mmu_idx, page_size); return 0; } diff --git a/target-cris/helper.c b/target-cris/helper.c index ec84b57c0b..4092d279ba 100644 --- a/target-cris/helper.c +++ b/target-cris/helper.c @@ -106,7 +106,7 @@ int cris_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw, */ phy = res.phy & ~0x80000000; prot = res.prot; - tlb_set_page(env, address & TARGET_PAGE_MASK, phy, + tlb_set_page(cs, address & TARGET_PAGE_MASK, phy, prot, mmu_idx, TARGET_PAGE_SIZE); r = 0; } diff --git a/target-i386/helper.c b/target-i386/helper.c index 54899a0542..4f447b8cf9 100644 --- a/target-i386/helper.c +++ b/target-i386/helper.c @@ -877,7 +877,7 @@ int x86_cpu_handle_mmu_fault(CPUState *cs, vaddr addr, paddr = (pte & TARGET_PAGE_MASK) + page_offset; vaddr = virt_addr + page_offset; - tlb_set_page(env, vaddr, paddr, prot, mmu_idx, page_size); + tlb_set_page(cs, vaddr, paddr, prot, mmu_idx, page_size); return 0; do_fault_protect: error_code = PG_ERROR_P_MASK; diff --git a/target-lm32/helper.c b/target-lm32/helper.c index 3adfea9ef0..783aa16a45 100644 --- a/target-lm32/helper.c +++ b/target-lm32/helper.c @@ -30,10 +30,10 @@ int lm32_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw, address &= TARGET_PAGE_MASK; prot = PAGE_BITS; if (env->flags & LM32_FLAG_IGNORE_MSB) { - tlb_set_page(env, address, address & 0x7fffffff, prot, mmu_idx, - TARGET_PAGE_SIZE); + tlb_set_page(cs, address, address & 0x7fffffff, prot, mmu_idx, + TARGET_PAGE_SIZE); } else { - tlb_set_page(env, address, address, prot, mmu_idx, TARGET_PAGE_SIZE); + tlb_set_page(cs, address, address, prot, mmu_idx, TARGET_PAGE_SIZE); } return 0; diff --git a/target-m68k/helper.c b/target-m68k/helper.c index 276fb4bcc9..077b653f24 100644 --- a/target-m68k/helper.c +++ b/target-m68k/helper.c @@ -303,12 +303,11 @@ hwaddr m68k_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) int m68k_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw, int mmu_idx) { - M68kCPU *cpu = M68K_CPU(cs); int prot; address &= TARGET_PAGE_MASK; prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; - tlb_set_page(&cpu->env, address, address, prot, mmu_idx, TARGET_PAGE_SIZE); + tlb_set_page(cs, address, address, prot, mmu_idx, TARGET_PAGE_SIZE); return 0; } diff --git a/target-microblaze/helper.c b/target-microblaze/helper.c index 11d8aa266d..59c9ad5aef 100644 --- a/target-microblaze/helper.c +++ b/target-microblaze/helper.c @@ -77,7 +77,7 @@ int mb_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw, DMMU(qemu_log("MMU map mmu=%d v=%x p=%x prot=%x\n", mmu_idx, vaddr, paddr, lu.prot)); - tlb_set_page(env, vaddr, paddr, lu.prot, mmu_idx, TARGET_PAGE_SIZE); + tlb_set_page(cs, vaddr, paddr, lu.prot, mmu_idx, TARGET_PAGE_SIZE); r = 0; } else { env->sregs[SR_EAR] = address; @@ -108,7 +108,7 @@ int mb_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw, /* MMU disabled or not available. */ address &= TARGET_PAGE_MASK; prot = PAGE_BITS; - tlb_set_page(env, address, address, prot, mmu_idx, TARGET_PAGE_SIZE); + tlb_set_page(cs, address, address, prot, mmu_idx, TARGET_PAGE_SIZE); r = 0; } return r; diff --git a/target-mips/helper.c b/target-mips/helper.c index f3879eddda..b28ae9b033 100644 --- a/target-mips/helper.c +++ b/target-mips/helper.c @@ -300,7 +300,7 @@ int mips_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw, " prot %d\n", __func__, address, ret, physical, prot); if (ret == TLBRET_MATCH) { - tlb_set_page(env, address & TARGET_PAGE_MASK, + tlb_set_page(cs, address & TARGET_PAGE_MASK, physical & TARGET_PAGE_MASK, prot | PAGE_EXEC, mmu_idx, TARGET_PAGE_SIZE); ret = 0; diff --git a/target-moxie/helper.c b/target-moxie/helper.c index 04b36b78b5..3d0c34dd0a 100644 --- a/target-moxie/helper.c +++ b/target-moxie/helper.c @@ -148,7 +148,7 @@ int moxie_cpu_handle_mmu_fault(CPUState *cs, vaddr address, phy = res.phy; r = 0; } - tlb_set_page(env, address, phy, prot, mmu_idx, TARGET_PAGE_SIZE); + tlb_set_page(cs, address, phy, prot, mmu_idx, TARGET_PAGE_SIZE); return r; } diff --git a/target-openrisc/mmu.c b/target-openrisc/mmu.c index 4222219acd..750a93636b 100644 --- a/target-openrisc/mmu.c +++ b/target-openrisc/mmu.c @@ -187,7 +187,7 @@ int openrisc_cpu_handle_mmu_fault(CPUState *cs, address, rw); if (ret == TLBRET_MATCH) { - tlb_set_page(&cpu->env, address & TARGET_PAGE_MASK, + tlb_set_page(cs, address & TARGET_PAGE_MASK, physical & TARGET_PAGE_MASK, prot, mmu_idx, TARGET_PAGE_SIZE); ret = 0; diff --git a/target-ppc/mmu-hash32.c b/target-ppc/mmu-hash32.c index 6a4d6a8025..1cc19162b7 100644 --- a/target-ppc/mmu-hash32.c +++ b/target-ppc/mmu-hash32.c @@ -400,7 +400,7 @@ int ppc_hash32_handle_mmu_fault(PowerPCCPU *cpu, target_ulong eaddr, int rwx, if (((rwx == 2) && (msr_ir == 0)) || ((rwx != 2) && (msr_dr == 0))) { /* Translation is off */ raddr = eaddr; - tlb_set_page(env, eaddr & TARGET_PAGE_MASK, raddr & TARGET_PAGE_MASK, + tlb_set_page(cs, eaddr & TARGET_PAGE_MASK, raddr & TARGET_PAGE_MASK, PAGE_READ | PAGE_WRITE | PAGE_EXEC, mmu_idx, TARGET_PAGE_SIZE); return 0; @@ -427,7 +427,7 @@ int ppc_hash32_handle_mmu_fault(PowerPCCPU *cpu, target_ulong eaddr, int rwx, return 1; } - tlb_set_page(env, eaddr & TARGET_PAGE_MASK, + tlb_set_page(cs, eaddr & TARGET_PAGE_MASK, raddr & TARGET_PAGE_MASK, prot, mmu_idx, TARGET_PAGE_SIZE); return 0; @@ -441,7 +441,7 @@ int ppc_hash32_handle_mmu_fault(PowerPCCPU *cpu, target_ulong eaddr, int rwx, if (sr & SR32_T) { if (ppc_hash32_direct_store(env, sr, eaddr, rwx, &raddr, &prot) == 0) { - tlb_set_page(env, eaddr & TARGET_PAGE_MASK, + tlb_set_page(cs, eaddr & TARGET_PAGE_MASK, raddr & TARGET_PAGE_MASK, prot, mmu_idx, TARGET_PAGE_SIZE); return 0; @@ -522,7 +522,7 @@ int ppc_hash32_handle_mmu_fault(PowerPCCPU *cpu, target_ulong eaddr, int rwx, raddr = ppc_hash32_pte_raddr(sr, pte, eaddr); - tlb_set_page(env, eaddr & TARGET_PAGE_MASK, raddr & TARGET_PAGE_MASK, + tlb_set_page(cs, eaddr & TARGET_PAGE_MASK, raddr & TARGET_PAGE_MASK, prot, mmu_idx, TARGET_PAGE_SIZE); return 0; diff --git a/target-ppc/mmu-hash64.c b/target-ppc/mmu-hash64.c index 3f405b3cc9..1fefe5881e 100644 --- a/target-ppc/mmu-hash64.c +++ b/target-ppc/mmu-hash64.c @@ -476,7 +476,7 @@ int ppc_hash64_handle_mmu_fault(PowerPCCPU *cpu, target_ulong eaddr, /* Translation is off */ /* In real mode the top 4 effective address bits are ignored */ raddr = eaddr & 0x0FFFFFFFFFFFFFFFULL; - tlb_set_page(env, eaddr & TARGET_PAGE_MASK, raddr & TARGET_PAGE_MASK, + tlb_set_page(cs, eaddr & TARGET_PAGE_MASK, raddr & TARGET_PAGE_MASK, PAGE_READ | PAGE_WRITE | PAGE_EXEC, mmu_idx, TARGET_PAGE_SIZE); return 0; @@ -578,7 +578,7 @@ int ppc_hash64_handle_mmu_fault(PowerPCCPU *cpu, target_ulong eaddr, raddr = ppc_hash64_pte_raddr(slb, pte, eaddr); - tlb_set_page(env, eaddr & TARGET_PAGE_MASK, raddr & TARGET_PAGE_MASK, + tlb_set_page(cs, eaddr & TARGET_PAGE_MASK, raddr & TARGET_PAGE_MASK, prot, mmu_idx, TARGET_PAGE_SIZE); return 0; diff --git a/target-ppc/mmu_helper.c b/target-ppc/mmu_helper.c index 653e50230e..1771863dff 100644 --- a/target-ppc/mmu_helper.c +++ b/target-ppc/mmu_helper.c @@ -1514,7 +1514,7 @@ static int cpu_ppc_handle_mmu_fault(CPUPPCState *env, target_ulong address, } ret = get_physical_address(env, &ctx, address, rw, access_type); if (ret == 0) { - tlb_set_page(env, address & TARGET_PAGE_MASK, + tlb_set_page(cs, address & TARGET_PAGE_MASK, ctx.raddr & TARGET_PAGE_MASK, ctx.prot, mmu_idx, TARGET_PAGE_SIZE); ret = 0; diff --git a/target-s390x/helper.c b/target-s390x/helper.c index d4ea7d56d1..aa628b8fe2 100644 --- a/target-s390x/helper.c +++ b/target-s390x/helper.c @@ -417,7 +417,7 @@ int s390_cpu_handle_mmu_fault(CPUState *cs, vaddr orig_vaddr, DPRINTF("%s: set tlb %" PRIx64 " -> %" PRIx64 " (%x)\n", __func__, (uint64_t)vaddr, (uint64_t)raddr, prot); - tlb_set_page(env, orig_vaddr, raddr, prot, + tlb_set_page(cs, orig_vaddr, raddr, prot, mmu_idx, TARGET_PAGE_SIZE); return 0; diff --git a/target-sh4/helper.c b/target-sh4/helper.c index 88f69be216..9ebdd5c9b5 100644 --- a/target-sh4/helper.c +++ b/target-sh4/helper.c @@ -512,7 +512,7 @@ int superh_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw, address &= TARGET_PAGE_MASK; physical &= TARGET_PAGE_MASK; - tlb_set_page(env, address, physical, prot, mmu_idx, TARGET_PAGE_SIZE); + tlb_set_page(cs, address, physical, prot, mmu_idx, TARGET_PAGE_SIZE); return 0; } diff --git a/target-sparc/mmu_helper.c b/target-sparc/mmu_helper.c index 1571c6a026..61afbcf048 100644 --- a/target-sparc/mmu_helper.c +++ b/target-sparc/mmu_helper.c @@ -217,7 +217,7 @@ int sparc_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw, printf("Translate at %" VADDR_PRIx " -> " TARGET_FMT_plx ", vaddr " TARGET_FMT_lx "\n", address, paddr, vaddr); #endif - tlb_set_page(env, vaddr, paddr, prot, mmu_idx, page_size); + tlb_set_page(cs, vaddr, paddr, prot, mmu_idx, page_size); return 0; } @@ -233,7 +233,7 @@ int sparc_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw, neverland. Fake/overridden mappings will be flushed when switching to normal mode. */ prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; - tlb_set_page(env, vaddr, paddr, prot, mmu_idx, TARGET_PAGE_SIZE); + tlb_set_page(cs, vaddr, paddr, prot, mmu_idx, TARGET_PAGE_SIZE); return 0; } else { if (rw & 2) { @@ -729,7 +729,7 @@ int sparc_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw, env->dmmu.mmu_primary_context, env->dmmu.mmu_secondary_context); - tlb_set_page(env, vaddr, paddr, prot, mmu_idx, page_size); + tlb_set_page(cs, vaddr, paddr, prot, mmu_idx, page_size); return 0; } /* XXX */ diff --git a/target-unicore32/softmmu.c b/target-unicore32/softmmu.c index 39ecd98907..9a3786dddb 100644 --- a/target-unicore32/softmmu.c +++ b/target-unicore32/softmmu.c @@ -253,7 +253,7 @@ int uc32_cpu_handle_mmu_fault(CPUState *cs, vaddr address, /* Map a single page. */ phys_addr &= TARGET_PAGE_MASK; address &= TARGET_PAGE_MASK; - tlb_set_page(env, address, phys_addr, prot, mmu_idx, page_size); + tlb_set_page(cs, address, phys_addr, prot, mmu_idx, page_size); return 0; } diff --git a/target-xtensa/op_helper.c b/target-xtensa/op_helper.c index 1eec89155c..b531019488 100644 --- a/target-xtensa/op_helper.c +++ b/target-xtensa/op_helper.c @@ -77,10 +77,10 @@ void tlb_fill(CPUState *cs, vaddr, is_write, mmu_idx, paddr, ret); if (ret == 0) { - tlb_set_page(env, - vaddr & TARGET_PAGE_MASK, - paddr & TARGET_PAGE_MASK, - access, mmu_idx, page_size); + tlb_set_page(cs, + vaddr & TARGET_PAGE_MASK, + paddr & TARGET_PAGE_MASK, + access, mmu_idx, page_size); } else { cpu_restore_state(cs, retaddr); HELPER(exception_cause_vaddr)(env, env->pc, ret, vaddr); -- cgit 1.4.1