From 3b6434953934e6d4a776ed426d8c6d6badee176f Mon Sep 17 00:00:00 2001 From: Peter Maydell Date: Sun, 26 Apr 2015 16:49:23 +0100 Subject: memory: Replace io_mem_read/write with memory_region_dispatch_read/write MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Rather than retaining io_mem_read/write as simple wrappers around the memory_region_dispatch_read/write functions, make the latter public and change all the callers to use them, since we need to touch all the callsites anyway to add MemTxAttrs and MemTxResult support. Delete io_mem_read and io_mem_write entirely. (All the callers currently pass MEMTXATTRS_UNSPECIFIED and convert the return value back to bool or ignore it.) Signed-off-by: Peter Maydell Reviewed-by: Alex Bennée --- include/exec/exec-all.h | 4 ---- 1 file changed, 4 deletions(-) (limited to 'include/exec/exec-all.h') diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index 8eb0db3910..ff1bc3e4c1 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -341,10 +341,6 @@ void phys_mem_set_alloc(void *(*alloc)(size_t, uint64_t *align)); struct MemoryRegion *iotlb_to_region(CPUState *cpu, hwaddr index); -bool io_mem_read(struct MemoryRegion *mr, hwaddr addr, - uint64_t *pvalue, unsigned size); -bool io_mem_write(struct MemoryRegion *mr, hwaddr addr, - uint64_t value, unsigned size); void tlb_fill(CPUState *cpu, target_ulong addr, int is_write, int mmu_idx, uintptr_t retaddr); -- cgit 1.4.1 From fadc1cbe85c6b032d5842ec0d19d209f50fcb375 Mon Sep 17 00:00:00 2001 From: Peter Maydell Date: Sun, 26 Apr 2015 16:49:24 +0100 Subject: Add MemTxAttrs to the IOTLB MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add a MemTxAttrs field to the IOTLB, and allow target-specific code to set it via a new tlb_set_page_with_attrs() function; pass the attributes through to the device when making IO accesses. Signed-off-by: Peter Maydell Reviewed-by: Paolo Bonzini Reviewed-by: Edgar E. Iglesias Reviewed-by: Alex Bennée --- cputlb.c | 18 +++++++++++++++--- include/exec/cpu-defs.h | 2 ++ include/exec/exec-all.h | 3 +++ softmmu_template.h | 4 ++-- 4 files changed, 22 insertions(+), 5 deletions(-) (limited to 'include/exec/exec-all.h') diff --git a/cputlb.c b/cputlb.c index 5e1cb8f9d2..7606548200 100644 --- a/cputlb.c +++ b/cputlb.c @@ -249,9 +249,9 @@ static void tlb_add_large_page(CPUArchState *env, target_ulong vaddr, * Called from TCG-generated code, which is under an RCU read-side * critical section. */ -void tlb_set_page(CPUState *cpu, target_ulong vaddr, - hwaddr paddr, int prot, - int mmu_idx, target_ulong size) +void tlb_set_page_with_attrs(CPUState *cpu, target_ulong vaddr, + hwaddr paddr, MemTxAttrs attrs, int prot, + int mmu_idx, target_ulong size) { CPUArchState *env = cpu->env_ptr; MemoryRegionSection *section; @@ -302,6 +302,7 @@ void tlb_set_page(CPUState *cpu, target_ulong vaddr, /* refill the tlb */ env->iotlb[mmu_idx][index].addr = iotlb - vaddr; + env->iotlb[mmu_idx][index].attrs = attrs; te->addend = addend - vaddr; if (prot & PAGE_READ) { te->addr_read = address; @@ -331,6 +332,17 @@ void tlb_set_page(CPUState *cpu, target_ulong vaddr, } } +/* Add a new TLB entry, but without specifying the memory + * transaction attributes to be used. + */ +void tlb_set_page(CPUState *cpu, target_ulong vaddr, + hwaddr paddr, int prot, + int mmu_idx, target_ulong size) +{ + tlb_set_page_with_attrs(cpu, vaddr, paddr, MEMTXATTRS_UNSPECIFIED, + prot, mmu_idx, size); +} + /* NOTE: this function can trigger an exception */ /* NOTE2: the returned address is not exactly the physical address: it * is actually a ram_addr_t (in system mode; the user mode emulation diff --git a/include/exec/cpu-defs.h b/include/exec/cpu-defs.h index 7f88185c7f..3f56546066 100644 --- a/include/exec/cpu-defs.h +++ b/include/exec/cpu-defs.h @@ -30,6 +30,7 @@ #ifndef CONFIG_USER_ONLY #include "exec/hwaddr.h" #endif +#include "exec/memattrs.h" #ifndef TARGET_LONG_BITS #error TARGET_LONG_BITS must be defined before including this header @@ -109,6 +110,7 @@ QEMU_BUILD_BUG_ON(sizeof(CPUTLBEntry) != (1 << CPU_TLB_ENTRY_BITS)); */ typedef struct CPUIOTLBEntry { hwaddr addr; + MemTxAttrs attrs; } CPUIOTLBEntry; #define CPU_COMMON_TLB \ diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index ff1bc3e4c1..b58cd47ced 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -105,6 +105,9 @@ void tlb_flush(CPUState *cpu, int flush_global); void tlb_set_page(CPUState *cpu, target_ulong vaddr, hwaddr paddr, int prot, int mmu_idx, target_ulong size); +void tlb_set_page_with_attrs(CPUState *cpu, target_ulong vaddr, + hwaddr paddr, MemTxAttrs attrs, + int prot, int mmu_idx, target_ulong size); void tb_invalidate_phys_addr(AddressSpace *as, hwaddr addr); #else static inline void tlb_flush_page(CPUState *cpu, target_ulong addr) diff --git a/softmmu_template.h b/softmmu_template.h index 0e30986e5b..16b08523e9 100644 --- a/softmmu_template.h +++ b/softmmu_template.h @@ -160,7 +160,7 @@ static inline DATA_TYPE glue(io_read, SUFFIX)(CPUArchState *env, cpu->mem_io_vaddr = addr; memory_region_dispatch_read(mr, physaddr, &val, 1 << SHIFT, - MEMTXATTRS_UNSPECIFIED); + iotlbentry->attrs); return val; } #endif @@ -382,7 +382,7 @@ static inline void glue(io_write, SUFFIX)(CPUArchState *env, cpu->mem_io_vaddr = addr; cpu->mem_io_pc = retaddr; memory_region_dispatch_write(mr, physaddr, val, 1 << SHIFT, - MEMTXATTRS_UNSPECIFIED); + iotlbentry->attrs); } void helper_le_st_name(CPUArchState *env, target_ulong addr, DATA_TYPE val, -- cgit 1.4.1