From 79e4208506651660b866f536616a5f8f3175f909 Mon Sep 17 00:00:00 2001 From: Richard Henderson Date: Fri, 22 Mar 2019 08:36:40 -0700 Subject: tcg: Fold CPUTLBWindow into CPUTLBDesc MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Both structures are allocated once per mmu_idx. There is no reason for them to be separate. Reviewed-by: Alistair Francis Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson --- include/exec/cpu-defs.h | 17 ++++------------- 1 file changed, 4 insertions(+), 13 deletions(-) (limited to 'include/exec') diff --git a/include/exec/cpu-defs.h b/include/exec/cpu-defs.h index 8f2a848bf5..52d150aaf1 100644 --- a/include/exec/cpu-defs.h +++ b/include/exec/cpu-defs.h @@ -127,18 +127,6 @@ typedef struct CPUIOTLBEntry { MemTxAttrs attrs; } CPUIOTLBEntry; -/** - * struct CPUTLBWindow - * @begin_ns: host time (in ns) at the beginning of the time window - * @max_entries: maximum number of entries observed in the window - * - * See also: tlb_mmu_resize_locked() - */ -typedef struct CPUTLBWindow { - int64_t begin_ns; - size_t max_entries; -} CPUTLBWindow; - typedef struct CPUTLBDesc { /* * Describe a region covering all of the large pages allocated @@ -148,9 +136,12 @@ typedef struct CPUTLBDesc { */ target_ulong large_page_addr; target_ulong large_page_mask; + /* host time (in ns) at the beginning of the time window */ + int64_t window_begin_ns; + /* maximum number of entries observed in the window */ + size_t window_max_entries; /* The next index to use in the tlb victim table. */ size_t vindex; - CPUTLBWindow window; size_t n_used_entries; } CPUTLBDesc; -- cgit 1.4.1 From 74433bf083b0766aba81534f92de13194f23ff3e Mon Sep 17 00:00:00 2001 From: Richard Henderson Date: Fri, 22 Mar 2019 11:51:19 -0700 Subject: tcg: Split out target/arch/cpu-param.h For all targets, into this new file move TARGET_LONG_BITS, TARGET_PAGE_BITS, TARGET_PHYS_ADDR_SPACE_BITS, TARGET_VIRT_ADDR_SPACE_BITS, and NB_MMU_MODES. Include this new file from exec/cpu-defs.h. This now removes the somewhat odd requirement that target/arch/cpu.h defines TARGET_LONG_BITS before including exec/cpu-defs.h, so push the bulk of the includes within target/arch/cpu.h to the top. Reviewed-by: Peter Maydell Acked-by: Alistair Francis Signed-off-by: Richard Henderson --- include/exec/cpu-defs.h | 22 +++++++++++++++++++++- target/alpha/cpu-param.h | 31 +++++++++++++++++++++++++++++++ target/alpha/cpu.h | 23 +---------------------- target/arm/cpu-param.h | 34 ++++++++++++++++++++++++++++++++++ target/arm/cpu.h | 33 +++------------------------------ target/cris/cpu-param.h | 17 +++++++++++++++++ target/cris/cpu.h | 11 +---------- target/hppa/cpu-param.h | 34 ++++++++++++++++++++++++++++++++++ target/hppa/cpu.h | 24 +----------------------- target/i386/cpu-param.h | 28 ++++++++++++++++++++++++++++ target/i386/cpu.h | 21 --------------------- target/lm32/cpu-param.h | 17 +++++++++++++++++ target/lm32/cpu.h | 12 +++--------- target/m68k/cpu-param.h | 22 ++++++++++++++++++++++ target/m68k/cpu.h | 16 ++-------------- target/microblaze/cpu-param.h | 18 ++++++++++++++++++ target/microblaze/cpu.h | 14 ++------------ target/mips/cpu-param.h | 29 +++++++++++++++++++++++++++++ target/mips/cpu.h | 3 +-- target/mips/mips-defs.h | 15 --------------- target/moxie/cpu-param.h | 17 +++++++++++++++++ target/moxie/cpu.h | 12 +----------- target/nios2/cpu-param.h | 21 +++++++++++++++++++++ target/nios2/cpu.h | 17 ++--------------- target/openrisc/cpu-param.h | 17 +++++++++++++++++ target/openrisc/cpu.h | 14 +++----------- target/ppc/cpu-param.h | 37 +++++++++++++++++++++++++++++++++++++ target/ppc/cpu.h | 42 ++++-------------------------------------- target/riscv/cpu-param.h | 23 +++++++++++++++++++++++ target/riscv/cpu.h | 21 ++++----------------- target/s390x/cpu-param.h | 17 +++++++++++++++++ target/s390x/cpu.h | 11 +---------- target/sh4/cpu-param.h | 21 +++++++++++++++++++++ target/sh4/cpu.h | 14 +------------- target/sparc/cpu-param.h | 28 ++++++++++++++++++++++++++++ target/sparc/cpu.h | 20 ++------------------ target/tilegx/cpu-param.h | 17 +++++++++++++++++ target/tilegx/cpu.h | 9 +-------- target/tricore/cpu-param.h | 17 +++++++++++++++++ target/tricore/cpu.h | 4 +--- target/tricore/tricore-defs.h | 5 ----- target/unicore32/cpu-param.h | 17 +++++++++++++++++ target/unicore32/cpu.h | 10 +--------- target/xtensa/cpu-param.h | 21 +++++++++++++++++++++ target/xtensa/cpu.h | 21 +++++---------------- 45 files changed, 544 insertions(+), 333 deletions(-) create mode 100644 target/alpha/cpu-param.h create mode 100644 target/arm/cpu-param.h create mode 100644 target/cris/cpu-param.h create mode 100644 target/hppa/cpu-param.h create mode 100644 target/i386/cpu-param.h create mode 100644 target/lm32/cpu-param.h create mode 100644 target/m68k/cpu-param.h create mode 100644 target/microblaze/cpu-param.h create mode 100644 target/mips/cpu-param.h create mode 100644 target/moxie/cpu-param.h create mode 100644 target/nios2/cpu-param.h create mode 100644 target/openrisc/cpu-param.h create mode 100644 target/ppc/cpu-param.h create mode 100644 target/riscv/cpu-param.h create mode 100644 target/s390x/cpu-param.h create mode 100644 target/sh4/cpu-param.h create mode 100644 target/sparc/cpu-param.h create mode 100644 target/tilegx/cpu-param.h create mode 100644 target/tricore/cpu-param.h create mode 100644 target/unicore32/cpu-param.h create mode 100644 target/xtensa/cpu-param.h (limited to 'include/exec') diff --git a/include/exec/cpu-defs.h b/include/exec/cpu-defs.h index 52d150aaf1..2694481769 100644 --- a/include/exec/cpu-defs.h +++ b/include/exec/cpu-defs.h @@ -34,8 +34,28 @@ #endif #include "exec/memattrs.h" +#include "cpu-param.h" + #ifndef TARGET_LONG_BITS -#error TARGET_LONG_BITS must be defined before including this header +# error TARGET_LONG_BITS must be defined in cpu-param.h +#endif +#ifndef NB_MMU_MODES +# error NB_MMU_MODES must be defined in cpu-param.h +#endif +#ifndef TARGET_PHYS_ADDR_SPACE_BITS +# error TARGET_PHYS_ADDR_SPACE_BITS must be defined in cpu-param.h +#endif +#ifndef TARGET_VIRT_ADDR_SPACE_BITS +# error TARGET_VIRT_ADDR_SPACE_BITS must be defined in cpu-param.h +#endif +#ifndef TARGET_PAGE_BITS +# ifdef TARGET_PAGE_BITS_VARY +# ifndef TARGET_PAGE_BITS_MIN +# error TARGET_PAGE_BITS_MIN must be defined in cpu-param.h +# endif +# else +# error TARGET_PAGE_BITS must be defined in cpu-param.h +# endif #endif #define TARGET_LONG_SIZE (TARGET_LONG_BITS / 8) diff --git a/target/alpha/cpu-param.h b/target/alpha/cpu-param.h new file mode 100644 index 0000000000..692aee27ca --- /dev/null +++ b/target/alpha/cpu-param.h @@ -0,0 +1,31 @@ +/* + * Alpha cpu parameters for qemu. + * + * Copyright (c) 2007 Jocelyn Mayer + * SPDX-License-Identifier: LGPL-2.0+ + */ + +#ifndef ALPHA_CPU_PARAM_H +#define ALPHA_CPU_PARAM_H 1 + +#define TARGET_LONG_BITS 64 +#define TARGET_PAGE_BITS 13 +#ifdef CONFIG_USER_ONLY +/* + * ??? The kernel likes to give addresses in high memory. If the host has + * more virtual address space than the guest, this can lead to impossible + * allocations. Honor the long-standing assumption that only kernel addrs + * are negative, but otherwise allow allocations anywhere. This could lead + * to tricky emulation problems for programs doing tagged addressing, but + * that's far fewer than encounter the impossible allocation problem. + */ +#define TARGET_PHYS_ADDR_SPACE_BITS 63 +#define TARGET_VIRT_ADDR_SPACE_BITS 63 +#else +/* ??? EV4 has 34 phys addr bits, EV5 has 40, EV6 has 44. */ +#define TARGET_PHYS_ADDR_SPACE_BITS 44 +#define TARGET_VIRT_ADDR_SPACE_BITS (30 + TARGET_PAGE_BITS) +#endif +#define NB_MMU_MODES 3 + +#endif diff --git a/target/alpha/cpu.h b/target/alpha/cpu.h index ba6bc31b15..dc1883f0f1 100644 --- a/target/alpha/cpu.h +++ b/target/alpha/cpu.h @@ -22,8 +22,8 @@ #include "qemu-common.h" #include "cpu-qom.h" +#include "exec/cpu-defs.h" -#define TARGET_LONG_BITS 64 #define ALIGNED_ONLY #define CPUArchState struct CPUAlphaState @@ -31,28 +31,9 @@ /* Alpha processors have a weak memory model */ #define TCG_GUEST_DEFAULT_MO (0) -#include "exec/cpu-defs.h" - #define ICACHE_LINE_SIZE 32 #define DCACHE_LINE_SIZE 32 -#define TARGET_PAGE_BITS 13 - -#ifdef CONFIG_USER_ONLY -/* ??? The kernel likes to give addresses in high memory. If the host has - more virtual address space than the guest, this can lead to impossible - allocations. Honor the long-standing assumption that only kernel addrs - are negative, but otherwise allow allocations anywhere. This could lead - to tricky emulation problems for programs doing tagged addressing, but - that's far fewer than encounter the impossible allocation problem. */ -#define TARGET_PHYS_ADDR_SPACE_BITS 63 -#define TARGET_VIRT_ADDR_SPACE_BITS 63 -#else -/* ??? EV4 has 34 phys addr bits, EV5 has 40, EV6 has 44. */ -#define TARGET_PHYS_ADDR_SPACE_BITS 44 -#define TARGET_VIRT_ADDR_SPACE_BITS (30 + TARGET_PAGE_BITS) -#endif - /* Alpha major type */ enum { ALPHA_EV3 = 1, @@ -217,8 +198,6 @@ enum { PALcode cheats and usees the KSEG mapping for its code+data rather than physical addresses. */ -#define NB_MMU_MODES 3 - #define MMU_MODE0_SUFFIX _kernel #define MMU_MODE1_SUFFIX _user #define MMU_KERNEL_IDX 0 diff --git a/target/arm/cpu-param.h b/target/arm/cpu-param.h new file mode 100644 index 0000000000..6e6948e960 --- /dev/null +++ b/target/arm/cpu-param.h @@ -0,0 +1,34 @@ +/* + * ARM cpu parameters for qemu. + * + * Copyright (c) 2003 Fabrice Bellard + * SPDX-License-Identifier: LGPL-2.0+ + */ + +#ifndef ARM_CPU_PARAM_H +#define ARM_CPU_PARAM_H 1 + +#ifdef TARGET_AARCH64 +# define TARGET_LONG_BITS 64 +# define TARGET_PHYS_ADDR_SPACE_BITS 48 +# define TARGET_VIRT_ADDR_SPACE_BITS 48 +#else +# define TARGET_LONG_BITS 32 +# define TARGET_PHYS_ADDR_SPACE_BITS 40 +# define TARGET_VIRT_ADDR_SPACE_BITS 32 +#endif + +#ifdef CONFIG_USER_ONLY +#define TARGET_PAGE_BITS 12 +#else +/* + * ARMv7 and later CPUs have 4K pages minimum, but ARMv5 and v6 + * have to support 1K tiny pages. + */ +# define TARGET_PAGE_BITS_VARY +# define TARGET_PAGE_BITS_MIN 10 +#endif + +#define NB_MMU_MODES 8 + +#endif diff --git a/target/arm/cpu.h b/target/arm/cpu.h index c34207611b..f8020b4823 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -22,23 +22,15 @@ #include "kvm-consts.h" #include "hw/registerfields.h" - -#if defined(TARGET_AARCH64) - /* AArch64 definitions */ -# define TARGET_LONG_BITS 64 -#else -# define TARGET_LONG_BITS 32 -#endif +#include "qemu-common.h" +#include "cpu-qom.h" +#include "exec/cpu-defs.h" /* ARM processors have a weak memory model */ #define TCG_GUEST_DEFAULT_MO (0) #define CPUArchState struct CPUARMState -#include "qemu-common.h" -#include "cpu-qom.h" -#include "exec/cpu-defs.h" - #define EXCP_UDEF 1 /* undefined instruction */ #define EXCP_SWI 2 /* software interrupt */ #define EXCP_PREFETCH_ABORT 3 @@ -114,7 +106,6 @@ enum { #define ARM_CPU_VIRQ 2 #define ARM_CPU_VFIQ 3 -#define NB_MMU_MODES 8 /* ARM-specific extra insn start words: * 1: Conditional execution bits * 2: Partial exception syndrome for data aborts @@ -2639,24 +2630,6 @@ bool write_cpustate_to_list(ARMCPU *cpu, bool kvm_sync); #define ARM_CPUID_TI915T 0x54029152 #define ARM_CPUID_TI925T 0x54029252 -#if defined(CONFIG_USER_ONLY) -#define TARGET_PAGE_BITS 12 -#else -/* ARMv7 and later CPUs have 4K pages minimum, but ARMv5 and v6 - * have to support 1K tiny pages. - */ -#define TARGET_PAGE_BITS_VARY -#define TARGET_PAGE_BITS_MIN 10 -#endif - -#if defined(TARGET_AARCH64) -# define TARGET_PHYS_ADDR_SPACE_BITS 48 -# define TARGET_VIRT_ADDR_SPACE_BITS 48 -#else -# define TARGET_PHYS_ADDR_SPACE_BITS 40 -# define TARGET_VIRT_ADDR_SPACE_BITS 32 -#endif - static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx, unsigned int target_el) { diff --git a/target/cris/cpu-param.h b/target/cris/cpu-param.h new file mode 100644 index 0000000000..36a3058761 --- /dev/null +++ b/target/cris/cpu-param.h @@ -0,0 +1,17 @@ +/* + * CRIS cpu parameters for qemu. + * + * Copyright (c) 2007 AXIS Communications AB + * SPDX-License-Identifier: LGPL-2.0+ + */ + +#ifndef CRIS_CPU_PARAM_H +#define CRIS_CPU_PARAM_H 1 + +#define TARGET_LONG_BITS 32 +#define TARGET_PAGE_BITS 13 +#define TARGET_PHYS_ADDR_SPACE_BITS 32 +#define TARGET_VIRT_ADDR_SPACE_BITS 32 +#define NB_MMU_MODES 2 + +#endif diff --git a/target/cris/cpu.h b/target/cris/cpu.h index 857de79e24..25408c2bf7 100644 --- a/target/cris/cpu.h +++ b/target/cris/cpu.h @@ -23,13 +23,10 @@ #include "qemu-common.h" #include "cpu-qom.h" - -#define TARGET_LONG_BITS 32 +#include "exec/cpu-defs.h" #define CPUArchState struct CPUCRISState -#include "exec/cpu-defs.h" - #define EXCP_NMI 1 #define EXCP_GURU 2 #define EXCP_BUSFAULT 3 @@ -105,8 +102,6 @@ #define CC_A 14 #define CC_P 15 -#define NB_MMU_MODES 2 - typedef struct { uint32_t hi; uint32_t lo; @@ -260,12 +255,8 @@ enum { }; /* CRIS uses 8k pages. */ -#define TARGET_PAGE_BITS 13 #define MMAP_SHIFT TARGET_PAGE_BITS -#define TARGET_PHYS_ADDR_SPACE_BITS 32 -#define TARGET_VIRT_ADDR_SPACE_BITS 32 - #define CRIS_CPU_TYPE_SUFFIX "-" TYPE_CRIS_CPU #define CRIS_CPU_TYPE_NAME(name) (name CRIS_CPU_TYPE_SUFFIX) #define CPU_RESOLVING_TYPE TYPE_CRIS_CPU diff --git a/target/hppa/cpu-param.h b/target/hppa/cpu-param.h new file mode 100644 index 0000000000..a97d1428df --- /dev/null +++ b/target/hppa/cpu-param.h @@ -0,0 +1,34 @@ +/* + * PA-RISC cpu parameters for qemu. + * + * Copyright (c) 2016 Richard Henderson + * SPDX-License-Identifier: LGPL-2.0+ + */ + +#ifndef HPPA_CPU_PARAM_H +#define HPPA_CPU_PARAM_H 1 + +#ifdef TARGET_HPPA64 +# define TARGET_LONG_BITS 64 +# define TARGET_REGISTER_BITS 64 +# define TARGET_VIRT_ADDR_SPACE_BITS 64 +# define TARGET_PHYS_ADDR_SPACE_BITS 64 +#elif defined(CONFIG_USER_ONLY) +# define TARGET_LONG_BITS 32 +# define TARGET_REGISTER_BITS 32 +# define TARGET_VIRT_ADDR_SPACE_BITS 32 +# define TARGET_PHYS_ADDR_SPACE_BITS 32 +#else +/* + * In order to form the GVA from space:offset, + * we need a 64-bit virtual address space. + */ +# define TARGET_LONG_BITS 64 +# define TARGET_REGISTER_BITS 32 +# define TARGET_VIRT_ADDR_SPACE_BITS 64 +# define TARGET_PHYS_ADDR_SPACE_BITS 32 +#endif +#define TARGET_PAGE_BITS 12 +#define NB_MMU_MODES 5 + +#endif diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h index c1e0215e66..fb527eba88 100644 --- a/target/hppa/cpu.h +++ b/target/hppa/cpu.h @@ -22,25 +22,8 @@ #include "qemu-common.h" #include "cpu-qom.h" +#include "exec/cpu-defs.h" -#ifdef TARGET_HPPA64 -#define TARGET_LONG_BITS 64 -#define TARGET_VIRT_ADDR_SPACE_BITS 64 -#define TARGET_REGISTER_BITS 64 -#define TARGET_PHYS_ADDR_SPACE_BITS 64 -#elif defined(CONFIG_USER_ONLY) -#define TARGET_LONG_BITS 32 -#define TARGET_VIRT_ADDR_SPACE_BITS 32 -#define TARGET_REGISTER_BITS 32 -#define TARGET_PHYS_ADDR_SPACE_BITS 32 -#else -/* In order to form the GVA from space:offset, - we need a 64-bit virtual address space. */ -#define TARGET_LONG_BITS 64 -#define TARGET_VIRT_ADDR_SPACE_BITS 64 -#define TARGET_REGISTER_BITS 32 -#define TARGET_PHYS_ADDR_SPACE_BITS 32 -#endif /* PA-RISC 1.x processors have a strong memory model. */ /* ??? While we do not yet implement PA-RISC 2.0, those processors have @@ -50,12 +33,7 @@ #define CPUArchState struct CPUHPPAState -#include "exec/cpu-defs.h" - -#define TARGET_PAGE_BITS 12 - #define ALIGNED_ONLY -#define NB_MMU_MODES 5 #define MMU_KERNEL_IDX 0 #define MMU_USER_IDX 3 #define MMU_PHYS_IDX 4 diff --git a/target/i386/cpu-param.h b/target/i386/cpu-param.h new file mode 100644 index 0000000000..57abc64c0d --- /dev/null +++ b/target/i386/cpu-param.h @@ -0,0 +1,28 @@ +/* + * i386 cpu parameters for qemu. + * + * Copyright (c) 2003 Fabrice Bellard + * SPDX-License-Identifier: LGPL-2.0+ + */ + +#ifndef I386_CPU_PARAM_H +#define I386_CPU_PARAM_H 1 + +#ifdef TARGET_X86_64 +# define TARGET_LONG_BITS 64 +# define TARGET_PHYS_ADDR_SPACE_BITS 52 +/* + * ??? This is really 48 bits, sign-extended, but the only thing + * accessible to userland with bit 48 set is the VSYSCALL, and that + * is handled via other mechanisms. + */ +# define TARGET_VIRT_ADDR_SPACE_BITS 47 +#else +# define TARGET_LONG_BITS 32 +# define TARGET_PHYS_ADDR_SPACE_BITS 36 +# define TARGET_VIRT_ADDR_SPACE_BITS 32 +#endif +#define TARGET_PAGE_BITS 12 +#define NB_MMU_MODES 3 + +#endif diff --git a/target/i386/cpu.h b/target/i386/cpu.h index bd06523a53..36f5095768 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -24,13 +24,6 @@ #include "qemu-common.h" #include "cpu-qom.h" #include "hyperv-proto.h" - -#ifdef TARGET_X86_64 -#define TARGET_LONG_BITS 64 -#else -#define TARGET_LONG_BITS 32 -#endif - #include "exec/cpu-defs.h" /* The x86 has a strong memory model with some store-after-load re-ordering */ @@ -956,7 +949,6 @@ typedef struct { #define MAX_FIXED_COUNTERS 3 #define MAX_GP_COUNTERS (MSR_IA32_PERF_STATUS - MSR_P6_EVNTSEL0) -#define NB_MMU_MODES 3 #define TARGET_INSN_START_EXTRA_WORDS 1 #define NB_OPMASK_REGS 8 @@ -1695,19 +1687,6 @@ void cpu_x86_update_dr7(CPUX86State *env, uint32_t new_dr7); /* hw/pc.c */ uint64_t cpu_get_tsc(CPUX86State *env); -#define TARGET_PAGE_BITS 12 - -#ifdef TARGET_X86_64 -#define TARGET_PHYS_ADDR_SPACE_BITS 52 -/* ??? This is really 48 bits, sign-extended, but the only thing - accessible to userland with bit 48 set is the VSYSCALL, and that - is handled via other mechanisms. */ -#define TARGET_VIRT_ADDR_SPACE_BITS 47 -#else -#define TARGET_PHYS_ADDR_SPACE_BITS 36 -#define TARGET_VIRT_ADDR_SPACE_BITS 32 -#endif - /* XXX: This value should match the one returned by CPUID * and in exec.c */ # if defined(TARGET_X86_64) diff --git a/target/lm32/cpu-param.h b/target/lm32/cpu-param.h new file mode 100644 index 0000000000..d89574ad19 --- /dev/null +++ b/target/lm32/cpu-param.h @@ -0,0 +1,17 @@ +/* + * LatticeMico32 cpu parameters for qemu. + * + * Copyright (c) 2010 Michael Walle + * SPDX-License-Identifier: LGPL-2.0+ + */ + +#ifndef LM32_CPU_PARAM_H +#define LM32_CPU_PARAM_H 1 + +#define TARGET_LONG_BITS 32 +#define TARGET_PAGE_BITS 12 +#define TARGET_PHYS_ADDR_SPACE_BITS 32 +#define TARGET_VIRT_ADDR_SPACE_BITS 32 +#define NB_MMU_MODES 1 + +#endif diff --git a/target/lm32/cpu.h b/target/lm32/cpu.h index d224d4426e..e75110c4e0 100644 --- a/target/lm32/cpu.h +++ b/target/lm32/cpu.h @@ -20,26 +20,20 @@ #ifndef LM32_CPU_H #define LM32_CPU_H -#define TARGET_LONG_BITS 32 - -#define CPUArchState struct CPULM32State - #include "qemu-common.h" #include "cpu-qom.h" #include "exec/cpu-defs.h" + +#define CPUArchState struct CPULM32State + struct CPULM32State; typedef struct CPULM32State CPULM32State; -#define NB_MMU_MODES 1 -#define TARGET_PAGE_BITS 12 static inline int cpu_mmu_index(CPULM32State *env, bool ifetch) { return 0; } -#define TARGET_PHYS_ADDR_SPACE_BITS 32 -#define TARGET_VIRT_ADDR_SPACE_BITS 32 - /* Exceptions indices */ enum { EXCP_RESET = 0, diff --git a/target/m68k/cpu-param.h b/target/m68k/cpu-param.h new file mode 100644 index 0000000000..06556dfbf3 --- /dev/null +++ b/target/m68k/cpu-param.h @@ -0,0 +1,22 @@ +/* + * m68k cpu parameters for qemu. + * + * Copyright (c) 2005-2007 CodeSourcery + * SPDX-License-Identifier: LGPL-2.0+ + */ + +#ifndef M68K_CPU_PARAM_H +#define M68K_CPU_PARAM_H 1 + +#define TARGET_LONG_BITS 32 +/* + * Coldfire Linux uses 8k pages + * and m68k linux uses 4k pages + * use the smallest one + */ +#define TARGET_PAGE_BITS 12 +#define TARGET_PHYS_ADDR_SPACE_BITS 32 +#define TARGET_VIRT_ADDR_SPACE_BITS 32 +#define NB_MMU_MODES 2 + +#endif diff --git a/target/m68k/cpu.h b/target/m68k/cpu.h index 9deff9e234..e99c102302 100644 --- a/target/m68k/cpu.h +++ b/target/m68k/cpu.h @@ -21,14 +21,12 @@ #ifndef M68K_CPU_H #define M68K_CPU_H -#define TARGET_LONG_BITS 32 - -#define CPUArchState struct CPUM68KState - #include "qemu-common.h" #include "exec/cpu-defs.h" #include "cpu-qom.h" +#define CPUArchState struct CPUM68KState + #define OS_BYTE 0 #define OS_WORD 1 #define OS_LONG 2 @@ -82,7 +80,6 @@ #define M68K_MAX_TTR 2 #define TTR(type, index) ttr[((type & ACCESS_CODE) == ACCESS_CODE) * 2 + index] -#define NB_MMU_MODES 2 #define TARGET_INSN_START_EXTRA_WORDS 1 typedef CPU_LDoubleU FPReg; @@ -502,12 +499,6 @@ void m68k_cpu_list(void); void register_m68k_insns (CPUM68KState *env); -/* Coldfire Linux uses 8k pages - * and m68k linux uses 4k pages - * use the smallest one - */ -#define TARGET_PAGE_BITS 12 - enum { /* 1 bit to define user level / supervisor access */ ACCESS_SUPER = 0x01, @@ -522,9 +513,6 @@ enum { ACCESS_DATA = 0x20, /* Data load/store access */ }; -#define TARGET_PHYS_ADDR_SPACE_BITS 32 -#define TARGET_VIRT_ADDR_SPACE_BITS 32 - #define M68K_CPU_TYPE_SUFFIX "-" TYPE_M68K_CPU #define M68K_CPU_TYPE_NAME(model) model M68K_CPU_TYPE_SUFFIX #define CPU_RESOLVING_TYPE TYPE_M68K_CPU diff --git a/target/microblaze/cpu-param.h b/target/microblaze/cpu-param.h new file mode 100644 index 0000000000..4abbc62d50 --- /dev/null +++ b/target/microblaze/cpu-param.h @@ -0,0 +1,18 @@ +/* + * MicroBlaze cpu parameters for qemu. + * + * Copyright (c) 2009 Edgar E. Iglesias + * SPDX-License-Identifier: LGPL-2.0+ + */ + +#ifndef MICROBLAZE_CPU_PARAM_H +#define MICROBLAZE_CPU_PARAM_H 1 + +#define TARGET_LONG_BITS 64 +#define TARGET_PHYS_ADDR_SPACE_BITS 64 +#define TARGET_VIRT_ADDR_SPACE_BITS 64 +/* FIXME: MB uses variable pages down to 1K but linux only uses 4k. */ +#define TARGET_PAGE_BITS 12 +#define NB_MMU_MODES 3 + +#endif diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h index 7a9fb8f4aa..b8db8ca9a3 100644 --- a/target/microblaze/cpu.h +++ b/target/microblaze/cpu.h @@ -22,13 +22,11 @@ #include "qemu-common.h" #include "cpu-qom.h" - -#define TARGET_LONG_BITS 64 +#include "exec/cpu-defs.h" +#include "fpu/softfloat-types.h" #define CPUArchState struct CPUMBState -#include "exec/cpu-defs.h" -#include "fpu/softfloat-types.h" struct CPUMBState; typedef struct CPUMBState CPUMBState; #if !defined(CONFIG_USER_ONLY) @@ -228,8 +226,6 @@ typedef struct CPUMBState CPUMBState; #define CC_NE 1 #define CC_EQ 0 -#define NB_MMU_MODES 3 - #define STREAM_EXCEPTION (1 << 0) #define STREAM_ATOMIC (1 << 1) #define STREAM_TEST (1 << 2) @@ -340,12 +336,6 @@ void mb_tcg_init(void); int cpu_mb_signal_handler(int host_signum, void *pinfo, void *puc); -/* FIXME: MB uses variable pages down to 1K but linux only uses 4k. */ -#define TARGET_PAGE_BITS 12 - -#define TARGET_PHYS_ADDR_SPACE_BITS 64 -#define TARGET_VIRT_ADDR_SPACE_BITS 64 - #define CPU_RESOLVING_TYPE TYPE_MICROBLAZE_CPU #define cpu_signal_handler cpu_mb_signal_handler diff --git a/target/mips/cpu-param.h b/target/mips/cpu-param.h new file mode 100644 index 0000000000..308660d29d --- /dev/null +++ b/target/mips/cpu-param.h @@ -0,0 +1,29 @@ +/* + * MIPS cpu parameters for qemu. + * + * SPDX-License-Identifier: LGPL-2.0+ + */ + +#ifndef MIPS_CPU_PARAM_H +#define MIPS_CPU_PARAM_H 1 + +#ifdef TARGET_MIPS64 +# define TARGET_LONG_BITS 64 +#else +# define TARGET_LONG_BITS 32 +#endif +#ifdef TARGET_MIPS64 +#define TARGET_PHYS_ADDR_SPACE_BITS 48 +#define TARGET_VIRT_ADDR_SPACE_BITS 48 +#else +#define TARGET_PHYS_ADDR_SPACE_BITS 40 +# ifdef CONFIG_USER_ONLY +# define TARGET_VIRT_ADDR_SPACE_BITS 31 +# else +# define TARGET_VIRT_ADDR_SPACE_BITS 32 +#endif +#endif +#define TARGET_PAGE_BITS 12 +#define NB_MMU_MODES 4 + +#endif diff --git a/target/mips/cpu.h b/target/mips/cpu.h index 06a8ed4748..34e7aec4d0 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -7,9 +7,9 @@ #include "qemu-common.h" #include "cpu-qom.h" -#include "mips-defs.h" #include "exec/cpu-defs.h" #include "fpu/softfloat.h" +#include "mips-defs.h" #define TCG_GUEST_DEFAULT_MO (0) @@ -103,7 +103,6 @@ struct CPUMIPSFPUContext { #define FP_UNIMPLEMENTED 32 }; -#define NB_MMU_MODES 4 #define TARGET_INSN_START_EXTRA_WORDS 2 typedef struct CPUMIPSMVPContext CPUMIPSMVPContext; diff --git a/target/mips/mips-defs.h b/target/mips/mips-defs.h index dbdb4b2b2d..bbf056a548 100644 --- a/target/mips/mips-defs.h +++ b/target/mips/mips-defs.h @@ -5,23 +5,8 @@ //#define USE_HOST_FLOAT_REGS /* Real pages are variable size... */ -#define TARGET_PAGE_BITS 12 #define MIPS_TLB_MAX 128 -#if defined(TARGET_MIPS64) -#define TARGET_LONG_BITS 64 -#define TARGET_PHYS_ADDR_SPACE_BITS 48 -#define TARGET_VIRT_ADDR_SPACE_BITS 48 -#else -#define TARGET_LONG_BITS 32 -#define TARGET_PHYS_ADDR_SPACE_BITS 40 -# ifdef CONFIG_USER_ONLY -# define TARGET_VIRT_ADDR_SPACE_BITS 31 -# else -# define TARGET_VIRT_ADDR_SPACE_BITS 32 -#endif -#endif - /* * bit definitions for insn_flags (ISAs/ASEs flags) * ------------------------------------------------ diff --git a/target/moxie/cpu-param.h b/target/moxie/cpu-param.h new file mode 100644 index 0000000000..9a40ef525c --- /dev/null +++ b/target/moxie/cpu-param.h @@ -0,0 +1,17 @@ +/* + * Moxie cpu parameters for qemu. + * + * Copyright (c) 2008, 2010, 2013 Anthony Green + * SPDX-License-Identifier: LGPL-2.1+ + */ + +#ifndef MOXIE_CPU_PARAM_H +#define MOXIE_CPU_PARAM_H 1 + +#define TARGET_LONG_BITS 32 +#define TARGET_PAGE_BITS 12 /* 4k */ +#define TARGET_PHYS_ADDR_SPACE_BITS 32 +#define TARGET_VIRT_ADDR_SPACE_BITS 32 +#define NB_MMU_MODES 1 + +#endif diff --git a/target/moxie/cpu.h b/target/moxie/cpu.h index a63a96bc05..7164dd7f5f 100644 --- a/target/moxie/cpu.h +++ b/target/moxie/cpu.h @@ -21,8 +21,7 @@ #define MOXIE_CPU_H #include "qemu-common.h" - -#define TARGET_LONG_BITS 32 +#include "exec/cpu-defs.h" #define CPUArchState struct CPUMoxieState @@ -33,15 +32,6 @@ #define MOXIE_EX_MMU_MISS 4 #define MOXIE_EX_BREAK 16 -#include "exec/cpu-defs.h" - -#define TARGET_PAGE_BITS 12 /* 4k */ - -#define TARGET_PHYS_ADDR_SPACE_BITS 32 -#define TARGET_VIRT_ADDR_SPACE_BITS 32 - -#define NB_MMU_MODES 1 - typedef struct CPUMoxieState { uint32_t flags; /* general execution flags */ diff --git a/target/nios2/cpu-param.h b/target/nios2/cpu-param.h new file mode 100644 index 0000000000..38bedbfd61 --- /dev/null +++ b/target/nios2/cpu-param.h @@ -0,0 +1,21 @@ +/* + * Altera Nios II cpu parameters for qemu. + * + * Copyright (c) 2012 Chris Wulff + * SPDX-License-Identifier: LGPL-2.1+ + */ + +#ifndef NIOS2_CPU_PARAM_H +#define NIOS2_CPU_PARAM_H 1 + +#define TARGET_LONG_BITS 32 +#define TARGET_PAGE_BITS 12 +#define TARGET_PHYS_ADDR_SPACE_BITS 32 +#ifdef CONFIG_USER_ONLY +# define TARGET_VIRT_ADDR_SPACE_BITS 31 +#else +# define TARGET_VIRT_ADDR_SPACE_BITS 32 +#endif +#define NB_MMU_MODES 2 + +#endif diff --git a/target/nios2/cpu.h b/target/nios2/cpu.h index 35d3886dc2..c4ccea9cf0 100644 --- a/target/nios2/cpu.h +++ b/target/nios2/cpu.h @@ -22,13 +22,11 @@ #define NIOS2_CPU_H #include "qemu-common.h" - -#define TARGET_LONG_BITS 32 +#include "exec/cpu-defs.h" +#include "qom/cpu.h" #define CPUArchState struct CPUNios2State -#include "exec/cpu-defs.h" -#include "qom/cpu.h" struct CPUNios2State; typedef struct CPUNios2State CPUNios2State; #if !defined(CONFIG_USER_ONLY) @@ -164,8 +162,6 @@ typedef struct Nios2CPUClass { #define CPU_INTERRUPT_NMI CPU_INTERRUPT_TGT_EXT_3 -#define NB_MMU_MODES 2 - struct CPUNios2State { uint32_t regs[NUM_CORE_REGS]; @@ -225,13 +221,6 @@ void nios2_check_interrupts(CPUNios2State *env); void do_nios2_semihosting(CPUNios2State *env); -#define TARGET_PHYS_ADDR_SPACE_BITS 32 -#ifdef CONFIG_USER_ONLY -# define TARGET_VIRT_ADDR_SPACE_BITS 31 -#else -# define TARGET_VIRT_ADDR_SPACE_BITS 32 -#endif - #define CPU_RESOLVING_TYPE TYPE_NIOS2_CPU #define cpu_gen_code cpu_nios2_gen_code @@ -239,8 +228,6 @@ void do_nios2_semihosting(CPUNios2State *env); #define CPU_SAVE_VERSION 1 -#define TARGET_PAGE_BITS 12 - /* MMU modes definitions */ #define MMU_MODE0_SUFFIX _kernel #define MMU_MODE1_SUFFIX _user diff --git a/target/openrisc/cpu-param.h b/target/openrisc/cpu-param.h new file mode 100644 index 0000000000..06ee64d171 --- /dev/null +++ b/target/openrisc/cpu-param.h @@ -0,0 +1,17 @@ +/* + * OpenRISC cpu parameters for qemu. + * + * Copyright (c) 2011-2012 Jia Liu + * SPDX-License-Identifier: LGPL-2.0+ + */ + +#ifndef OPENRISC_CPU_PARAM_H +#define OPENRISC_CPU_PARAM_H 1 + +#define TARGET_LONG_BITS 32 +#define TARGET_PAGE_BITS 13 +#define TARGET_PHYS_ADDR_SPACE_BITS 32 +#define TARGET_VIRT_ADDR_SPACE_BITS 32 +#define NB_MMU_MODES 3 + +#endif diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h index 9473d94d0c..3727efabf3 100644 --- a/target/openrisc/cpu.h +++ b/target/openrisc/cpu.h @@ -20,17 +20,15 @@ #ifndef OPENRISC_CPU_H #define OPENRISC_CPU_H -#define TARGET_LONG_BITS 32 +#include "qemu-common.h" +#include "exec/cpu-defs.h" +#include "qom/cpu.h" #define CPUArchState struct CPUOpenRISCState /* cpu_openrisc_map_address_* in CPUOpenRISCTLBContext need this decl. */ struct OpenRISCCPU; -#include "qemu-common.h" -#include "exec/cpu-defs.h" -#include "qom/cpu.h" - #define TYPE_OPENRISC_CPU "or1k-cpu" #define OPENRISC_CPU_CLASS(klass) \ @@ -56,7 +54,6 @@ typedef struct OpenRISCCPUClass { void (*parent_reset)(CPUState *cpu); } OpenRISCCPUClass; -#define NB_MMU_MODES 3 #define TARGET_INSN_START_EXTRA_WORDS 1 enum { @@ -65,11 +62,6 @@ enum { MMU_USER_IDX = 2, }; -#define TARGET_PAGE_BITS 13 - -#define TARGET_PHYS_ADDR_SPACE_BITS 32 -#define TARGET_VIRT_ADDR_SPACE_BITS 32 - #define SET_FP_CAUSE(reg, v) do {\ (reg) = ((reg) & ~(0x3f << 12)) | \ ((v & 0x3f) << 12);\ diff --git a/target/ppc/cpu-param.h b/target/ppc/cpu-param.h new file mode 100644 index 0000000000..37b458d33d --- /dev/null +++ b/target/ppc/cpu-param.h @@ -0,0 +1,37 @@ +/* + * PowerPC cpu parameters for qemu. + * + * Copyright (c) 2007 Jocelyn Mayer + * SPDX-License-Identifier: LGPL-2.0+ + */ + +#ifndef PPC_CPU_PARAM_H +#define PPC_CPU_PARAM_H 1 + +#ifdef TARGET_PPC64 +# define TARGET_LONG_BITS 64 +/* + * Note that the official physical address space bits is 62-M where M + * is implementation dependent. I've not looked up M for the set of + * cpus we emulate at the system level. + */ +#define TARGET_PHYS_ADDR_SPACE_BITS 62 +/* + * Note that the PPC environment architecture talks about 80 bit virtual + * addresses, with segmentation. Obviously that's not all visible to a + * single process, which is all we're concerned with here. + */ +# ifdef TARGET_ABI32 +# define TARGET_VIRT_ADDR_SPACE_BITS 32 +# else +# define TARGET_VIRT_ADDR_SPACE_BITS 64 +# endif +#else +# define TARGET_LONG_BITS 32 +# define TARGET_PHYS_ADDR_SPACE_BITS 36 +# define TARGET_VIRT_ADDR_SPACE_BITS 32 +#endif +#define TARGET_PAGE_BITS 12 +#define NB_MMU_MODES 10 + +#endif diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index d7f23ad5e0..02ca453df3 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -22,53 +22,20 @@ #include "qemu-common.h" #include "qemu/int128.h" +#include "exec/cpu-defs.h" +#include "cpu-qom.h" +#include "exec/cpu-defs.h" +#include "cpu-qom.h" /* #define PPC_EMULATE_32BITS_HYPV */ -#if defined(TARGET_PPC64) -/* PowerPC 64 definitions */ -#define TARGET_LONG_BITS 64 -#define TARGET_PAGE_BITS 12 - #define TCG_GUEST_DEFAULT_MO 0 -/* - * Note that the official physical address space bits is 62-M where M - * is implementation dependent. I've not looked up M for the set of - * cpus we emulate at the system level. - */ -#define TARGET_PHYS_ADDR_SPACE_BITS 62 - -/* - * Note that the PPC environment architecture talks about 80 bit - * virtual addresses, with segmentation. Obviously that's not all - * visible to a single process, which is all we're concerned with - * here. - */ -#ifdef TARGET_ABI32 -# define TARGET_VIRT_ADDR_SPACE_BITS 32 -#else -# define TARGET_VIRT_ADDR_SPACE_BITS 64 -#endif - #define TARGET_PAGE_BITS_64K 16 #define TARGET_PAGE_BITS_16M 24 -#else /* defined(TARGET_PPC64) */ -/* PowerPC 32 definitions */ -#define TARGET_LONG_BITS 32 -#define TARGET_PAGE_BITS 12 - -#define TARGET_PHYS_ADDR_SPACE_BITS 36 -#define TARGET_VIRT_ADDR_SPACE_BITS 32 - -#endif /* defined(TARGET_PPC64) */ - #define CPUArchState struct CPUPPCState -#include "exec/cpu-defs.h" -#include "cpu-qom.h" - #if defined(TARGET_PPC64) #define PPC_ELF_MACHINE EM_PPC64 #else @@ -974,7 +941,6 @@ struct ppc_radix_page_info { * + real/paged mode combinations. The other two modes are for * external PID load/store. */ -#define NB_MMU_MODES 10 #define MMU_MODE8_SUFFIX _epl #define MMU_MODE9_SUFFIX _eps #define PPC_TLB_EPID_LOAD 8 diff --git a/target/riscv/cpu-param.h b/target/riscv/cpu-param.h new file mode 100644 index 0000000000..664fc1d371 --- /dev/null +++ b/target/riscv/cpu-param.h @@ -0,0 +1,23 @@ +/* + * RISC-V cpu parameters for qemu. + * + * Copyright (c) 2017-2018 SiFive, Inc. + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef RISCV_CPU_PARAM_H +#define RISCV_CPU_PARAM_H 1 + +#if defined(TARGET_RISCV64) +# define TARGET_LONG_BITS 64 +# define TARGET_PHYS_ADDR_SPACE_BITS 56 /* 44-bit PPN */ +# define TARGET_VIRT_ADDR_SPACE_BITS 48 /* sv48 */ +#elif defined(TARGET_RISCV32) +# define TARGET_LONG_BITS 32 +# define TARGET_PHYS_ADDR_SPACE_BITS 34 /* 22-bit PPN */ +# define TARGET_VIRT_ADDR_SPACE_BITS 32 /* sv32 */ +#endif +#define TARGET_PAGE_BITS 12 /* 4 KiB Pages */ +#define NB_MMU_MODES 4 + +#endif diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 74e726c1c9..bc517dbad8 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -20,27 +20,15 @@ #ifndef RISCV_CPU_H #define RISCV_CPU_H -/* QEMU addressing/paging config */ -#define TARGET_PAGE_BITS 12 /* 4 KiB Pages */ -#if defined(TARGET_RISCV64) -#define TARGET_LONG_BITS 64 -#define TARGET_PHYS_ADDR_SPACE_BITS 56 /* 44-bit PPN */ -#define TARGET_VIRT_ADDR_SPACE_BITS 48 /* sv48 */ -#elif defined(TARGET_RISCV32) -#define TARGET_LONG_BITS 32 -#define TARGET_PHYS_ADDR_SPACE_BITS 34 /* 22-bit PPN */ -#define TARGET_VIRT_ADDR_SPACE_BITS 32 /* sv32 */ -#endif - -#define TCG_GUEST_DEFAULT_MO 0 - -#define CPUArchState struct CPURISCVState - #include "qemu-common.h" #include "qom/cpu.h" #include "exec/cpu-defs.h" #include "fpu/softfloat.h" +#define TCG_GUEST_DEFAULT_MO 0 + +#define CPUArchState struct CPURISCVState + #define TYPE_RISCV_CPU "riscv-cpu" #define RISCV_CPU_TYPE_SUFFIX "-" TYPE_RISCV_CPU @@ -98,7 +86,6 @@ enum { #define TRANSLATE_FAIL 1 #define TRANSLATE_SUCCESS 0 -#define NB_MMU_MODES 4 #define MMU_USER_IDX 3 #define MAX_RISCV_PMPS (16) diff --git a/target/s390x/cpu-param.h b/target/s390x/cpu-param.h new file mode 100644 index 0000000000..472db648d7 --- /dev/null +++ b/target/s390x/cpu-param.h @@ -0,0 +1,17 @@ +/* + * S/390 cpu parameters for qemu. + * + * Copyright (c) 2009 Ulrich Hecht + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef S390_CPU_PARAM_H +#define S390_CPU_PARAM_H 1 + +#define TARGET_LONG_BITS 64 +#define TARGET_PAGE_BITS 12 +#define TARGET_PHYS_ADDR_SPACE_BITS 64 +#define TARGET_VIRT_ADDR_SPACE_BITS 64 +#define NB_MMU_MODES 4 + +#endif diff --git a/target/s390x/cpu.h b/target/s390x/cpu.h index 4fc08a2c88..1577252e72 100644 --- a/target/s390x/cpu.h +++ b/target/s390x/cpu.h @@ -24,26 +24,17 @@ #include "qemu-common.h" #include "cpu-qom.h" #include "cpu_models.h" - -#define TARGET_LONG_BITS 64 +#include "exec/cpu-defs.h" #define ELF_MACHINE_UNAME "S390X" #define CPUArchState struct CPUS390XState -#include "exec/cpu-defs.h" - /* The z/Architecture has a strong memory model with some store-after-load re-ordering */ #define TCG_GUEST_DEFAULT_MO (TCG_MO_ALL & ~TCG_MO_ST_LD) -#define TARGET_PAGE_BITS 12 - -#define TARGET_PHYS_ADDR_SPACE_BITS 64 -#define TARGET_VIRT_ADDR_SPACE_BITS 64 - #include "exec/cpu-all.h" -#define NB_MMU_MODES 4 #define TARGET_INSN_START_EXTRA_WORDS 1 #define MMU_MODE0_SUFFIX _primary diff --git a/target/sh4/cpu-param.h b/target/sh4/cpu-param.h new file mode 100644 index 0000000000..81ace3503b --- /dev/null +++ b/target/sh4/cpu-param.h @@ -0,0 +1,21 @@ +/* + * SH4 cpu parameters for qemu. + * + * Copyright (c) 2005 Samuel Tardieu + * SPDX-License-Identifier: LGPL-2.0+ + */ + +#ifndef SH4_CPU_PARAM_H +#define SH4_CPU_PARAM_H 1 + +#define TARGET_LONG_BITS 32 +#define TARGET_PAGE_BITS 12 /* 4k */ +#define TARGET_PHYS_ADDR_SPACE_BITS 32 +#ifdef CONFIG_USER_ONLY +# define TARGET_VIRT_ADDR_SPACE_BITS 31 +#else +# define TARGET_VIRT_ADDR_SPACE_BITS 32 +#endif +#define NB_MMU_MODES 2 + +#endif diff --git a/target/sh4/cpu.h b/target/sh4/cpu.h index 547194aac7..7af6ff5d57 100644 --- a/target/sh4/cpu.h +++ b/target/sh4/cpu.h @@ -22,8 +22,8 @@ #include "qemu-common.h" #include "cpu-qom.h" +#include "exec/cpu-defs.h" -#define TARGET_LONG_BITS 32 #define ALIGNED_ONLY /* CPU Subtypes */ @@ -38,17 +38,6 @@ #define CPUArchState struct CPUSH4State -#include "exec/cpu-defs.h" - -#define TARGET_PAGE_BITS 12 /* 4k XXXXX */ - -#define TARGET_PHYS_ADDR_SPACE_BITS 32 -#ifdef CONFIG_USER_ONLY -# define TARGET_VIRT_ADDR_SPACE_BITS 31 -#else -# define TARGET_VIRT_ADDR_SPACE_BITS 32 -#endif - #define SR_MD 30 #define SR_RB 29 #define SR_BL 28 @@ -132,7 +121,6 @@ typedef struct tlb_t { #define UTLB_SIZE 64 #define ITLB_SIZE 4 -#define NB_MMU_MODES 2 #define TARGET_INSN_START_EXTRA_WORDS 1 enum sh_features { diff --git a/target/sparc/cpu-param.h b/target/sparc/cpu-param.h new file mode 100644 index 0000000000..4746d89411 --- /dev/null +++ b/target/sparc/cpu-param.h @@ -0,0 +1,28 @@ +/* + * Sparc cpu parameters for qemu. + * + * SPDX-License-Identifier: LGPL-2.0+ + */ + +#ifndef SPARC_CPU_PARAM_H +#define SPARC_CPU_PARAM_H 1 + +#ifdef TARGET_SPARC64 +# define TARGET_LONG_BITS 64 +# define TARGET_PAGE_BITS 13 /* 8k */ +# define TARGET_PHYS_ADDR_SPACE_BITS 41 +# ifdef TARGET_ABI32 +# define TARGET_VIRT_ADDR_SPACE_BITS 32 +# else +# define TARGET_VIRT_ADDR_SPACE_BITS 44 +# endif +# define NB_MMU_MODES 6 +#else +# define TARGET_LONG_BITS 32 +# define TARGET_PAGE_BITS 12 /* 4k */ +# define TARGET_PHYS_ADDR_SPACE_BITS 36 +# define TARGET_VIRT_ADDR_SPACE_BITS 32 +# define NB_MMU_MODES 3 +#endif + +#endif diff --git a/target/sparc/cpu.h b/target/sparc/cpu.h index f31e8535df..bcfdf513cf 100644 --- a/target/sparc/cpu.h +++ b/target/sparc/cpu.h @@ -4,31 +4,18 @@ #include "qemu-common.h" #include "qemu/bswap.h" #include "cpu-qom.h" +#include "exec/cpu-defs.h" #define ALIGNED_ONLY #if !defined(TARGET_SPARC64) -#define TARGET_LONG_BITS 32 #define TARGET_DPREGS 16 -#define TARGET_PAGE_BITS 12 /* 4k */ -#define TARGET_PHYS_ADDR_SPACE_BITS 36 -#define TARGET_VIRT_ADDR_SPACE_BITS 32 #else -#define TARGET_LONG_BITS 64 #define TARGET_DPREGS 32 -#define TARGET_PAGE_BITS 13 /* 8k */ -#define TARGET_PHYS_ADDR_SPACE_BITS 41 -# ifdef TARGET_ABI32 -# define TARGET_VIRT_ADDR_SPACE_BITS 32 -# else -# define TARGET_VIRT_ADDR_SPACE_BITS 44 -# endif #endif #define CPUArchState struct CPUSPARCState -#include "exec/cpu-defs.h" - /*#define EXCP_INTERRUPT 0x100*/ /* trap definitions */ @@ -225,10 +212,7 @@ enum { #define MIN_NWINDOWS 3 #define MAX_NWINDOWS 32 -#if !defined(TARGET_SPARC64) -#define NB_MMU_MODES 3 -#else -#define NB_MMU_MODES 6 +#ifdef TARGET_SPARC64 typedef struct trap_state { uint64_t tpc; uint64_t tnpc; diff --git a/target/tilegx/cpu-param.h b/target/tilegx/cpu-param.h new file mode 100644 index 0000000000..80a341cbb7 --- /dev/null +++ b/target/tilegx/cpu-param.h @@ -0,0 +1,17 @@ +/* + * TILE-Gx cpu parameters for qemu. + * + * Copyright (c) 2015 Chen Gang + * SPDX-License-Identifier: LGPL-2.0+ + */ + +#ifndef TILEGX_CPU_PARAM_H +#define TILEGX_CPU_PARAM_H 1 + +#define TARGET_LONG_BITS 64 +#define TARGET_PAGE_BITS 16 /* TILE-Gx uses 64KB page size */ +#define TARGET_PHYS_ADDR_SPACE_BITS 42 +#define TARGET_VIRT_ADDR_SPACE_BITS 64 +#define NB_MMU_MODES 1 + +#endif diff --git a/target/tilegx/cpu.h b/target/tilegx/cpu.h index 238f8d36d7..429a6c6b43 100644 --- a/target/tilegx/cpu.h +++ b/target/tilegx/cpu.h @@ -21,13 +21,9 @@ #define TILEGX_CPU_H #include "qemu-common.h" - -#define TARGET_LONG_BITS 64 - -#define CPUArchState struct CPUTLGState - #include "exec/cpu-defs.h" +#define CPUArchState struct CPUTLGState /* TILE-Gx common register alias */ #define TILEGX_R_RE 0 /* 0 register, for function/syscall return value */ @@ -154,9 +150,6 @@ static inline TileGXCPU *tilegx_env_get_cpu(CPUTLGState *env) #define ENV_OFFSET offsetof(TileGXCPU, env) /* TILE-Gx memory attributes */ -#define TARGET_PAGE_BITS 16 /* TILE-Gx uses 64KB page size */ -#define TARGET_PHYS_ADDR_SPACE_BITS 42 -#define TARGET_VIRT_ADDR_SPACE_BITS 64 #define MMU_USER_IDX 0 /* Current memory operation is in user mode */ #include "exec/cpu-all.h" diff --git a/target/tricore/cpu-param.h b/target/tricore/cpu-param.h new file mode 100644 index 0000000000..cf5d9af89d --- /dev/null +++ b/target/tricore/cpu-param.h @@ -0,0 +1,17 @@ +/* + * TriCore cpu parameters for qemu. + * + * Copyright (c) 2012-2014 Bastian Koppelmann C-Lab/University Paderborn + * SPDX-License-Identifier: LGPL-2.1+ + */ + +#ifndef TRICORE_CPU_PARAM_H +#define TRICORE_CPU_PARAM_H 1 + +#define TARGET_LONG_BITS 32 +#define TARGET_PAGE_BITS 14 +#define TARGET_PHYS_ADDR_SPACE_BITS 32 +#define TARGET_VIRT_ADDR_SPACE_BITS 32 +#define NB_MMU_MODES 3 + +#endif diff --git a/target/tricore/cpu.h b/target/tricore/cpu.h index 287f4328a3..bccde45a07 100644 --- a/target/tricore/cpu.h +++ b/target/tricore/cpu.h @@ -20,10 +20,10 @@ #ifndef TRICORE_CPU_H #define TRICORE_CPU_H -#include "tricore-defs.h" #include "qemu-common.h" #include "cpu-qom.h" #include "exec/cpu-defs.h" +#include "tricore-defs.h" #define CPUArchState struct CPUTriCoreState @@ -31,8 +31,6 @@ struct CPUTriCoreState; struct tricore_boot_info; -#define NB_MMU_MODES 3 - typedef struct tricore_def_t tricore_def_t; typedef struct CPUTriCoreState CPUTriCoreState; diff --git a/target/tricore/tricore-defs.h b/target/tricore/tricore-defs.h index e871aa1c6b..f5e0a0bed8 100644 --- a/target/tricore/tricore-defs.h +++ b/target/tricore/tricore-defs.h @@ -18,11 +18,6 @@ #ifndef QEMU_TRICORE_DEFS_H #define QEMU_TRICORE_DEFS_H -#define TARGET_PAGE_BITS 14 -#define TARGET_LONG_BITS 32 -#define TARGET_PHYS_ADDR_SPACE_BITS 32 -#define TARGET_VIRT_ADDR_SPACE_BITS 32 - #define TRICORE_TLB_MAX 128 #endif /* QEMU_TRICORE_DEFS_H */ diff --git a/target/unicore32/cpu-param.h b/target/unicore32/cpu-param.h new file mode 100644 index 0000000000..94d8a5daa1 --- /dev/null +++ b/target/unicore32/cpu-param.h @@ -0,0 +1,17 @@ +/* + * UniCore32 cpu parameters for qemu. + * + * Copyright (C) 2010-2012 Guan Xuetao + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef UNICORE32_CPU_PARAM_H +#define UNICORE32_CPU_PARAM_H 1 + +#define TARGET_LONG_BITS 32 +#define TARGET_PAGE_BITS 12 +#define TARGET_PHYS_ADDR_SPACE_BITS 32 +#define TARGET_VIRT_ADDR_SPACE_BITS 32 +#define NB_MMU_MODES 2 + +#endif diff --git a/target/unicore32/cpu.h b/target/unicore32/cpu.h index f052ee08bf..a4c4ea328e 100644 --- a/target/unicore32/cpu.h +++ b/target/unicore32/cpu.h @@ -12,19 +12,11 @@ #ifndef UNICORE32_CPU_H #define UNICORE32_CPU_H -#define TARGET_LONG_BITS 32 -#define TARGET_PAGE_BITS 12 - -#define TARGET_PHYS_ADDR_SPACE_BITS 32 -#define TARGET_VIRT_ADDR_SPACE_BITS 32 - -#define CPUArchState struct CPUUniCore32State - #include "qemu-common.h" #include "cpu-qom.h" #include "exec/cpu-defs.h" -#define NB_MMU_MODES 2 +#define CPUArchState struct CPUUniCore32State typedef struct CPUUniCore32State { /* Regs for current mode. */ diff --git a/target/xtensa/cpu-param.h b/target/xtensa/cpu-param.h new file mode 100644 index 0000000000..4fde21b941 --- /dev/null +++ b/target/xtensa/cpu-param.h @@ -0,0 +1,21 @@ +/* + * Xtensa cpu parameters for qemu. + * + * Copyright (c) 2011, Max Filippov, Open Source and Linux Lab. + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef XTENSA_CPU_PARAM_H +#define XTENSA_CPU_PARAM_H 1 + +#define TARGET_LONG_BITS 32 +#define TARGET_PAGE_BITS 12 +#define TARGET_PHYS_ADDR_SPACE_BITS 32 +#ifdef CONFIG_USER_ONLY +#define TARGET_VIRT_ADDR_SPACE_BITS 30 +#else +#define TARGET_VIRT_ADDR_SPACE_BITS 32 +#endif +#define NB_MMU_MODES 4 + +#endif diff --git a/target/xtensa/cpu.h b/target/xtensa/cpu.h index a0df46f73b..0c6afd43a4 100644 --- a/target/xtensa/cpu.h +++ b/target/xtensa/cpu.h @@ -28,28 +28,17 @@ #ifndef XTENSA_CPU_H #define XTENSA_CPU_H -#define ALIGNED_ONLY -#define TARGET_LONG_BITS 32 - -/* Xtensa processors have a weak memory model */ -#define TCG_GUEST_DEFAULT_MO (0) - -#define CPUArchState struct CPUXtensaState - #include "qemu-common.h" #include "cpu-qom.h" #include "exec/cpu-defs.h" #include "xtensa-isa.h" -#define NB_MMU_MODES 4 +#define ALIGNED_ONLY -#define TARGET_PHYS_ADDR_SPACE_BITS 32 -#ifdef CONFIG_USER_ONLY -#define TARGET_VIRT_ADDR_SPACE_BITS 30 -#else -#define TARGET_VIRT_ADDR_SPACE_BITS 32 -#endif -#define TARGET_PAGE_BITS 12 +/* Xtensa processors have a weak memory model */ +#define TCG_GUEST_DEFAULT_MO (0) + +#define CPUArchState struct CPUXtensaState enum { /* Additional instructions */ -- cgit 1.4.1 From a40ec84ee2b02086e27fab78a152c20b09c723cf Mon Sep 17 00:00:00 2001 From: Richard Henderson Date: Fri, 22 Mar 2019 13:52:09 -0700 Subject: tcg: Create struct CPUTLB Move all softmmu tlb data into this structure. Arrange the members so that we are able to place mask+table together and at a smaller absolute offset from ENV. Reviewed-by: Peter Maydell Acked-by: Alistair Francis Signed-off-by: Richard Henderson --- accel/tcg/cputlb.c | 164 +++++++++++++++++++++++-------------------- include/exec/cpu-defs.h | 59 +++++++++------- include/exec/cpu_ldst.h | 6 +- target/arm/translate-a64.c | 2 +- tcg/aarch64/tcg-target.inc.c | 10 +-- tcg/arm/tcg-target.inc.c | 10 +-- tcg/i386/tcg-target.inc.c | 4 +- tcg/mips/tcg-target.inc.c | 12 +--- tcg/ppc/tcg-target.inc.c | 8 +-- tcg/riscv/tcg-target.inc.c | 12 +--- tcg/s390/tcg-target.inc.c | 8 +-- tcg/sparc/tcg-target.inc.c | 12 +--- 12 files changed, 145 insertions(+), 162 deletions(-) (limited to 'include/exec') diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index 41f2296f93..a3a39e9a77 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -76,7 +76,7 @@ QEMU_BUILD_BUG_ON(NB_MMU_MODES > 16); static inline size_t sizeof_tlb(CPUArchState *env, uintptr_t mmu_idx) { - return env->tlb_mask[mmu_idx] + (1 << CPU_TLB_ENTRY_BITS); + return env_tlb(env)->f[mmu_idx].mask + (1 << CPU_TLB_ENTRY_BITS); } static void tlb_window_reset(CPUTLBDesc *desc, int64_t ns, @@ -91,14 +91,14 @@ static void tlb_dyn_init(CPUArchState *env) int i; for (i = 0; i < NB_MMU_MODES; i++) { - CPUTLBDesc *desc = &env->tlb_d[i]; + CPUTLBDesc *desc = &env_tlb(env)->d[i]; size_t n_entries = 1 << CPU_TLB_DYN_DEFAULT_BITS; tlb_window_reset(desc, get_clock_realtime(), 0); desc->n_used_entries = 0; - env->tlb_mask[i] = (n_entries - 1) << CPU_TLB_ENTRY_BITS; - env->tlb_table[i] = g_new(CPUTLBEntry, n_entries); - env->iotlb[i] = g_new(CPUIOTLBEntry, n_entries); + env_tlb(env)->f[i].mask = (n_entries - 1) << CPU_TLB_ENTRY_BITS; + env_tlb(env)->f[i].table = g_new(CPUTLBEntry, n_entries); + env_tlb(env)->d[i].iotlb = g_new(CPUIOTLBEntry, n_entries); } } @@ -144,7 +144,7 @@ static void tlb_dyn_init(CPUArchState *env) */ static void tlb_mmu_resize_locked(CPUArchState *env, int mmu_idx) { - CPUTLBDesc *desc = &env->tlb_d[mmu_idx]; + CPUTLBDesc *desc = &env_tlb(env)->d[mmu_idx]; size_t old_size = tlb_n_entries(env, mmu_idx); size_t rate; size_t new_size = old_size; @@ -187,14 +187,14 @@ static void tlb_mmu_resize_locked(CPUArchState *env, int mmu_idx) return; } - g_free(env->tlb_table[mmu_idx]); - g_free(env->iotlb[mmu_idx]); + g_free(env_tlb(env)->f[mmu_idx].table); + g_free(env_tlb(env)->d[mmu_idx].iotlb); tlb_window_reset(desc, now, 0); /* desc->n_used_entries is cleared by the caller */ - env->tlb_mask[mmu_idx] = (new_size - 1) << CPU_TLB_ENTRY_BITS; - env->tlb_table[mmu_idx] = g_try_new(CPUTLBEntry, new_size); - env->iotlb[mmu_idx] = g_try_new(CPUIOTLBEntry, new_size); + env_tlb(env)->f[mmu_idx].mask = (new_size - 1) << CPU_TLB_ENTRY_BITS; + env_tlb(env)->f[mmu_idx].table = g_try_new(CPUTLBEntry, new_size); + env_tlb(env)->d[mmu_idx].iotlb = g_try_new(CPUIOTLBEntry, new_size); /* * If the allocations fail, try smaller sizes. We just freed some * memory, so going back to half of new_size has a good chance of working. @@ -202,46 +202,47 @@ static void tlb_mmu_resize_locked(CPUArchState *env, int mmu_idx) * allocations to fail though, so we progressively reduce the allocation * size, aborting if we cannot even allocate the smallest TLB we support. */ - while (env->tlb_table[mmu_idx] == NULL || env->iotlb[mmu_idx] == NULL) { + while (env_tlb(env)->f[mmu_idx].table == NULL || + env_tlb(env)->d[mmu_idx].iotlb == NULL) { if (new_size == (1 << CPU_TLB_DYN_MIN_BITS)) { error_report("%s: %s", __func__, strerror(errno)); abort(); } new_size = MAX(new_size >> 1, 1 << CPU_TLB_DYN_MIN_BITS); - env->tlb_mask[mmu_idx] = (new_size - 1) << CPU_TLB_ENTRY_BITS; + env_tlb(env)->f[mmu_idx].mask = (new_size - 1) << CPU_TLB_ENTRY_BITS; - g_free(env->tlb_table[mmu_idx]); - g_free(env->iotlb[mmu_idx]); - env->tlb_table[mmu_idx] = g_try_new(CPUTLBEntry, new_size); - env->iotlb[mmu_idx] = g_try_new(CPUIOTLBEntry, new_size); + g_free(env_tlb(env)->f[mmu_idx].table); + g_free(env_tlb(env)->d[mmu_idx].iotlb); + env_tlb(env)->f[mmu_idx].table = g_try_new(CPUTLBEntry, new_size); + env_tlb(env)->d[mmu_idx].iotlb = g_try_new(CPUIOTLBEntry, new_size); } } static inline void tlb_table_flush_by_mmuidx(CPUArchState *env, int mmu_idx) { tlb_mmu_resize_locked(env, mmu_idx); - memset(env->tlb_table[mmu_idx], -1, sizeof_tlb(env, mmu_idx)); - env->tlb_d[mmu_idx].n_used_entries = 0; + memset(env_tlb(env)->f[mmu_idx].table, -1, sizeof_tlb(env, mmu_idx)); + env_tlb(env)->d[mmu_idx].n_used_entries = 0; } static inline void tlb_n_used_entries_inc(CPUArchState *env, uintptr_t mmu_idx) { - env->tlb_d[mmu_idx].n_used_entries++; + env_tlb(env)->d[mmu_idx].n_used_entries++; } static inline void tlb_n_used_entries_dec(CPUArchState *env, uintptr_t mmu_idx) { - env->tlb_d[mmu_idx].n_used_entries--; + env_tlb(env)->d[mmu_idx].n_used_entries--; } void tlb_init(CPUState *cpu) { CPUArchState *env = cpu->env_ptr; - qemu_spin_init(&env->tlb_c.lock); + qemu_spin_init(&env_tlb(env)->c.lock); /* Ensure that cpu_reset performs a full flush. */ - env->tlb_c.dirty = ALL_MMUIDX_BITS; + env_tlb(env)->c.dirty = ALL_MMUIDX_BITS; tlb_dyn_init(env); } @@ -273,9 +274,9 @@ void tlb_flush_counts(size_t *pfull, size_t *ppart, size_t *pelide) CPU_FOREACH(cpu) { CPUArchState *env = cpu->env_ptr; - full += atomic_read(&env->tlb_c.full_flush_count); - part += atomic_read(&env->tlb_c.part_flush_count); - elide += atomic_read(&env->tlb_c.elide_flush_count); + full += atomic_read(&env_tlb(env)->c.full_flush_count); + part += atomic_read(&env_tlb(env)->c.part_flush_count); + elide += atomic_read(&env_tlb(env)->c.elide_flush_count); } *pfull = full; *ppart = part; @@ -285,10 +286,11 @@ void tlb_flush_counts(size_t *pfull, size_t *ppart, size_t *pelide) static void tlb_flush_one_mmuidx_locked(CPUArchState *env, int mmu_idx) { tlb_table_flush_by_mmuidx(env, mmu_idx); - memset(env->tlb_v_table[mmu_idx], -1, sizeof(env->tlb_v_table[0])); - env->tlb_d[mmu_idx].large_page_addr = -1; - env->tlb_d[mmu_idx].large_page_mask = -1; - env->tlb_d[mmu_idx].vindex = 0; + env_tlb(env)->d[mmu_idx].large_page_addr = -1; + env_tlb(env)->d[mmu_idx].large_page_mask = -1; + env_tlb(env)->d[mmu_idx].vindex = 0; + memset(env_tlb(env)->d[mmu_idx].vtable, -1, + sizeof(env_tlb(env)->d[0].vtable)); } static void tlb_flush_by_mmuidx_async_work(CPUState *cpu, run_on_cpu_data data) @@ -301,31 +303,31 @@ static void tlb_flush_by_mmuidx_async_work(CPUState *cpu, run_on_cpu_data data) tlb_debug("mmu_idx:0x%04" PRIx16 "\n", asked); - qemu_spin_lock(&env->tlb_c.lock); + qemu_spin_lock(&env_tlb(env)->c.lock); - all_dirty = env->tlb_c.dirty; + all_dirty = env_tlb(env)->c.dirty; to_clean = asked & all_dirty; all_dirty &= ~to_clean; - env->tlb_c.dirty = all_dirty; + env_tlb(env)->c.dirty = all_dirty; for (work = to_clean; work != 0; work &= work - 1) { int mmu_idx = ctz32(work); tlb_flush_one_mmuidx_locked(env, mmu_idx); } - qemu_spin_unlock(&env->tlb_c.lock); + qemu_spin_unlock(&env_tlb(env)->c.lock); cpu_tb_jmp_cache_clear(cpu); if (to_clean == ALL_MMUIDX_BITS) { - atomic_set(&env->tlb_c.full_flush_count, - env->tlb_c.full_flush_count + 1); + atomic_set(&env_tlb(env)->c.full_flush_count, + env_tlb(env)->c.full_flush_count + 1); } else { - atomic_set(&env->tlb_c.part_flush_count, - env->tlb_c.part_flush_count + ctpop16(to_clean)); + atomic_set(&env_tlb(env)->c.part_flush_count, + env_tlb(env)->c.part_flush_count + ctpop16(to_clean)); if (to_clean != asked) { - atomic_set(&env->tlb_c.elide_flush_count, - env->tlb_c.elide_flush_count + + atomic_set(&env_tlb(env)->c.elide_flush_count, + env_tlb(env)->c.elide_flush_count + ctpop16(asked & ~to_clean)); } } @@ -410,11 +412,12 @@ static inline bool tlb_flush_entry_locked(CPUTLBEntry *tlb_entry, static inline void tlb_flush_vtlb_page_locked(CPUArchState *env, int mmu_idx, target_ulong page) { + CPUTLBDesc *d = &env_tlb(env)->d[mmu_idx]; int k; assert_cpu_is_self(ENV_GET_CPU(env)); for (k = 0; k < CPU_VTLB_SIZE; k++) { - if (tlb_flush_entry_locked(&env->tlb_v_table[mmu_idx][k], page)) { + if (tlb_flush_entry_locked(&d->vtable[k], page)) { tlb_n_used_entries_dec(env, mmu_idx); } } @@ -423,8 +426,8 @@ static inline void tlb_flush_vtlb_page_locked(CPUArchState *env, int mmu_idx, static void tlb_flush_page_locked(CPUArchState *env, int midx, target_ulong page) { - target_ulong lp_addr = env->tlb_d[midx].large_page_addr; - target_ulong lp_mask = env->tlb_d[midx].large_page_mask; + target_ulong lp_addr = env_tlb(env)->d[midx].large_page_addr; + target_ulong lp_mask = env_tlb(env)->d[midx].large_page_mask; /* Check if we need to flush due to large pages. */ if ((page & lp_mask) == lp_addr) { @@ -459,13 +462,13 @@ static void tlb_flush_page_by_mmuidx_async_work(CPUState *cpu, tlb_debug("page addr:" TARGET_FMT_lx " mmu_map:0x%lx\n", addr, mmu_idx_bitmap); - qemu_spin_lock(&env->tlb_c.lock); + qemu_spin_lock(&env_tlb(env)->c.lock); for (mmu_idx = 0; mmu_idx < NB_MMU_MODES; mmu_idx++) { if (test_bit(mmu_idx, &mmu_idx_bitmap)) { tlb_flush_page_locked(env, mmu_idx, addr); } } - qemu_spin_unlock(&env->tlb_c.lock); + qemu_spin_unlock(&env_tlb(env)->c.lock); tb_flush_jmp_cache(cpu, addr); } @@ -609,22 +612,22 @@ void tlb_reset_dirty(CPUState *cpu, ram_addr_t start1, ram_addr_t length) int mmu_idx; env = cpu->env_ptr; - qemu_spin_lock(&env->tlb_c.lock); + qemu_spin_lock(&env_tlb(env)->c.lock); for (mmu_idx = 0; mmu_idx < NB_MMU_MODES; mmu_idx++) { unsigned int i; unsigned int n = tlb_n_entries(env, mmu_idx); for (i = 0; i < n; i++) { - tlb_reset_dirty_range_locked(&env->tlb_table[mmu_idx][i], start1, - length); + tlb_reset_dirty_range_locked(&env_tlb(env)->f[mmu_idx].table[i], + start1, length); } for (i = 0; i < CPU_VTLB_SIZE; i++) { - tlb_reset_dirty_range_locked(&env->tlb_v_table[mmu_idx][i], start1, - length); + tlb_reset_dirty_range_locked(&env_tlb(env)->d[mmu_idx].vtable[i], + start1, length); } } - qemu_spin_unlock(&env->tlb_c.lock); + qemu_spin_unlock(&env_tlb(env)->c.lock); } /* Called with tlb_c.lock held */ @@ -646,7 +649,7 @@ void tlb_set_dirty(CPUState *cpu, target_ulong vaddr) assert_cpu_is_self(cpu); vaddr &= TARGET_PAGE_MASK; - qemu_spin_lock(&env->tlb_c.lock); + qemu_spin_lock(&env_tlb(env)->c.lock); for (mmu_idx = 0; mmu_idx < NB_MMU_MODES; mmu_idx++) { tlb_set_dirty1_locked(tlb_entry(env, mmu_idx, vaddr), vaddr); } @@ -654,10 +657,10 @@ void tlb_set_dirty(CPUState *cpu, target_ulong vaddr) for (mmu_idx = 0; mmu_idx < NB_MMU_MODES; mmu_idx++) { int k; for (k = 0; k < CPU_VTLB_SIZE; k++) { - tlb_set_dirty1_locked(&env->tlb_v_table[mmu_idx][k], vaddr); + tlb_set_dirty1_locked(&env_tlb(env)->d[mmu_idx].vtable[k], vaddr); } } - qemu_spin_unlock(&env->tlb_c.lock); + qemu_spin_unlock(&env_tlb(env)->c.lock); } /* Our TLB does not support large pages, so remember the area covered by @@ -665,7 +668,7 @@ void tlb_set_dirty(CPUState *cpu, target_ulong vaddr) static void tlb_add_large_page(CPUArchState *env, int mmu_idx, target_ulong vaddr, target_ulong size) { - target_ulong lp_addr = env->tlb_d[mmu_idx].large_page_addr; + target_ulong lp_addr = env_tlb(env)->d[mmu_idx].large_page_addr; target_ulong lp_mask = ~(size - 1); if (lp_addr == (target_ulong)-1) { @@ -675,13 +678,13 @@ static void tlb_add_large_page(CPUArchState *env, int mmu_idx, /* Extend the existing region to include the new page. This is a compromise between unnecessary flushes and the cost of maintaining a full variable size TLB. */ - lp_mask &= env->tlb_d[mmu_idx].large_page_mask; + lp_mask &= env_tlb(env)->d[mmu_idx].large_page_mask; while (((lp_addr ^ vaddr) & lp_mask) != 0) { lp_mask <<= 1; } } - env->tlb_d[mmu_idx].large_page_addr = lp_addr & lp_mask; - env->tlb_d[mmu_idx].large_page_mask = lp_mask; + env_tlb(env)->d[mmu_idx].large_page_addr = lp_addr & lp_mask; + env_tlb(env)->d[mmu_idx].large_page_mask = lp_mask; } /* Add a new TLB entry. At most one entry for a given virtual address @@ -696,6 +699,8 @@ void tlb_set_page_with_attrs(CPUState *cpu, target_ulong vaddr, int mmu_idx, target_ulong size) { CPUArchState *env = cpu->env_ptr; + CPUTLB *tlb = env_tlb(env); + CPUTLBDesc *desc = &tlb->d[mmu_idx]; MemoryRegionSection *section; unsigned int index; target_ulong address; @@ -757,10 +762,10 @@ void tlb_set_page_with_attrs(CPUState *cpu, target_ulong vaddr, * a longer critical section, but this is not a concern since the TLB lock * is unlikely to be contended. */ - qemu_spin_lock(&env->tlb_c.lock); + qemu_spin_lock(&tlb->c.lock); /* Note that the tlb is no longer clean. */ - env->tlb_c.dirty |= 1 << mmu_idx; + tlb->c.dirty |= 1 << mmu_idx; /* Make sure there's no cached translation for the new page. */ tlb_flush_vtlb_page_locked(env, mmu_idx, vaddr_page); @@ -770,12 +775,12 @@ void tlb_set_page_with_attrs(CPUState *cpu, target_ulong vaddr, * different page; otherwise just overwrite the stale data. */ if (!tlb_hit_page_anyprot(te, vaddr_page) && !tlb_entry_is_empty(te)) { - unsigned vidx = env->tlb_d[mmu_idx].vindex++ % CPU_VTLB_SIZE; - CPUTLBEntry *tv = &env->tlb_v_table[mmu_idx][vidx]; + unsigned vidx = desc->vindex++ % CPU_VTLB_SIZE; + CPUTLBEntry *tv = &desc->vtable[vidx]; /* Evict the old entry into the victim tlb. */ copy_tlb_helper_locked(tv, te); - env->iotlb_v[mmu_idx][vidx] = env->iotlb[mmu_idx][index]; + desc->viotlb[vidx] = desc->iotlb[index]; tlb_n_used_entries_dec(env, mmu_idx); } @@ -792,8 +797,8 @@ void tlb_set_page_with_attrs(CPUState *cpu, target_ulong vaddr, * subtract here is that of the page base, and not the same as the * vaddr we add back in io_readx()/io_writex()/get_page_addr_code(). */ - env->iotlb[mmu_idx][index].addr = iotlb - vaddr_page; - env->iotlb[mmu_idx][index].attrs = attrs; + desc->iotlb[index].addr = iotlb - vaddr_page; + desc->iotlb[index].attrs = attrs; /* Now calculate the new entry */ tn.addend = addend - vaddr_page; @@ -829,7 +834,7 @@ void tlb_set_page_with_attrs(CPUState *cpu, target_ulong vaddr, copy_tlb_helper_locked(te, &tn); tlb_n_used_entries_inc(env, mmu_idx); - qemu_spin_unlock(&env->tlb_c.lock); + qemu_spin_unlock(&tlb->c.lock); } /* Add a new TLB entry, but without specifying the memory @@ -976,21 +981,28 @@ static bool victim_tlb_hit(CPUArchState *env, size_t mmu_idx, size_t index, assert_cpu_is_self(ENV_GET_CPU(env)); for (vidx = 0; vidx < CPU_VTLB_SIZE; ++vidx) { - CPUTLBEntry *vtlb = &env->tlb_v_table[mmu_idx][vidx]; - target_ulong cmp = tlb_read_ofs(vtlb, elt_ofs); + CPUTLBEntry *vtlb = &env_tlb(env)->d[mmu_idx].vtable[vidx]; + target_ulong cmp; + + /* elt_ofs might correspond to .addr_write, so use atomic_read */ +#if TCG_OVERSIZED_GUEST + cmp = *(target_ulong *)((uintptr_t)vtlb + elt_ofs); +#else + cmp = atomic_read((target_ulong *)((uintptr_t)vtlb + elt_ofs)); +#endif if (cmp == page) { /* Found entry in victim tlb, swap tlb and iotlb. */ - CPUTLBEntry tmptlb, *tlb = &env->tlb_table[mmu_idx][index]; + CPUTLBEntry tmptlb, *tlb = &env_tlb(env)->f[mmu_idx].table[index]; - qemu_spin_lock(&env->tlb_c.lock); + qemu_spin_lock(&env_tlb(env)->c.lock); copy_tlb_helper_locked(&tmptlb, tlb); copy_tlb_helper_locked(tlb, vtlb); copy_tlb_helper_locked(vtlb, &tmptlb); - qemu_spin_unlock(&env->tlb_c.lock); + qemu_spin_unlock(&env_tlb(env)->c.lock); - CPUIOTLBEntry tmpio, *io = &env->iotlb[mmu_idx][index]; - CPUIOTLBEntry *vio = &env->iotlb_v[mmu_idx][vidx]; + CPUIOTLBEntry tmpio, *io = &env_tlb(env)->d[mmu_idx].iotlb[index]; + CPUIOTLBEntry *vio = &env_tlb(env)->d[mmu_idx].viotlb[vidx]; tmpio = *io; *io = *vio; *vio = tmpio; return true; } @@ -1293,8 +1305,8 @@ load_helper(CPUArchState *env, target_ulong addr, TCGMemOpIdx oi, } } - res = io_readx(env, &env->iotlb[mmu_idx][index], mmu_idx, addr, - retaddr, access_type, size); + res = io_readx(env, &env_tlb(env)->d[mmu_idx].iotlb[index], + mmu_idx, addr, retaddr, access_type, size); return handle_bswap(res, size, big_endian); } @@ -1541,7 +1553,7 @@ store_helper(CPUArchState *env, target_ulong addr, uint64_t val, } } - io_writex(env, &env->iotlb[mmu_idx][index], mmu_idx, + io_writex(env, &env_tlb(env)->d[mmu_idx].iotlb[index], mmu_idx, handle_bswap(val, size, big_endian), addr, retaddr, size); return; diff --git a/include/exec/cpu-defs.h b/include/exec/cpu-defs.h index 2694481769..b9ec261b01 100644 --- a/include/exec/cpu-defs.h +++ b/include/exec/cpu-defs.h @@ -78,6 +78,7 @@ typedef uint64_t target_ulong; #endif #if !defined(CONFIG_USER_ONLY) && defined(CONFIG_TCG) + /* use a fully associative victim tlb of 8 entries */ #define CPU_VTLB_SIZE 8 @@ -147,6 +148,10 @@ typedef struct CPUIOTLBEntry { MemTxAttrs attrs; } CPUIOTLBEntry; +/* + * Data elements that are per MMU mode, minus the bits accessed by + * the TCG fast path. + */ typedef struct CPUTLBDesc { /* * Describe a region covering all of the large pages allocated @@ -160,16 +165,31 @@ typedef struct CPUTLBDesc { int64_t window_begin_ns; /* maximum number of entries observed in the window */ size_t window_max_entries; + size_t n_used_entries; /* The next index to use in the tlb victim table. */ size_t vindex; - size_t n_used_entries; + /* The tlb victim table, in two parts. */ + CPUTLBEntry vtable[CPU_VTLB_SIZE]; + CPUIOTLBEntry viotlb[CPU_VTLB_SIZE]; + /* The iotlb. */ + CPUIOTLBEntry *iotlb; } CPUTLBDesc; +/* + * Data elements that are per MMU mode, accessed by the fast path. + */ +typedef struct CPUTLBDescFast { + /* Contains (n_entries - 1) << CPU_TLB_ENTRY_BITS */ + uintptr_t mask; + /* The array of tlb entries itself. */ + CPUTLBEntry *table; +} CPUTLBDescFast; + /* * Data elements that are shared between all MMU modes. */ typedef struct CPUTLBCommon { - /* Serialize updates to tlb_table and tlb_v_table, and others as noted. */ + /* Serialize updates to f.table and d.vtable, and others as noted. */ QemuSpin lock; /* * Within dirty, for each bit N, modifications have been made to @@ -187,35 +207,24 @@ typedef struct CPUTLBCommon { size_t elide_flush_count; } CPUTLBCommon; -# define CPU_TLB \ - /* tlb_mask[i] contains (n_entries - 1) << CPU_TLB_ENTRY_BITS */ \ - uintptr_t tlb_mask[NB_MMU_MODES]; \ - CPUTLBEntry *tlb_table[NB_MMU_MODES]; -# define CPU_IOTLB \ - CPUIOTLBEntry *iotlb[NB_MMU_MODES]; - /* + * The entire softmmu tlb, for all MMU modes. * The meaning of each of the MMU modes is defined in the target code. - * Note that NB_MMU_MODES is not yet defined; we can only reference it - * within preprocessor defines that will be expanded later. */ -#define CPU_COMMON_TLB \ - CPUTLBCommon tlb_c; \ - CPUTLBDesc tlb_d[NB_MMU_MODES]; \ - CPU_TLB \ - CPUTLBEntry tlb_v_table[NB_MMU_MODES][CPU_VTLB_SIZE]; \ - CPU_IOTLB \ - CPUIOTLBEntry iotlb_v[NB_MMU_MODES][CPU_VTLB_SIZE]; - -#else +typedef struct CPUTLB { + CPUTLBDescFast f[NB_MMU_MODES]; + CPUTLBDesc d[NB_MMU_MODES]; + CPUTLBCommon c; +} CPUTLB; -#define CPU_COMMON_TLB +/* There are target-specific members named "tlb". This is temporary. */ +#define CPU_COMMON CPUTLB tlb_; +#define env_tlb(ENV) (&(ENV)->tlb_) -#endif +#else +#define CPU_COMMON /* Nothing */ -#define CPU_COMMON \ - /* soft mmu support */ \ - CPU_COMMON_TLB \ +#endif /* !CONFIG_USER_ONLY && CONFIG_TCG */ #endif diff --git a/include/exec/cpu_ldst.h b/include/exec/cpu_ldst.h index 7b28a839d2..a08b11bd2c 100644 --- a/include/exec/cpu_ldst.h +++ b/include/exec/cpu_ldst.h @@ -139,21 +139,21 @@ static inline target_ulong tlb_addr_write(const CPUTLBEntry *entry) static inline uintptr_t tlb_index(CPUArchState *env, uintptr_t mmu_idx, target_ulong addr) { - uintptr_t size_mask = env->tlb_mask[mmu_idx] >> CPU_TLB_ENTRY_BITS; + uintptr_t size_mask = env_tlb(env)->f[mmu_idx].mask >> CPU_TLB_ENTRY_BITS; return (addr >> TARGET_PAGE_BITS) & size_mask; } static inline size_t tlb_n_entries(CPUArchState *env, uintptr_t mmu_idx) { - return (env->tlb_mask[mmu_idx] >> CPU_TLB_ENTRY_BITS) + 1; + return (env_tlb(env)->f[mmu_idx].mask >> CPU_TLB_ENTRY_BITS) + 1; } /* Find the TLB entry corresponding to the mmu_idx + address pair. */ static inline CPUTLBEntry *tlb_entry(CPUArchState *env, uintptr_t mmu_idx, target_ulong addr) { - return &env->tlb_table[mmu_idx][tlb_index(env, mmu_idx, addr)]; + return &env_tlb(env)->f[mmu_idx].table[tlb_index(env, mmu_idx, addr)]; } #ifdef MMU_MODE0_SUFFIX diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 092f0df3c4..f5440e57dd 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -14134,7 +14134,7 @@ static bool is_guarded_page(CPUARMState *env, DisasContext *s) * table entry even for that case. */ return (tlb_hit(entry->addr_code, addr) && - env->iotlb[mmu_idx][index].attrs.target_tlb_bit0); + env_tlb(env)->d[mmu_idx].iotlb[index].attrs.target_tlb_bit0); #endif } diff --git a/tcg/aarch64/tcg-target.inc.c b/tcg/aarch64/tcg-target.inc.c index 9e1dad9696..90957593a3 100644 --- a/tcg/aarch64/tcg-target.inc.c +++ b/tcg/aarch64/tcg-target.inc.c @@ -1637,12 +1637,8 @@ static void add_qemu_ldst_label(TCGContext *s, bool is_ld, TCGMemOpIdx oi, label->label_ptr[0] = label_ptr; } -/* We expect tlb_mask to be before tlb_table. */ -QEMU_BUILD_BUG_ON(offsetof(CPUArchState, tlb_table) < - offsetof(CPUArchState, tlb_mask)); - /* We expect to use a 24-bit unsigned offset from ENV. */ -QEMU_BUILD_BUG_ON(offsetof(CPUArchState, tlb_table[NB_MMU_MODES - 1]) +QEMU_BUILD_BUG_ON(offsetof(CPUArchState, tlb_.f[NB_MMU_MODES - 1].table) > 0xffffff); /* Load and compare a TLB entry, emitting the conditional jump to the @@ -1653,8 +1649,8 @@ static void tcg_out_tlb_read(TCGContext *s, TCGReg addr_reg, TCGMemOp opc, tcg_insn_unit **label_ptr, int mem_index, bool is_read) { - int mask_ofs = offsetof(CPUArchState, tlb_mask[mem_index]); - int table_ofs = offsetof(CPUArchState, tlb_table[mem_index]); + int mask_ofs = offsetof(CPUArchState, tlb_.f[mem_index].mask); + int table_ofs = offsetof(CPUArchState, tlb_.f[mem_index].table); unsigned a_bits = get_alignment_bits(opc); unsigned s_bits = opc & MO_SIZE; unsigned a_mask = (1u << a_bits) - 1; diff --git a/tcg/arm/tcg-target.inc.c b/tcg/arm/tcg-target.inc.c index 7316504c9d..38de6d59c7 100644 --- a/tcg/arm/tcg-target.inc.c +++ b/tcg/arm/tcg-target.inc.c @@ -1220,12 +1220,8 @@ static TCGReg tcg_out_arg_reg64(TCGContext *s, TCGReg argreg, #define TLB_SHIFT (CPU_TLB_ENTRY_BITS + CPU_TLB_BITS) -/* We expect tlb_mask to be before tlb_table. */ -QEMU_BUILD_BUG_ON(offsetof(CPUArchState, tlb_table) < - offsetof(CPUArchState, tlb_mask)); - /* We expect to use a 20-bit unsigned offset from ENV. */ -QEMU_BUILD_BUG_ON(offsetof(CPUArchState, tlb_table[NB_MMU_MODES - 1]) +QEMU_BUILD_BUG_ON(offsetof(CPUArchState, tlb_.f[NB_MMU_MODES - 1].table) > 0xfffff); /* Load and compare a TLB entry, leaving the flags set. Returns the register @@ -1236,8 +1232,8 @@ static TCGReg tcg_out_tlb_read(TCGContext *s, TCGReg addrlo, TCGReg addrhi, { int cmp_off = (is_load ? offsetof(CPUTLBEntry, addr_read) : offsetof(CPUTLBEntry, addr_write)); - int mask_off = offsetof(CPUArchState, tlb_mask[mem_index]); - int table_off = offsetof(CPUArchState, tlb_table[mem_index]); + int mask_off = offsetof(CPUArchState, tlb_.f[mem_index].mask); + int table_off = offsetof(CPUArchState, tlb_.f[mem_index].table); TCGReg mask_base = TCG_AREG0, table_base = TCG_AREG0; unsigned s_bits = opc & MO_SIZE; unsigned a_bits = get_alignment_bits(opc); diff --git a/tcg/i386/tcg-target.inc.c b/tcg/i386/tcg-target.inc.c index c0443da4af..5f5b886c04 100644 --- a/tcg/i386/tcg-target.inc.c +++ b/tcg/i386/tcg-target.inc.c @@ -1730,10 +1730,10 @@ static inline void tcg_out_tlb_load(TCGContext *s, TCGReg addrlo, TCGReg addrhi, TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS); tcg_out_modrm_offset(s, OPC_AND_GvEv + trexw, r0, TCG_AREG0, - offsetof(CPUArchState, tlb_mask[mem_index])); + offsetof(CPUArchState, tlb_.f[mem_index].mask)); tcg_out_modrm_offset(s, OPC_ADD_GvEv + hrexw, r0, TCG_AREG0, - offsetof(CPUArchState, tlb_table[mem_index])); + offsetof(CPUArchState, tlb_.f[mem_index].table)); /* If the required alignment is at least as large as the access, simply copy the address and mask. For lesser alignments, check that we don't diff --git a/tcg/mips/tcg-target.inc.c b/tcg/mips/tcg-target.inc.c index 7cafd4a790..ef6633587e 100644 --- a/tcg/mips/tcg-target.inc.c +++ b/tcg/mips/tcg-target.inc.c @@ -1202,14 +1202,6 @@ static int tcg_out_call_iarg_reg2(TCGContext *s, int i, TCGReg al, TCGReg ah) return i; } -/* We expect tlb_mask to be before tlb_table. */ -QEMU_BUILD_BUG_ON(offsetof(CPUArchState, tlb_table) < - offsetof(CPUArchState, tlb_mask)); - -/* We expect tlb_mask to be "near" tlb_table. */ -QEMU_BUILD_BUG_ON(offsetof(CPUArchState, tlb_table) - - offsetof(CPUArchState, tlb_mask) >= 0x8000); - /* * Perform the tlb comparison operation. * The complete host address is placed in BASE. @@ -1223,8 +1215,8 @@ static void tcg_out_tlb_load(TCGContext *s, TCGReg base, TCGReg addrl, unsigned s_bits = opc & MO_SIZE; unsigned a_bits = get_alignment_bits(opc); int mem_index = get_mmuidx(oi); - int mask_off = offsetof(CPUArchState, tlb_mask[mem_index]); - int table_off = offsetof(CPUArchState, tlb_table[mem_index]); + int mask_off = offsetof(CPUArchState, tlb_.f[mem_index].mask); + int table_off = offsetof(CPUArchState, tlb_.f[mem_index].mask); int add_off = offsetof(CPUTLBEntry, addend); int cmp_off = (is_load ? offsetof(CPUTLBEntry, addr_read) : offsetof(CPUTLBEntry, addr_write)); diff --git a/tcg/ppc/tcg-target.inc.c b/tcg/ppc/tcg-target.inc.c index 30c095d3d5..d69c18ac1e 100644 --- a/tcg/ppc/tcg-target.inc.c +++ b/tcg/ppc/tcg-target.inc.c @@ -1498,10 +1498,6 @@ static void * const qemu_st_helpers[16] = { [MO_BEQ] = helper_be_stq_mmu, }; -/* We expect tlb_mask to be before tlb_table. */ -QEMU_BUILD_BUG_ON(offsetof(CPUArchState, tlb_table) < - offsetof(CPUArchState, tlb_mask)); - /* Perform the TLB load and compare. Places the result of the comparison in CR7, loads the addend of the TLB into R3, and returns the register containing the guest address (zero-extended into R4). Clobbers R0 and R2. */ @@ -1514,8 +1510,8 @@ static TCGReg tcg_out_tlb_read(TCGContext *s, TCGMemOp opc, = (is_read ? offsetof(CPUTLBEntry, addr_read) : offsetof(CPUTLBEntry, addr_write)); - int mask_off = offsetof(CPUArchState, tlb_mask[mem_index]); - int table_off = offsetof(CPUArchState, tlb_table[mem_index]); + int mask_off = offsetof(CPUArchState, tlb_.f[mem_index].mask); + int table_off = offsetof(CPUArchState, tlb_.f[mem_index].table); TCGReg mask_base = TCG_AREG0, table_base = TCG_AREG0; unsigned s_bits = opc & MO_SIZE; unsigned a_bits = get_alignment_bits(opc); diff --git a/tcg/riscv/tcg-target.inc.c b/tcg/riscv/tcg-target.inc.c index 6497a4dab2..96c33bf621 100644 --- a/tcg/riscv/tcg-target.inc.c +++ b/tcg/riscv/tcg-target.inc.c @@ -962,14 +962,6 @@ static void * const qemu_st_helpers[16] = { /* We don't support oversize guests */ QEMU_BUILD_BUG_ON(TCG_TARGET_REG_BITS < TARGET_LONG_BITS); -/* We expect tlb_mask to be before tlb_table. */ -QEMU_BUILD_BUG_ON(offsetof(CPUArchState, tlb_table) < - offsetof(CPUArchState, tlb_mask)); - -/* We expect tlb_mask to be "near" tlb_table. */ -QEMU_BUILD_BUG_ON(offsetof(CPUArchState, tlb_table) - - offsetof(CPUArchState, tlb_mask) >= 0x800); - static void tcg_out_tlb_load(TCGContext *s, TCGReg addrl, TCGReg addrh, TCGMemOpIdx oi, tcg_insn_unit **label_ptr, bool is_load) @@ -982,8 +974,8 @@ static void tcg_out_tlb_load(TCGContext *s, TCGReg addrl, int mask_off, table_off; TCGReg mask_base = TCG_AREG0, table_base = TCG_AREG0; - mask_off = offsetof(CPUArchState, tlb_mask[mem_index]); - table_off = offsetof(CPUArchState, tlb_table[mem_index]); + mask_off = offsetof(CPUArchState, tlb_.f[mem_index].mask); + table_off = offsetof(CPUArchState, tlb_.f[mem_index].table); if (table_off > 0x7ff) { int mask_hi = mask_off - sextreg(mask_off, 0, 12); int table_hi = table_off - sextreg(table_off, 0, 12); diff --git a/tcg/s390/tcg-target.inc.c b/tcg/s390/tcg-target.inc.c index 331d51852c..4d896d0b58 100644 --- a/tcg/s390/tcg-target.inc.c +++ b/tcg/s390/tcg-target.inc.c @@ -1539,9 +1539,7 @@ static void tcg_out_qemu_st_direct(TCGContext *s, TCGMemOp opc, TCGReg data, #include "tcg-ldst.inc.c" /* We're expecting to use a 20-bit signed offset on the tlb memory ops. */ -QEMU_BUILD_BUG_ON(offsetof(CPUArchState, tlb_mask[NB_MMU_MODES - 1]) - > 0x7ffff); -QEMU_BUILD_BUG_ON(offsetof(CPUArchState, tlb_table[NB_MMU_MODES - 1]) +QEMU_BUILD_BUG_ON(offsetof(CPUArchState, tlb_.f[NB_MMU_MODES - 1].table) > 0x7ffff); /* Load and compare a TLB entry, leaving the flags set. Loads the TLB @@ -1553,8 +1551,8 @@ static TCGReg tcg_out_tlb_read(TCGContext* s, TCGReg addr_reg, TCGMemOp opc, unsigned a_bits = get_alignment_bits(opc); unsigned s_mask = (1 << s_bits) - 1; unsigned a_mask = (1 << a_bits) - 1; - int mask_off = offsetof(CPUArchState, tlb_mask[mem_index]); - int table_off = offsetof(CPUArchState, tlb_table[mem_index]); + int mask_off = offsetof(CPUArchState, tlb_.f[mem_index].mask); + int table_off = offsetof(CPUArchState, tlb_.f[mem_index].table); int ofs, a_off; uint64_t tlb_mask; diff --git a/tcg/sparc/tcg-target.inc.c b/tcg/sparc/tcg-target.inc.c index 83295955a7..066cb0e892 100644 --- a/tcg/sparc/tcg-target.inc.c +++ b/tcg/sparc/tcg-target.inc.c @@ -1075,19 +1075,11 @@ static void tcg_out_nop_fill(tcg_insn_unit *p, int count) The result of the TLB comparison is in %[ix]cc. The sanitized address is in the returned register, maybe %o0. The TLB addend is in %o1. */ -/* We expect tlb_mask to be before tlb_table. */ -QEMU_BUILD_BUG_ON(offsetof(CPUArchState, tlb_table) < - offsetof(CPUArchState, tlb_mask)); - -/* We expect tlb_mask to be "near" tlb_table. */ -QEMU_BUILD_BUG_ON(offsetof(CPUArchState, tlb_table) - - offsetof(CPUArchState, tlb_mask) >= (1 << 13)); - static TCGReg tcg_out_tlb_load(TCGContext *s, TCGReg addr, int mem_index, TCGMemOp opc, int which) { - int mask_off = offsetof(CPUArchState, tlb_mask[mem_index]); - int table_off = offsetof(CPUArchState, tlb_table[mem_index]); + int mask_off = offsetof(CPUArchState, tlb_.f[mem_index].mask); + int table_off = offsetof(CPUArchState, tlb_.f[mem_index].table); TCGReg base = TCG_AREG0; const TCGReg r0 = TCG_REG_O0; const TCGReg r1 = TCG_REG_O1; -- cgit 1.4.1 From 29a0af618ddd21f55df5753c3e16b0625f534b3c Mon Sep 17 00:00:00 2001 From: Richard Henderson Date: Fri, 22 Mar 2019 16:07:18 -0700 Subject: cpu: Replace ENV_GET_CPU with env_cpu Now that we have both ArchCPU and CPUArchState, we can define this generically instead of via macro in each target's cpu.h. Reviewed-by: Peter Maydell Acked-by: Alistair Francis Signed-off-by: Richard Henderson --- accel/tcg/atomic_template.h | 8 ++--- accel/tcg/cputlb.c | 38 ++++++++++---------- accel/tcg/tcg-runtime.c | 4 +-- accel/tcg/translate-all.c | 2 +- accel/tcg/user-exec.c | 2 +- bsd-user/syscall.c | 6 ++-- docs/devel/tracing.txt | 4 +-- hw/semihosting/console.c | 2 +- include/exec/cpu-all.h | 12 +++++++ include/exec/cpu_ldst_template.h | 6 ++-- include/exec/cpu_ldst_useronly_template.h | 6 ++-- include/exec/softmmu-semi.h | 16 ++++----- linux-user/arm/cpu_loop.c | 2 +- linux-user/cpu_loop-common.h | 2 +- linux-user/cris/cpu_loop.c | 2 +- linux-user/elfload.c | 6 ++-- linux-user/m68k/cpu_loop.c | 2 +- linux-user/main.c | 2 +- linux-user/mips/cpu_loop.c | 2 +- linux-user/nios2/cpu_loop.c | 2 +- linux-user/riscv/cpu_loop.c | 2 +- linux-user/signal.c | 8 ++--- linux-user/syscall.c | 18 +++++----- linux-user/uname.c | 2 +- scripts/tracetool/format/tcg_helper_c.py | 2 +- target/alpha/cpu.h | 2 -- target/arm/cpu.h | 2 -- target/arm/helper.c | 42 +++++++++++----------- target/cris/cpu.h | 2 -- target/hppa/cpu.h | 1 - target/hppa/op_helper.c | 2 +- target/i386/cpu.h | 2 -- target/i386/hax-all.c | 6 ++-- target/i386/hvf/x86_decode.c | 22 ++++++------ target/i386/hvf/x86_emu.c | 60 +++++++++++++++++-------------- target/i386/mem_helper.c | 4 +-- target/lm32/cpu.h | 2 -- target/m68k/cpu.h | 2 -- target/m68k/op_helper.c | 2 +- target/microblaze/cpu.h | 2 -- target/mips/cpu.h | 2 -- target/moxie/cpu.h | 2 -- target/nios2/cpu.h | 2 -- target/nios2/mmu.c | 4 +-- target/nios2/op_helper.c | 2 +- target/openrisc/cpu.h | 2 -- target/ppc/cpu.h | 2 -- target/ppc/mmu_helper.c | 2 +- target/riscv/cpu.h | 1 - target/s390x/cpu.h | 2 -- target/s390x/gdbstub.c | 24 ++++++------- target/s390x/mem_helper.c | 2 +- target/sh4/cpu.h | 2 -- target/sh4/op_helper.c | 2 +- target/sparc/cpu.h | 2 -- target/tilegx/cpu.h | 2 -- target/tricore/cpu.h | 2 -- target/unicore32/cpu.h | 2 -- target/xtensa/cpu.h | 2 -- 59 files changed, 175 insertions(+), 197 deletions(-) (limited to 'include/exec') diff --git a/accel/tcg/atomic_template.h b/accel/tcg/atomic_template.h index 685602b076..5aaf186253 100644 --- a/accel/tcg/atomic_template.h +++ b/accel/tcg/atomic_template.h @@ -62,21 +62,21 @@ #define ATOMIC_TRACE_RMW do { \ uint8_t info = glue(trace_mem_build_info_no_se, MEND)(SHIFT, false); \ \ - trace_guest_mem_before_exec(ENV_GET_CPU(env), addr, info); \ - trace_guest_mem_before_exec(ENV_GET_CPU(env), addr, \ + trace_guest_mem_before_exec(env_cpu(env), addr, info); \ + trace_guest_mem_before_exec(env_cpu(env), addr, \ info | TRACE_MEM_ST); \ } while (0) #define ATOMIC_TRACE_LD do { \ uint8_t info = glue(trace_mem_build_info_no_se, MEND)(SHIFT, false); \ \ - trace_guest_mem_before_exec(ENV_GET_CPU(env), addr, info); \ + trace_guest_mem_before_exec(env_cpu(env), addr, info); \ } while (0) # define ATOMIC_TRACE_ST do { \ uint8_t info = glue(trace_mem_build_info_no_se, MEND)(SHIFT, true); \ \ - trace_guest_mem_before_exec(ENV_GET_CPU(env), addr, info); \ + trace_guest_mem_before_exec(env_cpu(env), addr, info); \ } while (0) /* Define host-endian atomic operations. Note that END is used within diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index a3a39e9a77..baa3eb8f92 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -415,7 +415,7 @@ static inline void tlb_flush_vtlb_page_locked(CPUArchState *env, int mmu_idx, CPUTLBDesc *d = &env_tlb(env)->d[mmu_idx]; int k; - assert_cpu_is_self(ENV_GET_CPU(env)); + assert_cpu_is_self(env_cpu(env)); for (k = 0; k < CPU_VTLB_SIZE; k++) { if (tlb_flush_entry_locked(&d->vtable[k], page)) { tlb_n_used_entries_dec(env, mmu_idx); @@ -883,7 +883,7 @@ static uint64_t io_readx(CPUArchState *env, CPUIOTLBEntry *iotlbentry, int mmu_idx, target_ulong addr, uintptr_t retaddr, MMUAccessType access_type, int size) { - CPUState *cpu = ENV_GET_CPU(env); + CPUState *cpu = env_cpu(env); hwaddr mr_offset; MemoryRegionSection *section; MemoryRegion *mr; @@ -927,7 +927,7 @@ static void io_writex(CPUArchState *env, CPUIOTLBEntry *iotlbentry, int mmu_idx, uint64_t val, target_ulong addr, uintptr_t retaddr, int size) { - CPUState *cpu = ENV_GET_CPU(env); + CPUState *cpu = env_cpu(env); hwaddr mr_offset; MemoryRegionSection *section; MemoryRegion *mr; @@ -979,7 +979,7 @@ static bool victim_tlb_hit(CPUArchState *env, size_t mmu_idx, size_t index, { size_t vidx; - assert_cpu_is_self(ENV_GET_CPU(env)); + assert_cpu_is_self(env_cpu(env)); for (vidx = 0; vidx < CPU_VTLB_SIZE; ++vidx) { CPUTLBEntry *vtlb = &env_tlb(env)->d[mmu_idx].vtable[vidx]; target_ulong cmp; @@ -1029,7 +1029,7 @@ tb_page_addr_t get_page_addr_code(CPUArchState *env, target_ulong addr) if (unlikely(!tlb_hit(entry->addr_code, addr))) { if (!VICTIM_TLB_HIT(addr_code, addr)) { - tlb_fill(ENV_GET_CPU(env), addr, 0, MMU_INST_FETCH, mmu_idx, 0); + tlb_fill(env_cpu(env), addr, 0, MMU_INST_FETCH, mmu_idx, 0); index = tlb_index(env, mmu_idx, addr); entry = tlb_entry(env, mmu_idx, addr); } @@ -1067,7 +1067,7 @@ void probe_write(CPUArchState *env, target_ulong addr, int size, int mmu_idx, if (!tlb_hit(tlb_addr_write(entry), addr)) { /* TLB entry is for a different page */ if (!VICTIM_TLB_HIT(addr_write, addr)) { - tlb_fill(ENV_GET_CPU(env), addr, size, MMU_DATA_STORE, + tlb_fill(env_cpu(env), addr, size, MMU_DATA_STORE, mmu_idx, retaddr); } } @@ -1101,7 +1101,7 @@ void *tlb_vaddr_to_host(CPUArchState *env, abi_ptr addr, uintptr_t index = tlb_index(env, mmu_idx, addr); if (!victim_tlb_hit(env, mmu_idx, index, elt_ofs, page)) { - CPUState *cs = ENV_GET_CPU(env); + CPUState *cs = env_cpu(env); CPUClass *cc = CPU_GET_CLASS(cs); if (!cc->tlb_fill(cs, addr, 0, access_type, mmu_idx, true, 0)) { @@ -1144,7 +1144,7 @@ static void *atomic_mmu_lookup(CPUArchState *env, target_ulong addr, /* Enforce guest required alignment. */ if (unlikely(a_bits > 0 && (addr & ((1 << a_bits) - 1)))) { /* ??? Maybe indicate atomic op to cpu_unaligned_access */ - cpu_unaligned_access(ENV_GET_CPU(env), addr, MMU_DATA_STORE, + cpu_unaligned_access(env_cpu(env), addr, MMU_DATA_STORE, mmu_idx, retaddr); } @@ -1160,7 +1160,7 @@ static void *atomic_mmu_lookup(CPUArchState *env, target_ulong addr, /* Check TLB entry and enforce page permissions. */ if (!tlb_hit(tlb_addr, addr)) { if (!VICTIM_TLB_HIT(addr_write, addr)) { - tlb_fill(ENV_GET_CPU(env), addr, 1 << s_bits, MMU_DATA_STORE, + tlb_fill(env_cpu(env), addr, 1 << s_bits, MMU_DATA_STORE, mmu_idx, retaddr); index = tlb_index(env, mmu_idx, addr); tlbe = tlb_entry(env, mmu_idx, addr); @@ -1177,7 +1177,7 @@ static void *atomic_mmu_lookup(CPUArchState *env, target_ulong addr, /* Let the guest notice RMW on a write-only page. */ if (unlikely(tlbe->addr_read != (tlb_addr & ~TLB_NOTDIRTY))) { - tlb_fill(ENV_GET_CPU(env), addr, 1 << s_bits, MMU_DATA_LOAD, + tlb_fill(env_cpu(env), addr, 1 << s_bits, MMU_DATA_LOAD, mmu_idx, retaddr); /* Since we don't support reads and writes to different addresses, and we do have the proper page loaded for write, this shouldn't @@ -1190,7 +1190,7 @@ static void *atomic_mmu_lookup(CPUArchState *env, target_ulong addr, ndi->active = false; if (unlikely(tlb_addr & TLB_NOTDIRTY)) { ndi->active = true; - memory_notdirty_write_prepare(ndi, ENV_GET_CPU(env), addr, + memory_notdirty_write_prepare(ndi, env_cpu(env), addr, qemu_ram_addr_from_host_nofail(hostaddr), 1 << s_bits); } @@ -1198,7 +1198,7 @@ static void *atomic_mmu_lookup(CPUArchState *env, target_ulong addr, return hostaddr; stop_the_world: - cpu_loop_exit_atomic(ENV_GET_CPU(env), retaddr); + cpu_loop_exit_atomic(env_cpu(env), retaddr); } #ifdef TARGET_WORDS_BIGENDIAN @@ -1263,7 +1263,7 @@ load_helper(CPUArchState *env, target_ulong addr, TCGMemOpIdx oi, /* Handle CPU specific unaligned behaviour */ if (addr & ((1 << a_bits) - 1)) { - cpu_unaligned_access(ENV_GET_CPU(env), addr, access_type, + cpu_unaligned_access(env_cpu(env), addr, access_type, mmu_idx, retaddr); } @@ -1271,7 +1271,7 @@ load_helper(CPUArchState *env, target_ulong addr, TCGMemOpIdx oi, if (!tlb_hit(tlb_addr, addr)) { if (!victim_tlb_hit(env, mmu_idx, index, tlb_off, addr & TARGET_PAGE_MASK)) { - tlb_fill(ENV_GET_CPU(env), addr, size, + tlb_fill(env_cpu(env), addr, size, access_type, mmu_idx, retaddr); index = tlb_index(env, mmu_idx, addr); entry = tlb_entry(env, mmu_idx, addr); @@ -1292,7 +1292,7 @@ load_helper(CPUArchState *env, target_ulong addr, TCGMemOpIdx oi, * repeat the MMU check here. This tlb_fill() call might * longjump out if this access should cause a guest exception. */ - tlb_fill(ENV_GET_CPU(env), addr, size, + tlb_fill(env_cpu(env), addr, size, access_type, mmu_idx, retaddr); index = tlb_index(env, mmu_idx, addr); entry = tlb_entry(env, mmu_idx, addr); @@ -1511,7 +1511,7 @@ store_helper(CPUArchState *env, target_ulong addr, uint64_t val, /* Handle CPU specific unaligned behaviour */ if (addr & ((1 << a_bits) - 1)) { - cpu_unaligned_access(ENV_GET_CPU(env), addr, MMU_DATA_STORE, + cpu_unaligned_access(env_cpu(env), addr, MMU_DATA_STORE, mmu_idx, retaddr); } @@ -1519,7 +1519,7 @@ store_helper(CPUArchState *env, target_ulong addr, uint64_t val, if (!tlb_hit(tlb_addr, addr)) { if (!victim_tlb_hit(env, mmu_idx, index, tlb_off, addr & TARGET_PAGE_MASK)) { - tlb_fill(ENV_GET_CPU(env), addr, size, MMU_DATA_STORE, + tlb_fill(env_cpu(env), addr, size, MMU_DATA_STORE, mmu_idx, retaddr); index = tlb_index(env, mmu_idx, addr); entry = tlb_entry(env, mmu_idx, addr); @@ -1540,7 +1540,7 @@ store_helper(CPUArchState *env, target_ulong addr, uint64_t val, * repeat the MMU check here. This tlb_fill() call might * longjump out if this access should cause a guest exception. */ - tlb_fill(ENV_GET_CPU(env), addr, size, MMU_DATA_STORE, + tlb_fill(env_cpu(env), addr, size, MMU_DATA_STORE, mmu_idx, retaddr); index = tlb_index(env, mmu_idx, addr); entry = tlb_entry(env, mmu_idx, addr); @@ -1580,7 +1580,7 @@ store_helper(CPUArchState *env, target_ulong addr, uint64_t val, if (!tlb_hit_page(tlb_addr2, page2) && !victim_tlb_hit(env, mmu_idx, index2, tlb_off, page2 & TARGET_PAGE_MASK)) { - tlb_fill(ENV_GET_CPU(env), page2, size, MMU_DATA_STORE, + tlb_fill(env_cpu(env), page2, size, MMU_DATA_STORE, mmu_idx, retaddr); } diff --git a/accel/tcg/tcg-runtime.c b/accel/tcg/tcg-runtime.c index d0d4484406..8a1e408e31 100644 --- a/accel/tcg/tcg-runtime.c +++ b/accel/tcg/tcg-runtime.c @@ -146,7 +146,7 @@ uint64_t HELPER(ctpop_i64)(uint64_t arg) void *HELPER(lookup_tb_ptr)(CPUArchState *env) { - CPUState *cpu = ENV_GET_CPU(env); + CPUState *cpu = env_cpu(env); TranslationBlock *tb; target_ulong cs_base, pc; uint32_t flags; @@ -165,5 +165,5 @@ void *HELPER(lookup_tb_ptr)(CPUArchState *env) void HELPER(exit_atomic)(CPUArchState *env) { - cpu_loop_exit_atomic(ENV_GET_CPU(env), GETPC()); + cpu_loop_exit_atomic(env_cpu(env), GETPC()); } diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index 20b59f93f4..52d94facf0 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -1732,7 +1732,7 @@ TranslationBlock *tb_gen_code(CPUState *cpu, tcg_func_start(tcg_ctx); - tcg_ctx->cpu = ENV_GET_CPU(env); + tcg_ctx->cpu = env_cpu(env); gen_intermediate_code(cpu, tb, max_insns); tcg_ctx->cpu = NULL; diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c index 8cfbeb1b56..cb5f4b19c5 100644 --- a/accel/tcg/user-exec.c +++ b/accel/tcg/user-exec.c @@ -680,7 +680,7 @@ static void *atomic_mmu_lookup(CPUArchState *env, target_ulong addr, { /* Enforce qemu required alignment. */ if (unlikely(addr & (size - 1))) { - cpu_loop_exit_atomic(ENV_GET_CPU(env), retaddr); + cpu_loop_exit_atomic(env_cpu(env), retaddr); } helper_retaddr = retaddr; return g2h(addr); diff --git a/bsd-user/syscall.c b/bsd-user/syscall.c index 66492aaf5d..1ee6195d9f 100644 --- a/bsd-user/syscall.c +++ b/bsd-user/syscall.c @@ -315,7 +315,7 @@ abi_long do_freebsd_syscall(void *cpu_env, int num, abi_long arg1, abi_long arg5, abi_long arg6, abi_long arg7, abi_long arg8) { - CPUState *cpu = ENV_GET_CPU(cpu_env); + CPUState *cpu = env_cpu(cpu_env); abi_long ret; void *p; @@ -413,7 +413,7 @@ abi_long do_netbsd_syscall(void *cpu_env, int num, abi_long arg1, abi_long arg2, abi_long arg3, abi_long arg4, abi_long arg5, abi_long arg6) { - CPUState *cpu = ENV_GET_CPU(cpu_env); + CPUState *cpu = env_cpu(cpu_env); abi_long ret; void *p; @@ -488,7 +488,7 @@ abi_long do_openbsd_syscall(void *cpu_env, int num, abi_long arg1, abi_long arg2, abi_long arg3, abi_long arg4, abi_long arg5, abi_long arg6) { - CPUState *cpu = ENV_GET_CPU(cpu_env); + CPUState *cpu = env_cpu(cpu_env); abi_long ret; void *p; diff --git a/docs/devel/tracing.txt b/docs/devel/tracing.txt index 056aa56496..76e492a489 100644 --- a/docs/devel/tracing.txt +++ b/docs/devel/tracing.txt @@ -434,9 +434,9 @@ Can be used as: /* trace emitted at this point */ trace_foo(0xd1); /* trace emitted at this point */ - trace_bar(ENV_GET_CPU(env), 0xd2); + trace_bar(env_cpu(env), 0xd2); /* trace emitted at this point (env) and when guest code is executed (cpu_env) */ - trace_baz_tcg(ENV_GET_CPU(env), cpu_env, 0xd3); + trace_baz_tcg(env_cpu(env), cpu_env, 0xd3); } If the translating vCPU has address 0xc1 and code is later executed by vCPU diff --git a/hw/semihosting/console.c b/hw/semihosting/console.c index 466ea6dade..4ab7533bb8 100644 --- a/hw/semihosting/console.c +++ b/hw/semihosting/console.c @@ -40,7 +40,7 @@ int qemu_semihosting_log_out(const char *s, int len) */ static GString *copy_user_string(CPUArchState *env, target_ulong addr, int len) { - CPUState *cpu = ENV_GET_CPU(env); + CPUState *cpu = env_cpu(env); GString *s = g_string_sized_new(len ? len : 128); uint8_t c; bool done; diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h index da07ce311f..454f6d663f 100644 --- a/include/exec/cpu-all.h +++ b/include/exec/cpu-all.h @@ -371,4 +371,16 @@ int cpu_memory_rw_debug(CPUState *cpu, target_ulong addr, int cpu_exec(CPUState *cpu); +/** + * env_cpu(env) + * @env: The architecture environment + * + * Return the CPUState associated with the environment. + */ +static inline CPUState *env_cpu(CPUArchState *env) +{ + ArchCPU *arch_cpu = container_of(env, ArchCPU, env); + return &arch_cpu->parent_obj; +} + #endif /* CPU_ALL_H */ diff --git a/include/exec/cpu_ldst_template.h b/include/exec/cpu_ldst_template.h index 0f061d47ef..af7e0b49f2 100644 --- a/include/exec/cpu_ldst_template.h +++ b/include/exec/cpu_ldst_template.h @@ -89,7 +89,7 @@ glue(glue(glue(cpu_ld, USUFFIX), MEMSUFFIX), _ra)(CPUArchState *env, #if !defined(SOFTMMU_CODE_ACCESS) trace_guest_mem_before_exec( - ENV_GET_CPU(env), ptr, + env_cpu(env), ptr, trace_mem_build_info(SHIFT, false, MO_TE, false)); #endif @@ -128,7 +128,7 @@ glue(glue(glue(cpu_lds, SUFFIX), MEMSUFFIX), _ra)(CPUArchState *env, #if !defined(SOFTMMU_CODE_ACCESS) trace_guest_mem_before_exec( - ENV_GET_CPU(env), ptr, + env_cpu(env), ptr, trace_mem_build_info(SHIFT, true, MO_TE, false)); #endif @@ -170,7 +170,7 @@ glue(glue(glue(cpu_st, SUFFIX), MEMSUFFIX), _ra)(CPUArchState *env, #if !defined(SOFTMMU_CODE_ACCESS) trace_guest_mem_before_exec( - ENV_GET_CPU(env), ptr, + env_cpu(env), ptr, trace_mem_build_info(SHIFT, false, MO_TE, true)); #endif diff --git a/include/exec/cpu_ldst_useronly_template.h b/include/exec/cpu_ldst_useronly_template.h index 0fd6019af0..bc45e2b8d4 100644 --- a/include/exec/cpu_ldst_useronly_template.h +++ b/include/exec/cpu_ldst_useronly_template.h @@ -66,7 +66,7 @@ glue(glue(cpu_ld, USUFFIX), MEMSUFFIX)(CPUArchState *env, abi_ptr ptr) { #if !defined(CODE_ACCESS) trace_guest_mem_before_exec( - ENV_GET_CPU(env), ptr, + env_cpu(env), ptr, trace_mem_build_info(SHIFT, false, MO_TE, false)); #endif return glue(glue(ld, USUFFIX), _p)(g2h(ptr)); @@ -90,7 +90,7 @@ glue(glue(cpu_lds, SUFFIX), MEMSUFFIX)(CPUArchState *env, abi_ptr ptr) { #if !defined(CODE_ACCESS) trace_guest_mem_before_exec( - ENV_GET_CPU(env), ptr, + env_cpu(env), ptr, trace_mem_build_info(SHIFT, true, MO_TE, false)); #endif return glue(glue(lds, SUFFIX), _p)(g2h(ptr)); @@ -116,7 +116,7 @@ glue(glue(cpu_st, SUFFIX), MEMSUFFIX)(CPUArchState *env, abi_ptr ptr, { #if !defined(CODE_ACCESS) trace_guest_mem_before_exec( - ENV_GET_CPU(env), ptr, + env_cpu(env), ptr, trace_mem_build_info(SHIFT, false, MO_TE, true)); #endif glue(glue(st, SUFFIX), _p)(g2h(ptr), v); diff --git a/include/exec/softmmu-semi.h b/include/exec/softmmu-semi.h index 7eefad8f39..970837992e 100644 --- a/include/exec/softmmu-semi.h +++ b/include/exec/softmmu-semi.h @@ -14,7 +14,7 @@ static inline uint64_t softmmu_tget64(CPUArchState *env, target_ulong addr) { uint64_t val; - cpu_memory_rw_debug(ENV_GET_CPU(env), addr, (uint8_t *)&val, 8, 0); + cpu_memory_rw_debug(env_cpu(env), addr, (uint8_t *)&val, 8, 0); return tswap64(val); } @@ -22,7 +22,7 @@ static inline uint32_t softmmu_tget32(CPUArchState *env, target_ulong addr) { uint32_t val; - cpu_memory_rw_debug(ENV_GET_CPU(env), addr, (uint8_t *)&val, 4, 0); + cpu_memory_rw_debug(env_cpu(env), addr, (uint8_t *)&val, 4, 0); return tswap32(val); } @@ -30,7 +30,7 @@ static inline uint32_t softmmu_tget8(CPUArchState *env, target_ulong addr) { uint8_t val; - cpu_memory_rw_debug(ENV_GET_CPU(env), addr, &val, 1, 0); + cpu_memory_rw_debug(env_cpu(env), addr, &val, 1, 0); return val; } @@ -43,14 +43,14 @@ static inline void softmmu_tput64(CPUArchState *env, target_ulong addr, uint64_t val) { val = tswap64(val); - cpu_memory_rw_debug(ENV_GET_CPU(env), addr, (uint8_t *)&val, 8, 1); + cpu_memory_rw_debug(env_cpu(env), addr, (uint8_t *)&val, 8, 1); } static inline void softmmu_tput32(CPUArchState *env, target_ulong addr, uint32_t val) { val = tswap32(val); - cpu_memory_rw_debug(ENV_GET_CPU(env), addr, (uint8_t *)&val, 4, 1); + cpu_memory_rw_debug(env_cpu(env), addr, (uint8_t *)&val, 4, 1); } #define put_user_u64(arg, p) ({ softmmu_tput64(env, p, arg) ; 0; }) #define put_user_u32(arg, p) ({ softmmu_tput32(env, p, arg) ; 0; }) @@ -63,7 +63,7 @@ static void *softmmu_lock_user(CPUArchState *env, /* TODO: Make this something that isn't fixed size. */ p = malloc(len); if (p && copy) { - cpu_memory_rw_debug(ENV_GET_CPU(env), addr, p, len, 0); + cpu_memory_rw_debug(env_cpu(env), addr, p, len, 0); } return p; } @@ -79,7 +79,7 @@ static char *softmmu_lock_user_string(CPUArchState *env, target_ulong addr) return NULL; } do { - cpu_memory_rw_debug(ENV_GET_CPU(env), addr, &c, 1, 0); + cpu_memory_rw_debug(env_cpu(env), addr, &c, 1, 0); addr++; *(p++) = c; } while (c); @@ -90,7 +90,7 @@ static void softmmu_unlock_user(CPUArchState *env, void *p, target_ulong addr, target_ulong len) { if (len) { - cpu_memory_rw_debug(ENV_GET_CPU(env), addr, p, len, 1); + cpu_memory_rw_debug(env_cpu(env), addr, p, len, 1); } free(p); } diff --git a/linux-user/arm/cpu_loop.c b/linux-user/arm/cpu_loop.c index ee68aa60bf..b7e7a6323c 100644 --- a/linux-user/arm/cpu_loop.c +++ b/linux-user/arm/cpu_loop.c @@ -423,7 +423,7 @@ void cpu_loop(CPUARMState *env) void target_cpu_copy_regs(CPUArchState *env, struct target_pt_regs *regs) { - CPUState *cpu = ENV_GET_CPU(env); + CPUState *cpu = env_cpu(env); TaskState *ts = cpu->opaque; struct image_info *info = ts->info; int i; diff --git a/linux-user/cpu_loop-common.h b/linux-user/cpu_loop-common.h index c1d554a249..8828af28a4 100644 --- a/linux-user/cpu_loop-common.h +++ b/linux-user/cpu_loop-common.h @@ -24,7 +24,7 @@ #define EXCP_DUMP(env, fmt, ...) \ do { \ - CPUState *cs = ENV_GET_CPU(env); \ + CPUState *cs = env_cpu(env); \ fprintf(stderr, fmt , ## __VA_ARGS__); \ cpu_dump_state(cs, stderr, 0); \ if (qemu_log_separate()) { \ diff --git a/linux-user/cris/cpu_loop.c b/linux-user/cris/cpu_loop.c index af8c128bf8..7ec36cb0b5 100644 --- a/linux-user/cris/cpu_loop.c +++ b/linux-user/cris/cpu_loop.c @@ -83,7 +83,7 @@ void cpu_loop(CPUCRISState *env) void target_cpu_copy_regs(CPUArchState *env, struct target_pt_regs *regs) { - CPUState *cpu = ENV_GET_CPU(env); + CPUState *cpu = env_cpu(env); TaskState *ts = cpu->opaque; struct image_info *info = ts->info; diff --git a/linux-user/elfload.c b/linux-user/elfload.c index 5451d262ec..9fd65708c4 100644 --- a/linux-user/elfload.c +++ b/linux-user/elfload.c @@ -3377,7 +3377,7 @@ static int write_note(struct memelfnote *men, int fd) static void fill_thread_info(struct elf_note_info *info, const CPUArchState *env) { - CPUState *cpu = ENV_GET_CPU((CPUArchState *)env); + CPUState *cpu = env_cpu((CPUArchState *)env); TaskState *ts = (TaskState *)cpu->opaque; struct elf_thread_status *ets; @@ -3407,7 +3407,7 @@ static int fill_note_info(struct elf_note_info *info, long signr, const CPUArchState *env) { #define NUMNOTES 3 - CPUState *cpu = ENV_GET_CPU((CPUArchState *)env); + CPUState *cpu = env_cpu((CPUArchState *)env); TaskState *ts = (TaskState *)cpu->opaque; int i; @@ -3531,7 +3531,7 @@ static int write_note_info(struct elf_note_info *info, int fd) */ static int elf_core_dump(int signr, const CPUArchState *env) { - const CPUState *cpu = ENV_GET_CPU((CPUArchState *)env); + const CPUState *cpu = env_cpu((CPUArchState *)env); const TaskState *ts = (const TaskState *)cpu->opaque; struct vm_area_struct *vma = NULL; char corefile[PATH_MAX]; diff --git a/linux-user/m68k/cpu_loop.c b/linux-user/m68k/cpu_loop.c index bfb41bbcc5..42d8d841ea 100644 --- a/linux-user/m68k/cpu_loop.c +++ b/linux-user/m68k/cpu_loop.c @@ -130,7 +130,7 @@ void cpu_loop(CPUM68KState *env) void target_cpu_copy_regs(CPUArchState *env, struct target_pt_regs *regs) { - CPUState *cpu = ENV_GET_CPU(env); + CPUState *cpu = env_cpu(env); TaskState *ts = cpu->opaque; struct image_info *info = ts->info; diff --git a/linux-user/main.c b/linux-user/main.c index 689bcf436d..97ca22bb04 100644 --- a/linux-user/main.c +++ b/linux-user/main.c @@ -180,7 +180,7 @@ void init_task_state(TaskState *ts) CPUArchState *cpu_copy(CPUArchState *env) { - CPUState *cpu = ENV_GET_CPU(env); + CPUState *cpu = env_cpu(env); CPUState *new_cpu = cpu_create(cpu_type); CPUArchState *new_env = new_cpu->env_ptr; CPUBreakpoint *bp; diff --git a/linux-user/mips/cpu_loop.c b/linux-user/mips/cpu_loop.c index 61dc90d51c..828137cd84 100644 --- a/linux-user/mips/cpu_loop.c +++ b/linux-user/mips/cpu_loop.c @@ -654,7 +654,7 @@ error: void target_cpu_copy_regs(CPUArchState *env, struct target_pt_regs *regs) { - CPUState *cpu = ENV_GET_CPU(env); + CPUState *cpu = env_cpu(env); TaskState *ts = cpu->opaque; struct image_info *info = ts->info; int i; diff --git a/linux-user/nios2/cpu_loop.c b/linux-user/nios2/cpu_loop.c index 5aa1eca740..9869083fa1 100644 --- a/linux-user/nios2/cpu_loop.c +++ b/linux-user/nios2/cpu_loop.c @@ -23,7 +23,7 @@ void cpu_loop(CPUNios2State *env) { - CPUState *cs = ENV_GET_CPU(env); + CPUState *cs = env_cpu(env); Nios2CPU *cpu = NIOS2_CPU(cs); target_siginfo_t info; int trapnr, ret; diff --git a/linux-user/riscv/cpu_loop.c b/linux-user/riscv/cpu_loop.c index a9bac4ca79..31700f75d0 100644 --- a/linux-user/riscv/cpu_loop.c +++ b/linux-user/riscv/cpu_loop.c @@ -116,7 +116,7 @@ void cpu_loop(CPURISCVState *env) void target_cpu_copy_regs(CPUArchState *env, struct target_pt_regs *regs) { - CPUState *cpu = ENV_GET_CPU(env); + CPUState *cpu = env_cpu(env); TaskState *ts = cpu->opaque; struct image_info *info = ts->info; diff --git a/linux-user/signal.c b/linux-user/signal.c index 44b2d3b35a..7c5588adff 100644 --- a/linux-user/signal.c +++ b/linux-user/signal.c @@ -626,7 +626,7 @@ static void QEMU_NORETURN dump_core_and_abort(int target_sig) int queue_signal(CPUArchState *env, int sig, int si_type, target_siginfo_t *info) { - CPUState *cpu = ENV_GET_CPU(env); + CPUState *cpu = env_cpu(env); TaskState *ts = cpu->opaque; trace_user_queue_signal(env, sig); @@ -651,7 +651,7 @@ static void host_signal_handler(int host_signum, siginfo_t *info, void *puc) { CPUArchState *env = thread_cpu->env_ptr; - CPUState *cpu = ENV_GET_CPU(env); + CPUState *cpu = env_cpu(env); TaskState *ts = cpu->opaque; int sig; @@ -842,7 +842,7 @@ int do_sigaction(int sig, const struct target_sigaction *act, static void handle_pending_signal(CPUArchState *cpu_env, int sig, struct emulated_sigtable *k) { - CPUState *cpu = ENV_GET_CPU(cpu_env); + CPUState *cpu = env_cpu(cpu_env); abi_ulong handler; sigset_t set; target_sigset_t target_old_set; @@ -927,7 +927,7 @@ static void handle_pending_signal(CPUArchState *cpu_env, int sig, void process_pending_signals(CPUArchState *cpu_env) { - CPUState *cpu = ENV_GET_CPU(cpu_env); + CPUState *cpu = env_cpu(cpu_env); int sig; TaskState *ts = cpu->opaque; sigset_t set; diff --git a/linux-user/syscall.c b/linux-user/syscall.c index 5e29e675e9..d1a2c7831f 100644 --- a/linux-user/syscall.c +++ b/linux-user/syscall.c @@ -5484,7 +5484,7 @@ static void *clone_func(void *arg) rcu_register_thread(); tcg_register_thread(); env = info->env; - cpu = ENV_GET_CPU(env); + cpu = env_cpu(env); thread_cpu = cpu; ts = (TaskState *)cpu->opaque; info->tid = sys_gettid(); @@ -5514,7 +5514,7 @@ static int do_fork(CPUArchState *env, unsigned int flags, abi_ulong newsp, abi_ulong parent_tidptr, target_ulong newtls, abi_ulong child_tidptr) { - CPUState *cpu = ENV_GET_CPU(env); + CPUState *cpu = env_cpu(env); int ret; TaskState *ts; CPUState *new_cpu; @@ -5547,7 +5547,7 @@ static int do_fork(CPUArchState *env, unsigned int flags, abi_ulong newsp, new_env = cpu_copy(env); /* Init regs that differ from the parent. */ cpu_clone_regs(new_env, newsp); - new_cpu = ENV_GET_CPU(new_env); + new_cpu = env_cpu(new_env); new_cpu->opaque = ts; ts->bprm = parent_ts->bprm; ts->info = parent_ts->info; @@ -6654,7 +6654,7 @@ int host_to_target_waitstatus(int status) static int open_self_cmdline(void *cpu_env, int fd) { - CPUState *cpu = ENV_GET_CPU((CPUArchState *)cpu_env); + CPUState *cpu = env_cpu((CPUArchState *)cpu_env); struct linux_binprm *bprm = ((TaskState *)cpu->opaque)->bprm; int i; @@ -6671,7 +6671,7 @@ static int open_self_cmdline(void *cpu_env, int fd) static int open_self_maps(void *cpu_env, int fd) { - CPUState *cpu = ENV_GET_CPU((CPUArchState *)cpu_env); + CPUState *cpu = env_cpu((CPUArchState *)cpu_env); TaskState *ts = cpu->opaque; FILE *fp; char *line = NULL; @@ -6720,7 +6720,7 @@ static int open_self_maps(void *cpu_env, int fd) static int open_self_stat(void *cpu_env, int fd) { - CPUState *cpu = ENV_GET_CPU((CPUArchState *)cpu_env); + CPUState *cpu = env_cpu((CPUArchState *)cpu_env); TaskState *ts = cpu->opaque; abi_ulong start_stack = ts->info->start_stack; int i; @@ -6757,7 +6757,7 @@ static int open_self_stat(void *cpu_env, int fd) static int open_self_auxv(void *cpu_env, int fd) { - CPUState *cpu = ENV_GET_CPU((CPUArchState *)cpu_env); + CPUState *cpu = env_cpu((CPUArchState *)cpu_env); TaskState *ts = cpu->opaque; abi_ulong auxv = ts->info->saved_auxv; abi_ulong len = ts->info->auxv_len; @@ -7042,7 +7042,7 @@ static abi_long do_syscall1(void *cpu_env, int num, abi_long arg1, abi_long arg5, abi_long arg6, abi_long arg7, abi_long arg8) { - CPUState *cpu = ENV_GET_CPU(cpu_env); + CPUState *cpu = env_cpu(cpu_env); abi_long ret; #if defined(TARGET_NR_stat) || defined(TARGET_NR_stat64) \ || defined(TARGET_NR_lstat) || defined(TARGET_NR_lstat64) \ @@ -11706,7 +11706,7 @@ abi_long do_syscall(void *cpu_env, int num, abi_long arg1, abi_long arg5, abi_long arg6, abi_long arg7, abi_long arg8) { - CPUState *cpu = ENV_GET_CPU(cpu_env); + CPUState *cpu = env_cpu(cpu_env); abi_long ret; #ifdef DEBUG_ERESTARTSYS diff --git a/linux-user/uname.c b/linux-user/uname.c index 1c05f95387..a09ffe1ea7 100644 --- a/linux-user/uname.c +++ b/linux-user/uname.c @@ -54,7 +54,7 @@ const char *cpu_to_uname_machine(void *cpu_env) return "armv5te" utsname_suffix; #elif defined(TARGET_I386) && !defined(TARGET_X86_64) /* see arch/x86/kernel/cpu/bugs.c: check_bugs(), 386, 486, 586, 686 */ - CPUState *cpu = ENV_GET_CPU((CPUX86State *)cpu_env); + CPUState *cpu = env_cpu((CPUX86State *)cpu_env); int family = object_property_get_int(OBJECT(cpu), "family", NULL); if (family == 4) { return "i486"; diff --git a/scripts/tracetool/format/tcg_helper_c.py b/scripts/tracetool/format/tcg_helper_c.py index bbbd6ad0f4..79aa63eada 100644 --- a/scripts/tracetool/format/tcg_helper_c.py +++ b/scripts/tracetool/format/tcg_helper_c.py @@ -25,7 +25,7 @@ def vcpu_transform_args(args, mode): if mode == "code": return Arguments([ # Does cast from helper requirements to tracing types - ("CPUState *", "ENV_GET_CPU(%s)" % args.names()[0]), + ("CPUState *", "env_cpu(%s)" % args.names()[0]), ]) else: args = Arguments([ diff --git a/target/alpha/cpu.h b/target/alpha/cpu.h index 5af0b6c542..e391195be0 100644 --- a/target/alpha/cpu.h +++ b/target/alpha/cpu.h @@ -283,8 +283,6 @@ static inline AlphaCPU *alpha_env_get_cpu(CPUAlphaState *env) return container_of(env, AlphaCPU, env); } -#define ENV_GET_CPU(e) CPU(alpha_env_get_cpu(e)) - #define ENV_OFFSET offsetof(AlphaCPU, env) #ifndef CONFIG_USER_ONLY diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 4ebb6349f1..1afd1da491 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -922,8 +922,6 @@ void arm_cpu_post_init(Object *obj); uint64_t arm_cpu_mp_affinity(int idx, uint8_t clustersz); -#define ENV_GET_CPU(e) CPU(arm_env_get_cpu(e)) - #define ENV_OFFSET offsetof(ARMCPU, env) #ifndef CONFIG_USER_ONLY diff --git a/target/arm/helper.c b/target/arm/helper.c index 719fb92e60..f23989febf 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -587,7 +587,7 @@ static void contextidr_write(CPUARMState *env, const ARMCPRegInfo *ri, static void tlbiall_is_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { - CPUState *cs = ENV_GET_CPU(env); + CPUState *cs = env_cpu(env); tlb_flush_all_cpus_synced(cs); } @@ -595,7 +595,7 @@ static void tlbiall_is_write(CPUARMState *env, const ARMCPRegInfo *ri, static void tlbiasid_is_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { - CPUState *cs = ENV_GET_CPU(env); + CPUState *cs = env_cpu(env); tlb_flush_all_cpus_synced(cs); } @@ -603,7 +603,7 @@ static void tlbiasid_is_write(CPUARMState *env, const ARMCPRegInfo *ri, static void tlbimva_is_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { - CPUState *cs = ENV_GET_CPU(env); + CPUState *cs = env_cpu(env); tlb_flush_page_all_cpus_synced(cs, value & TARGET_PAGE_MASK); } @@ -611,7 +611,7 @@ static void tlbimva_is_write(CPUARMState *env, const ARMCPRegInfo *ri, static void tlbimvaa_is_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { - CPUState *cs = ENV_GET_CPU(env); + CPUState *cs = env_cpu(env); tlb_flush_page_all_cpus_synced(cs, value & TARGET_PAGE_MASK); } @@ -686,7 +686,7 @@ static void tlbimvaa_write(CPUARMState *env, const ARMCPRegInfo *ri, static void tlbiall_nsnh_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { - CPUState *cs = ENV_GET_CPU(env); + CPUState *cs = env_cpu(env); tlb_flush_by_mmuidx(cs, ARMMMUIdxBit_S12NSE1 | @@ -697,7 +697,7 @@ static void tlbiall_nsnh_write(CPUARMState *env, const ARMCPRegInfo *ri, static void tlbiall_nsnh_is_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { - CPUState *cs = ENV_GET_CPU(env); + CPUState *cs = env_cpu(env); tlb_flush_by_mmuidx_all_cpus_synced(cs, ARMMMUIdxBit_S12NSE1 | @@ -714,7 +714,7 @@ static void tlbiipas2_write(CPUARMState *env, const ARMCPRegInfo *ri, * translation information. * This must NOP if EL2 isn't implemented or SCR_EL3.NS is zero. */ - CPUState *cs = ENV_GET_CPU(env); + CPUState *cs = env_cpu(env); uint64_t pageaddr; if (!arm_feature(env, ARM_FEATURE_EL2) || !(env->cp15.scr_el3 & SCR_NS)) { @@ -729,7 +729,7 @@ static void tlbiipas2_write(CPUARMState *env, const ARMCPRegInfo *ri, static void tlbiipas2_is_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { - CPUState *cs = ENV_GET_CPU(env); + CPUState *cs = env_cpu(env); uint64_t pageaddr; if (!arm_feature(env, ARM_FEATURE_EL2) || !(env->cp15.scr_el3 & SCR_NS)) { @@ -745,7 +745,7 @@ static void tlbiipas2_is_write(CPUARMState *env, const ARMCPRegInfo *ri, static void tlbiall_hyp_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { - CPUState *cs = ENV_GET_CPU(env); + CPUState *cs = env_cpu(env); tlb_flush_by_mmuidx(cs, ARMMMUIdxBit_S1E2); } @@ -753,7 +753,7 @@ static void tlbiall_hyp_write(CPUARMState *env, const ARMCPRegInfo *ri, static void tlbiall_hyp_is_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { - CPUState *cs = ENV_GET_CPU(env); + CPUState *cs = env_cpu(env); tlb_flush_by_mmuidx_all_cpus_synced(cs, ARMMMUIdxBit_S1E2); } @@ -761,7 +761,7 @@ static void tlbiall_hyp_is_write(CPUARMState *env, const ARMCPRegInfo *ri, static void tlbimva_hyp_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { - CPUState *cs = ENV_GET_CPU(env); + CPUState *cs = env_cpu(env); uint64_t pageaddr = value & ~MAKE_64BIT_MASK(0, 12); tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdxBit_S1E2); @@ -770,7 +770,7 @@ static void tlbimva_hyp_write(CPUARMState *env, const ARMCPRegInfo *ri, static void tlbimva_hyp_is_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { - CPUState *cs = ENV_GET_CPU(env); + CPUState *cs = env_cpu(env); uint64_t pageaddr = value & ~MAKE_64BIT_MASK(0, 12); tlb_flush_page_by_mmuidx_all_cpus_synced(cs, pageaddr, @@ -1921,7 +1921,7 @@ static void csselr_write(CPUARMState *env, const ARMCPRegInfo *ri, static uint64_t isr_read(CPUARMState *env, const ARMCPRegInfo *ri) { - CPUState *cs = ENV_GET_CPU(env); + CPUState *cs = env_cpu(env); uint64_t hcr_el2 = arm_hcr_el2_eff(env); uint64_t ret = 0; @@ -3773,7 +3773,7 @@ static CPAccessResult aa64_cacheop_access(CPUARMState *env, static void tlbi_aa64_vmalle1is_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { - CPUState *cs = ENV_GET_CPU(env); + CPUState *cs = env_cpu(env); bool sec = arm_is_secure_below_el3(env); if (sec) { @@ -3790,7 +3790,7 @@ static void tlbi_aa64_vmalle1is_write(CPUARMState *env, const ARMCPRegInfo *ri, static void tlbi_aa64_vmalle1_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { - CPUState *cs = ENV_GET_CPU(env); + CPUState *cs = env_cpu(env); if (tlb_force_broadcast(env)) { tlbi_aa64_vmalle1is_write(env, NULL, value); @@ -3861,7 +3861,7 @@ static void tlbi_aa64_alle1is_write(CPUARMState *env, const ARMCPRegInfo *ri, * stage 2 translations, whereas most other scopes only invalidate * stage 1 translations. */ - CPUState *cs = ENV_GET_CPU(env); + CPUState *cs = env_cpu(env); bool sec = arm_is_secure_below_el3(env); bool has_el2 = arm_feature(env, ARM_FEATURE_EL2); @@ -3884,7 +3884,7 @@ static void tlbi_aa64_alle1is_write(CPUARMState *env, const ARMCPRegInfo *ri, static void tlbi_aa64_alle2is_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { - CPUState *cs = ENV_GET_CPU(env); + CPUState *cs = env_cpu(env); tlb_flush_by_mmuidx_all_cpus_synced(cs, ARMMMUIdxBit_S1E2); } @@ -3892,7 +3892,7 @@ static void tlbi_aa64_alle2is_write(CPUARMState *env, const ARMCPRegInfo *ri, static void tlbi_aa64_alle3is_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { - CPUState *cs = ENV_GET_CPU(env); + CPUState *cs = env_cpu(env); tlb_flush_by_mmuidx_all_cpus_synced(cs, ARMMMUIdxBit_S1E3); } @@ -3975,7 +3975,7 @@ static void tlbi_aa64_vae1_write(CPUARMState *env, const ARMCPRegInfo *ri, static void tlbi_aa64_vae2is_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { - CPUState *cs = ENV_GET_CPU(env); + CPUState *cs = env_cpu(env); uint64_t pageaddr = sextract64(value << 12, 0, 56); tlb_flush_page_by_mmuidx_all_cpus_synced(cs, pageaddr, @@ -3985,7 +3985,7 @@ static void tlbi_aa64_vae2is_write(CPUARMState *env, const ARMCPRegInfo *ri, static void tlbi_aa64_vae3is_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { - CPUState *cs = ENV_GET_CPU(env); + CPUState *cs = env_cpu(env); uint64_t pageaddr = sextract64(value << 12, 0, 56); tlb_flush_page_by_mmuidx_all_cpus_synced(cs, pageaddr, @@ -4017,7 +4017,7 @@ static void tlbi_aa64_ipas2e1_write(CPUARMState *env, const ARMCPRegInfo *ri, static void tlbi_aa64_ipas2e1is_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { - CPUState *cs = ENV_GET_CPU(env); + CPUState *cs = env_cpu(env); uint64_t pageaddr; if (!arm_feature(env, ARM_FEATURE_EL2) || !(env->cp15.scr_el3 & SCR_NS)) { diff --git a/target/cris/cpu.h b/target/cris/cpu.h index e978eb9539..0746d19f38 100644 --- a/target/cris/cpu.h +++ b/target/cris/cpu.h @@ -188,8 +188,6 @@ static inline CRISCPU *cris_env_get_cpu(CPUCRISState *env) return container_of(env, CRISCPU, env); } -#define ENV_GET_CPU(e) CPU(cris_env_get_cpu(e)) - #define ENV_OFFSET offsetof(CRISCPU, env) #ifndef CONFIG_USER_ONLY diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h index 6eef107370..0cb1fc8800 100644 --- a/target/hppa/cpu.h +++ b/target/hppa/cpu.h @@ -227,7 +227,6 @@ static inline HPPACPU *hppa_env_get_cpu(CPUHPPAState *env) return container_of(env, HPPACPU, env); } -#define ENV_GET_CPU(e) CPU(hppa_env_get_cpu(e)) #define ENV_OFFSET offsetof(HPPACPU, env) typedef CPUHPPAState CPUArchState; diff --git a/target/hppa/op_helper.c b/target/hppa/op_helper.c index a55a5dfc02..952e97a7d7 100644 --- a/target/hppa/op_helper.c +++ b/target/hppa/op_helper.c @@ -77,7 +77,7 @@ static void atomic_store_3(CPUHPPAState *env, target_ulong addr, uint32_t val, } #else /* FIXME -- we can do better. */ - cpu_loop_exit_atomic(ENV_GET_CPU(env), ra); + cpu_loop_exit_atomic(env_cpu(env), ra); #endif } diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 65f8f4d16c..103fd709b0 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -1485,8 +1485,6 @@ static inline X86CPU *x86_env_get_cpu(CPUX86State *env) return container_of(env, X86CPU, env); } -#define ENV_GET_CPU(e) CPU(x86_env_get_cpu(e)) - #define ENV_OFFSET offsetof(X86CPU, env) #ifndef CONFIG_USER_ONLY diff --git a/target/i386/hax-all.c b/target/i386/hax-all.c index 44b89c1d74..64fd51ad4a 100644 --- a/target/i386/hax-all.c +++ b/target/i386/hax-all.c @@ -67,7 +67,7 @@ int valid_hax_tunnel_size(uint16_t size) hax_fd hax_vcpu_get_fd(CPUArchState *env) { - struct hax_vcpu_state *vcpu = ENV_GET_CPU(env)->hax_vcpu; + struct hax_vcpu_state *vcpu = env_cpu(env)->hax_vcpu; if (!vcpu) { return HAX_INVALID_FD; } @@ -409,7 +409,7 @@ static int hax_handle_io(CPUArchState *env, uint32_t df, uint16_t port, static int hax_vcpu_interrupt(CPUArchState *env) { - CPUState *cpu = ENV_GET_CPU(env); + CPUState *cpu = env_cpu(env); struct hax_vcpu_state *vcpu = cpu->hax_vcpu; struct hax_tunnel *ht = vcpu->tunnel; @@ -461,7 +461,7 @@ void hax_raise_event(CPUState *cpu) static int hax_vcpu_hax_exec(CPUArchState *env) { int ret = 0; - CPUState *cpu = ENV_GET_CPU(env); + CPUState *cpu = env_cpu(env); X86CPU *x86_cpu = X86_CPU(cpu); struct hax_vcpu_state *vcpu = cpu->hax_vcpu; struct hax_tunnel *ht = vcpu->tunnel; diff --git a/target/i386/hvf/x86_decode.c b/target/i386/hvf/x86_decode.c index 9ef7d7513f..822fa1866e 100644 --- a/target/i386/hvf/x86_decode.c +++ b/target/i386/hvf/x86_decode.c @@ -75,8 +75,8 @@ static inline uint64_t decode_bytes(CPUX86State *env, struct x86_decode *decode, VM_PANIC_EX("%s invalid size %d\n", __func__, size); break; } - target_ulong va = linear_rip(ENV_GET_CPU(env), RIP(env)) + decode->len; - vmx_read_mem(ENV_GET_CPU(env), &val, va, size); + target_ulong va = linear_rip(env_cpu(env), RIP(env)) + decode->len; + vmx_read_mem(env_cpu(env), &val, va, size); decode->len += size; return val; @@ -1772,7 +1772,7 @@ void calc_modrm_operand32(CPUX86State *env, struct x86_decode *decode, if (4 == decode->modrm.rm) { ptr += get_sib_val(env, decode, &seg); } else if (!decode->modrm.mod && 5 == decode->modrm.rm) { - if (x86_is_long_mode(ENV_GET_CPU(env))) { + if (x86_is_long_mode(env_cpu(env))) { ptr += RIP(env) + decode->len; } else { ptr = decode->displacement; @@ -1877,7 +1877,7 @@ static void decode_prefix(CPUX86State *env, struct x86_decode *decode) decode->addr_size_override = byte; break; case PREFIX_REX ... (PREFIX_REX + 0xf): - if (x86_is_long_mode(ENV_GET_CPU(env))) { + if (x86_is_long_mode(env_cpu(env))) { decode->rex.rex = byte; break; } @@ -1892,16 +1892,16 @@ static void decode_prefix(CPUX86State *env, struct x86_decode *decode) void set_addressing_size(CPUX86State *env, struct x86_decode *decode) { decode->addressing_size = -1; - if (x86_is_real(ENV_GET_CPU(env)) || x86_is_v8086(ENV_GET_CPU(env))) { + if (x86_is_real(env_cpu(env)) || x86_is_v8086(env_cpu(env))) { if (decode->addr_size_override) { decode->addressing_size = 4; } else { decode->addressing_size = 2; } - } else if (!x86_is_long_mode(ENV_GET_CPU(env))) { + } else if (!x86_is_long_mode(env_cpu(env))) { /* protected */ struct vmx_segment cs; - vmx_read_segment_descriptor(ENV_GET_CPU(env), &cs, R_CS); + vmx_read_segment_descriptor(env_cpu(env), &cs, R_CS); /* check db */ if ((cs.ar >> 14) & 1) { if (decode->addr_size_override) { @@ -1929,16 +1929,16 @@ void set_addressing_size(CPUX86State *env, struct x86_decode *decode) void set_operand_size(CPUX86State *env, struct x86_decode *decode) { decode->operand_size = -1; - if (x86_is_real(ENV_GET_CPU(env)) || x86_is_v8086(ENV_GET_CPU(env))) { + if (x86_is_real(env_cpu(env)) || x86_is_v8086(env_cpu(env))) { if (decode->op_size_override) { decode->operand_size = 4; } else { decode->operand_size = 2; } - } else if (!x86_is_long_mode(ENV_GET_CPU(env))) { + } else if (!x86_is_long_mode(env_cpu(env))) { /* protected */ struct vmx_segment cs; - vmx_read_segment_descriptor(ENV_GET_CPU(env), &cs, R_CS); + vmx_read_segment_descriptor(env_cpu(env), &cs, R_CS); /* check db */ if ((cs.ar >> 14) & 1) { if (decode->op_size_override) { @@ -2188,5 +2188,5 @@ target_ulong decode_linear_addr(CPUX86State *env, struct x86_decode *decode, default: break; } - return linear_addr_size(ENV_GET_CPU(env), addr, decode->addressing_size, seg); + return linear_addr_size(env_cpu(env), addr, decode->addressing_size, seg); } diff --git a/target/i386/hvf/x86_emu.c b/target/i386/hvf/x86_emu.c index 3ea18edc68..1b04bd7e94 100644 --- a/target/i386/hvf/x86_emu.c +++ b/target/i386/hvf/x86_emu.c @@ -182,12 +182,12 @@ void write_val_ext(struct CPUX86State *env, target_ulong ptr, target_ulong val, write_val_to_reg(ptr, val, size); return; } - vmx_write_mem(ENV_GET_CPU(env), ptr, &val, size); + vmx_write_mem(env_cpu(env), ptr, &val, size); } uint8_t *read_mmio(struct CPUX86State *env, target_ulong ptr, int bytes) { - vmx_read_mem(ENV_GET_CPU(env), env->hvf_emul->mmio_buf, ptr, bytes); + vmx_read_mem(env_cpu(env), env->hvf_emul->mmio_buf, ptr, bytes); return env->hvf_emul->mmio_buf; } @@ -399,17 +399,18 @@ static void exec_out(struct CPUX86State *env, struct x86_decode *decode) { switch (decode->opcode[0]) { case 0xe6: - hvf_handle_io(ENV_GET_CPU(env), decode->op[0].val, &AL(env), 1, 1, 1); + hvf_handle_io(env_cpu(env), decode->op[0].val, &AL(env), 1, 1, 1); break; case 0xe7: - hvf_handle_io(ENV_GET_CPU(env), decode->op[0].val, &RAX(env), 1, + hvf_handle_io(env_cpu(env), decode->op[0].val, &RAX(env), 1, decode->operand_size, 1); break; case 0xee: - hvf_handle_io(ENV_GET_CPU(env), DX(env), &AL(env), 1, 1, 1); + hvf_handle_io(env_cpu(env), DX(env), &AL(env), 1, 1, 1); break; case 0xef: - hvf_handle_io(ENV_GET_CPU(env), DX(env), &RAX(env), 1, decode->operand_size, 1); + hvf_handle_io(env_cpu(env), DX(env), &RAX(env), 1, + decode->operand_size, 1); break; default: VM_PANIC("Bad out opcode\n"); @@ -423,10 +424,11 @@ static void exec_in(struct CPUX86State *env, struct x86_decode *decode) target_ulong val = 0; switch (decode->opcode[0]) { case 0xe4: - hvf_handle_io(ENV_GET_CPU(env), decode->op[0].val, &AL(env), 0, 1, 1); + hvf_handle_io(env_cpu(env), decode->op[0].val, &AL(env), 0, 1, 1); break; case 0xe5: - hvf_handle_io(ENV_GET_CPU(env), decode->op[0].val, &val, 0, decode->operand_size, 1); + hvf_handle_io(env_cpu(env), decode->op[0].val, &val, 0, + decode->operand_size, 1); if (decode->operand_size == 2) { AX(env) = val; } else { @@ -434,10 +436,10 @@ static void exec_in(struct CPUX86State *env, struct x86_decode *decode) } break; case 0xec: - hvf_handle_io(ENV_GET_CPU(env), DX(env), &AL(env), 0, 1, 1); + hvf_handle_io(env_cpu(env), DX(env), &AL(env), 0, 1, 1); break; case 0xed: - hvf_handle_io(ENV_GET_CPU(env), DX(env), &val, 0, decode->operand_size, 1); + hvf_handle_io(env_cpu(env), DX(env), &val, 0, decode->operand_size, 1); if (decode->operand_size == 2) { AX(env) = val; } else { @@ -484,12 +486,13 @@ static inline void string_rep(struct CPUX86State *env, struct x86_decode *decode static void exec_ins_single(struct CPUX86State *env, struct x86_decode *decode) { - target_ulong addr = linear_addr_size(ENV_GET_CPU(env), RDI(env), decode->addressing_size, - R_ES); + target_ulong addr = linear_addr_size(env_cpu(env), RDI(env), + decode->addressing_size, R_ES); - hvf_handle_io(ENV_GET_CPU(env), DX(env), env->hvf_emul->mmio_buf, 0, + hvf_handle_io(env_cpu(env), DX(env), env->hvf_emul->mmio_buf, 0, decode->operand_size, 1); - vmx_write_mem(ENV_GET_CPU(env), addr, env->hvf_emul->mmio_buf, decode->operand_size); + vmx_write_mem(env_cpu(env), addr, env->hvf_emul->mmio_buf, + decode->operand_size); string_increment_reg(env, R_EDI, decode); } @@ -509,8 +512,9 @@ static void exec_outs_single(struct CPUX86State *env, struct x86_decode *decode) { target_ulong addr = decode_linear_addr(env, decode, RSI(env), R_DS); - vmx_read_mem(ENV_GET_CPU(env), env->hvf_emul->mmio_buf, addr, decode->operand_size); - hvf_handle_io(ENV_GET_CPU(env), DX(env), env->hvf_emul->mmio_buf, 1, + vmx_read_mem(env_cpu(env), env->hvf_emul->mmio_buf, addr, + decode->operand_size); + hvf_handle_io(env_cpu(env), DX(env), env->hvf_emul->mmio_buf, 1, decode->operand_size, 1); string_increment_reg(env, R_ESI, decode); @@ -534,8 +538,8 @@ static void exec_movs_single(struct CPUX86State *env, struct x86_decode *decode) target_ulong val; src_addr = decode_linear_addr(env, decode, RSI(env), R_DS); - dst_addr = linear_addr_size(ENV_GET_CPU(env), RDI(env), decode->addressing_size, - R_ES); + dst_addr = linear_addr_size(env_cpu(env), RDI(env), + decode->addressing_size, R_ES); val = read_val_ext(env, src_addr, decode->operand_size); write_val_ext(env, dst_addr, val, decode->operand_size); @@ -561,8 +565,8 @@ static void exec_cmps_single(struct CPUX86State *env, struct x86_decode *decode) target_ulong dst_addr; src_addr = decode_linear_addr(env, decode, RSI(env), R_DS); - dst_addr = linear_addr_size(ENV_GET_CPU(env), RDI(env), decode->addressing_size, - R_ES); + dst_addr = linear_addr_size(env_cpu(env), RDI(env), + decode->addressing_size, R_ES); decode->op[0].type = X86_VAR_IMMEDIATE; decode->op[0].val = read_val_ext(env, src_addr, decode->operand_size); @@ -591,9 +595,10 @@ static void exec_stos_single(struct CPUX86State *env, struct x86_decode *decode) target_ulong addr; target_ulong val; - addr = linear_addr_size(ENV_GET_CPU(env), RDI(env), decode->addressing_size, R_ES); + addr = linear_addr_size(env_cpu(env), RDI(env), + decode->addressing_size, R_ES); val = read_reg(env, R_EAX, decode->operand_size); - vmx_write_mem(ENV_GET_CPU(env), addr, &val, decode->operand_size); + vmx_write_mem(env_cpu(env), addr, &val, decode->operand_size); string_increment_reg(env, R_EDI, decode); } @@ -614,9 +619,10 @@ static void exec_scas_single(struct CPUX86State *env, struct x86_decode *decode) { target_ulong addr; - addr = linear_addr_size(ENV_GET_CPU(env), RDI(env), decode->addressing_size, R_ES); + addr = linear_addr_size(env_cpu(env), RDI(env), + decode->addressing_size, R_ES); decode->op[1].type = X86_VAR_IMMEDIATE; - vmx_read_mem(ENV_GET_CPU(env), &decode->op[1].val, addr, decode->operand_size); + vmx_read_mem(env_cpu(env), &decode->op[1].val, addr, decode->operand_size); EXEC_2OP_FLAGS_CMD(env, decode, -, SET_FLAGS_OSZAPC_SUB, false); string_increment_reg(env, R_EDI, decode); @@ -641,7 +647,7 @@ static void exec_lods_single(struct CPUX86State *env, struct x86_decode *decode) target_ulong val = 0; addr = decode_linear_addr(env, decode, RSI(env), R_DS); - vmx_read_mem(ENV_GET_CPU(env), &val, addr, decode->operand_size); + vmx_read_mem(env_cpu(env), &val, addr, decode->operand_size); write_reg(env, R_EAX, val, decode->operand_size); string_increment_reg(env, R_ESI, decode); @@ -753,7 +759,7 @@ void simulate_rdmsr(struct CPUState *cpu) static void exec_rdmsr(struct CPUX86State *env, struct x86_decode *decode) { - simulate_rdmsr(ENV_GET_CPU(env)); + simulate_rdmsr(env_cpu(env)); RIP(env) += decode->len; } @@ -851,7 +857,7 @@ void simulate_wrmsr(struct CPUState *cpu) static void exec_wrmsr(struct CPUX86State *env, struct x86_decode *decode) { - simulate_wrmsr(ENV_GET_CPU(env)); + simulate_wrmsr(env_cpu(env)); RIP(env) += decode->len; } diff --git a/target/i386/mem_helper.c b/target/i386/mem_helper.c index 1885df29d2..d50d4b0c40 100644 --- a/target/i386/mem_helper.c +++ b/target/i386/mem_helper.c @@ -89,7 +89,7 @@ void helper_cmpxchg8b(CPUX86State *env, target_ulong a0) } CC_SRC = eflags; #else - cpu_loop_exit_atomic(ENV_GET_CPU(env), GETPC()); + cpu_loop_exit_atomic(env_cpu(env), GETPC()); #endif /* CONFIG_ATOMIC64 */ } @@ -158,7 +158,7 @@ void helper_cmpxchg16b(CPUX86State *env, target_ulong a0) } CC_SRC = eflags; } else { - cpu_loop_exit_atomic(ENV_GET_CPU(env), ra); + cpu_loop_exit_atomic(env_cpu(env), ra); } } #endif diff --git a/target/lm32/cpu.h b/target/lm32/cpu.h index 08c360bd16..ad9452eb9f 100644 --- a/target/lm32/cpu.h +++ b/target/lm32/cpu.h @@ -200,8 +200,6 @@ static inline LM32CPU *lm32_env_get_cpu(CPULM32State *env) return container_of(env, LM32CPU, env); } -#define ENV_GET_CPU(e) CPU(lm32_env_get_cpu(e)) - #define ENV_OFFSET offsetof(LM32CPU, env) #ifndef CONFIG_USER_ONLY diff --git a/target/m68k/cpu.h b/target/m68k/cpu.h index 1d30b73bdf..2e53cde076 100644 --- a/target/m68k/cpu.h +++ b/target/m68k/cpu.h @@ -168,8 +168,6 @@ static inline M68kCPU *m68k_env_get_cpu(CPUM68KState *env) return container_of(env, M68kCPU, env); } -#define ENV_GET_CPU(e) CPU(m68k_env_get_cpu(e)) - #define ENV_OFFSET offsetof(M68kCPU, env) void m68k_cpu_do_interrupt(CPUState *cpu); diff --git a/target/m68k/op_helper.c b/target/m68k/op_helper.c index bde2d551ff..3d1aa23a02 100644 --- a/target/m68k/op_helper.c +++ b/target/m68k/op_helper.c @@ -781,7 +781,7 @@ static void do_cas2l(CPUM68KState *env, uint32_t regs, uint32_t a1, uint32_t a2, #endif { /* Tell the main loop we need to serialize this insn. */ - cpu_loop_exit_atomic(ENV_GET_CPU(env), ra); + cpu_loop_exit_atomic(env_cpu(env), ra); } } else { /* We're executing in a serial context -- no need to be atomic. */ diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h index 5a7fe3cbf8..6e68e00e1f 100644 --- a/target/microblaze/cpu.h +++ b/target/microblaze/cpu.h @@ -315,8 +315,6 @@ static inline MicroBlazeCPU *mb_env_get_cpu(CPUMBState *env) return container_of(env, MicroBlazeCPU, env); } -#define ENV_GET_CPU(e) CPU(mb_env_get_cpu(e)) - #define ENV_OFFSET offsetof(MicroBlazeCPU, env) void mb_cpu_do_interrupt(CPUState *cs); diff --git a/target/mips/cpu.h b/target/mips/cpu.h index 12527ca104..e684572dda 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -1076,8 +1076,6 @@ static inline MIPSCPU *mips_env_get_cpu(CPUMIPSState *env) return container_of(env, MIPSCPU, env); } -#define ENV_GET_CPU(e) CPU(mips_env_get_cpu(e)) - #define ENV_OFFSET offsetof(MIPSCPU, env) void mips_cpu_list(void); diff --git a/target/moxie/cpu.h b/target/moxie/cpu.h index b27b0eabae..275fb9bfbb 100644 --- a/target/moxie/cpu.h +++ b/target/moxie/cpu.h @@ -95,8 +95,6 @@ static inline MoxieCPU *moxie_env_get_cpu(CPUMoxieState *env) return container_of(env, MoxieCPU, env); } -#define ENV_GET_CPU(e) CPU(moxie_env_get_cpu(e)) - #define ENV_OFFSET offsetof(MoxieCPU, env) void moxie_cpu_do_interrupt(CPUState *cs); diff --git a/target/nios2/cpu.h b/target/nios2/cpu.h index 5e51f1ae3f..ae6cf1b4d1 100644 --- a/target/nios2/cpu.h +++ b/target/nios2/cpu.h @@ -199,8 +199,6 @@ static inline Nios2CPU *nios2_env_get_cpu(CPUNios2State *env) return NIOS2_CPU(container_of(env, Nios2CPU, env)); } -#define ENV_GET_CPU(e) CPU(nios2_env_get_cpu(e)) - #define ENV_OFFSET offsetof(Nios2CPU, env) void nios2_tcg_init(void); diff --git a/target/nios2/mmu.c b/target/nios2/mmu.c index 47fa474efb..53ed6413b4 100644 --- a/target/nios2/mmu.c +++ b/target/nios2/mmu.c @@ -102,7 +102,7 @@ unsigned int mmu_translate(CPUNios2State *env, static void mmu_flush_pid(CPUNios2State *env, uint32_t pid) { - CPUState *cs = ENV_GET_CPU(env); + CPUState *cs = env_cpu(env); Nios2CPU *cpu = nios2_env_get_cpu(env); int idx; MMU_LOG(qemu_log("TLB Flush PID %d\n", pid)); @@ -126,7 +126,7 @@ static void mmu_flush_pid(CPUNios2State *env, uint32_t pid) void mmu_write(CPUNios2State *env, uint32_t rn, uint32_t v) { - CPUState *cs = ENV_GET_CPU(env); + CPUState *cs = env_cpu(env); Nios2CPU *cpu = nios2_env_get_cpu(env); MMU_LOG(qemu_log("mmu_write %08X = %08X\n", rn, v)); diff --git a/target/nios2/op_helper.c b/target/nios2/op_helper.c index 529ec6ac0e..a60730faac 100644 --- a/target/nios2/op_helper.c +++ b/target/nios2/op_helper.c @@ -46,7 +46,7 @@ void helper_check_interrupts(CPUNios2State *env) void helper_raise_exception(CPUNios2State *env, uint32_t index) { - CPUState *cs = ENV_GET_CPU(env); + CPUState *cs = env_cpu(env); cs->exception_index = index; cpu_loop_exit(cs); } diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h index 496895693e..50f79d540b 100644 --- a/target/openrisc/cpu.h +++ b/target/openrisc/cpu.h @@ -322,8 +322,6 @@ static inline OpenRISCCPU *openrisc_env_get_cpu(CPUOpenRISCState *env) return container_of(env, OpenRISCCPU, env); } -#define ENV_GET_CPU(e) CPU(openrisc_env_get_cpu(e)) - #define ENV_OFFSET offsetof(OpenRISCCPU, env) void cpu_openrisc_list(void); diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index 17e7213be9..ec92a8e7af 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -1208,8 +1208,6 @@ static inline PowerPCCPU *ppc_env_get_cpu(CPUPPCState *env) return container_of(env, PowerPCCPU, env); } -#define ENV_GET_CPU(e) CPU(ppc_env_get_cpu(e)) - #define ENV_OFFSET offsetof(PowerPCCPU, env) PowerPCCPUClass *ppc_cpu_class_by_pvr(uint32_t pvr); diff --git a/target/ppc/mmu_helper.c b/target/ppc/mmu_helper.c index e605efa883..e3149e4d3f 100644 --- a/target/ppc/mmu_helper.c +++ b/target/ppc/mmu_helper.c @@ -522,7 +522,7 @@ static inline int get_segment_6xx_tlb(CPUPPCState *env, mmu_ctx_t *ctx, ret = ppc6xx_tlb_check(env, ctx, eaddr, rw, type); #if defined(DUMP_PAGE_TABLES) if (qemu_loglevel_mask(CPU_LOG_MMU)) { - CPUState *cs = ENV_GET_CPU(env); + CPUState *cs = env_cpu(env); hwaddr curaddr; uint32_t a0, a1, a2, a3; diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 8ee5051119..9ab038bac3 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -244,7 +244,6 @@ extern const char * const riscv_fpr_regnames[]; extern const char * const riscv_excp_names[]; extern const char * const riscv_intr_names[]; -#define ENV_GET_CPU(e) CPU(riscv_env_get_cpu(e)) #define ENV_OFFSET offsetof(RISCVCPU, env) void riscv_cpu_do_interrupt(CPUState *cpu); diff --git a/target/s390x/cpu.h b/target/s390x/cpu.h index a8c3d702d3..56767f289d 100644 --- a/target/s390x/cpu.h +++ b/target/s390x/cpu.h @@ -168,8 +168,6 @@ static inline S390CPU *s390_env_get_cpu(CPUS390XState *env) return container_of(env, S390CPU, env); } -#define ENV_GET_CPU(e) CPU(s390_env_get_cpu(e)) - #define ENV_OFFSET offsetof(S390CPU, env) #ifndef CONFIG_USER_ONLY diff --git a/target/s390x/gdbstub.c b/target/s390x/gdbstub.c index 9cfd8fe3e0..a45d805a21 100644 --- a/target/s390x/gdbstub.c +++ b/target/s390x/gdbstub.c @@ -96,7 +96,7 @@ static int cpu_write_ac_reg(CPUS390XState *env, uint8_t *mem_buf, int n) switch (n) { case S390_A0_REGNUM ... S390_A15_REGNUM: env->aregs[n] = ldl_p(mem_buf); - cpu_synchronize_post_init(ENV_GET_CPU(env)); + cpu_synchronize_post_init(env_cpu(env)); return 4; default: return 0; @@ -201,9 +201,9 @@ static int cpu_write_c_reg(CPUS390XState *env, uint8_t *mem_buf, int n) case S390_C0_REGNUM ... S390_C15_REGNUM: env->cregs[n] = ldtul_p(mem_buf); if (tcg_enabled()) { - tlb_flush(ENV_GET_CPU(env)); + tlb_flush(env_cpu(env)); } - cpu_synchronize_post_init(ENV_GET_CPU(env)); + cpu_synchronize_post_init(env_cpu(env)); return 8; default: return 0; @@ -251,35 +251,35 @@ static int cpu_write_virt_reg(CPUS390XState *env, uint8_t *mem_buf, int n) switch (n) { case S390_VIRT_CKC_REGNUM: env->ckc = ldtul_p(mem_buf); - cpu_synchronize_post_init(ENV_GET_CPU(env)); + cpu_synchronize_post_init(env_cpu(env)); return 8; case S390_VIRT_CPUTM_REGNUM: env->cputm = ldtul_p(mem_buf); - cpu_synchronize_post_init(ENV_GET_CPU(env)); + cpu_synchronize_post_init(env_cpu(env)); return 8; case S390_VIRT_BEA_REGNUM: env->gbea = ldtul_p(mem_buf); - cpu_synchronize_post_init(ENV_GET_CPU(env)); + cpu_synchronize_post_init(env_cpu(env)); return 8; case S390_VIRT_PREFIX_REGNUM: env->psa = ldtul_p(mem_buf); - cpu_synchronize_post_init(ENV_GET_CPU(env)); + cpu_synchronize_post_init(env_cpu(env)); return 8; case S390_VIRT_PP_REGNUM: env->pp = ldtul_p(mem_buf); - cpu_synchronize_post_init(ENV_GET_CPU(env)); + cpu_synchronize_post_init(env_cpu(env)); return 8; case S390_VIRT_PFT_REGNUM: env->pfault_token = ldtul_p(mem_buf); - cpu_synchronize_post_init(ENV_GET_CPU(env)); + cpu_synchronize_post_init(env_cpu(env)); return 8; case S390_VIRT_PFS_REGNUM: env->pfault_select = ldtul_p(mem_buf); - cpu_synchronize_post_init(ENV_GET_CPU(env)); + cpu_synchronize_post_init(env_cpu(env)); return 8; case S390_VIRT_PFC_REGNUM: env->pfault_compare = ldtul_p(mem_buf); - cpu_synchronize_post_init(ENV_GET_CPU(env)); + cpu_synchronize_post_init(env_cpu(env)); return 8; default: return 0; @@ -303,7 +303,7 @@ static int cpu_read_gs_reg(CPUS390XState *env, uint8_t *mem_buf, int n) static int cpu_write_gs_reg(CPUS390XState *env, uint8_t *mem_buf, int n) { env->gscb[n] = ldtul_p(mem_buf); - cpu_synchronize_post_init(ENV_GET_CPU(env)); + cpu_synchronize_post_init(env_cpu(env)); return 8; } diff --git a/target/s390x/mem_helper.c b/target/s390x/mem_helper.c index ffd5f02fbe..4a0161602f 100644 --- a/target/s390x/mem_helper.c +++ b/target/s390x/mem_helper.c @@ -1461,7 +1461,7 @@ static uint32_t do_csst(CPUS390XState *env, uint32_t r3, uint64_t a1, #endif if ((HAVE_CMPXCHG128 ? 0 : fc + 2 > max) || (HAVE_ATOMIC128 ? 0 : sc > max)) { - cpu_loop_exit_atomic(ENV_GET_CPU(env), ra); + cpu_loop_exit_atomic(env_cpu(env), ra); } } diff --git a/target/sh4/cpu.h b/target/sh4/cpu.h index 1bdc997290..8b17e6d63e 100644 --- a/target/sh4/cpu.h +++ b/target/sh4/cpu.h @@ -212,8 +212,6 @@ static inline SuperHCPU *sh_env_get_cpu(CPUSH4State *env) return container_of(env, SuperHCPU, env); } -#define ENV_GET_CPU(e) CPU(sh_env_get_cpu(e)) - #define ENV_OFFSET offsetof(SuperHCPU, env) void superh_cpu_do_interrupt(CPUState *cpu); diff --git a/target/sh4/op_helper.c b/target/sh4/op_helper.c index bd5d782b50..932aa7a7c7 100644 --- a/target/sh4/op_helper.c +++ b/target/sh4/op_helper.c @@ -107,7 +107,7 @@ void helper_trapa(CPUSH4State *env, uint32_t tra) void helper_exclusive(CPUSH4State *env) { /* We do not want cpu_restore_state to run. */ - cpu_loop_exit_atomic(ENV_GET_CPU(env), 0); + cpu_loop_exit_atomic(env_cpu(env), 0); } void helper_movcal(CPUSH4State *env, uint32_t address, uint32_t value) diff --git a/target/sparc/cpu.h b/target/sparc/cpu.h index ba5904e05a..e29421349b 100644 --- a/target/sparc/cpu.h +++ b/target/sparc/cpu.h @@ -537,8 +537,6 @@ static inline SPARCCPU *sparc_env_get_cpu(CPUSPARCState *env) return container_of(env, SPARCCPU, env); } -#define ENV_GET_CPU(e) CPU(sparc_env_get_cpu(e)) - #define ENV_OFFSET offsetof(SPARCCPU, env) #ifndef CONFIG_USER_ONLY diff --git a/target/tilegx/cpu.h b/target/tilegx/cpu.h index 042a7a0c71..135df63523 100644 --- a/target/tilegx/cpu.h +++ b/target/tilegx/cpu.h @@ -143,8 +143,6 @@ static inline TileGXCPU *tilegx_env_get_cpu(CPUTLGState *env) return container_of(env, TileGXCPU, env); } -#define ENV_GET_CPU(e) CPU(tilegx_env_get_cpu(e)) - #define ENV_OFFSET offsetof(TileGXCPU, env) /* TILE-Gx memory attributes */ diff --git a/target/tricore/cpu.h b/target/tricore/cpu.h index 8d660df34a..4a2a955cc5 100644 --- a/target/tricore/cpu.h +++ b/target/tricore/cpu.h @@ -213,8 +213,6 @@ static inline TriCoreCPU *tricore_env_get_cpu(CPUTriCoreState *env) return TRICORE_CPU(container_of(env, TriCoreCPU, env)); } -#define ENV_GET_CPU(e) CPU(tricore_env_get_cpu(e)) - #define ENV_OFFSET offsetof(TriCoreCPU, env) hwaddr tricore_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); diff --git a/target/unicore32/cpu.h b/target/unicore32/cpu.h index 5c9c4d98c0..e91cec4d2e 100644 --- a/target/unicore32/cpu.h +++ b/target/unicore32/cpu.h @@ -81,8 +81,6 @@ static inline UniCore32CPU *uc32_env_get_cpu(CPUUniCore32State *env) return container_of(env, UniCore32CPU, env); } -#define ENV_GET_CPU(e) CPU(uc32_env_get_cpu(e)) - #define ENV_OFFSET offsetof(UniCore32CPU, env) void uc32_cpu_do_interrupt(CPUState *cpu); diff --git a/target/xtensa/cpu.h b/target/xtensa/cpu.h index 6e6fb1d893..3de53cb5d0 100644 --- a/target/xtensa/cpu.h +++ b/target/xtensa/cpu.h @@ -564,8 +564,6 @@ static inline XtensaCPU *xtensa_env_get_cpu(const CPUXtensaState *env) return container_of(env, XtensaCPU, env); } -#define ENV_GET_CPU(e) CPU(xtensa_env_get_cpu(e)) - #define ENV_OFFSET offsetof(XtensaCPU, env) -- cgit 1.4.1 From 083dc73d7a3cf2a75b5625fd8f0669b57a855d16 Mon Sep 17 00:00:00 2001 From: Richard Henderson Date: Fri, 22 Mar 2019 17:22:52 -0700 Subject: cpu: Introduce env_archcpu This will replace foo_env_get_cpu with a generic definition. No changes to the target specific code so far. Reviewed-by: Alistair Francis Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- include/exec/cpu-all.h | 14 ++++++++++++-- 1 file changed, 12 insertions(+), 2 deletions(-) (limited to 'include/exec') diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h index 454f6d663f..c62f07b354 100644 --- a/include/exec/cpu-all.h +++ b/include/exec/cpu-all.h @@ -371,6 +371,17 @@ int cpu_memory_rw_debug(CPUState *cpu, target_ulong addr, int cpu_exec(CPUState *cpu); +/** + * env_archcpu(env) + * @env: The architecture environment + * + * Return the ArchCPU associated with the environment. + */ +static inline ArchCPU *env_archcpu(CPUArchState *env) +{ + return container_of(env, ArchCPU, env); +} + /** * env_cpu(env) * @env: The architecture environment @@ -379,8 +390,7 @@ int cpu_exec(CPUState *cpu); */ static inline CPUState *env_cpu(CPUArchState *env) { - ArchCPU *arch_cpu = container_of(env, ArchCPU, env); - return &arch_cpu->parent_obj; + return &env_archcpu(env)->parent_obj; } #endif /* CPU_ALL_H */ -- cgit 1.4.1 From 677c4d69ac21961e76a386f9bfc892a44923acc0 Mon Sep 17 00:00:00 2001 From: Richard Henderson Date: Fri, 22 Mar 2019 17:00:56 -0700 Subject: cpu: Move ENV_OFFSET to exec/gen-icount.h Now that we have ArchCPU, we can define this generically, in the one place that needs it. Reviewed-by: Alistair Francis Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- include/exec/gen-icount.h | 2 ++ target/alpha/cpu.h | 1 - target/arm/cpu.h | 2 -- target/cris/cpu.h | 1 - target/hppa/cpu.h | 1 - target/i386/cpu.h | 1 - target/lm32/cpu.h | 1 - target/m68k/cpu.h | 1 - target/microblaze/cpu.h | 1 - target/mips/cpu.h | 1 - target/moxie/cpu.h | 1 - target/nios2/cpu.h | 1 - target/openrisc/cpu.h | 1 - target/ppc/cpu.h | 1 - target/riscv/cpu.h | 2 -- target/s390x/cpu.h | 1 - target/sh4/cpu.h | 1 - target/sparc/cpu.h | 1 - target/tilegx/cpu.h | 1 - target/tricore/cpu.h | 1 - target/unicore32/cpu.h | 1 - target/xtensa/cpu.h | 2 -- 22 files changed, 2 insertions(+), 24 deletions(-) (limited to 'include/exec') diff --git a/include/exec/gen-icount.h b/include/exec/gen-icount.h index 24f7991781..9cfa6ccce5 100644 --- a/include/exec/gen-icount.h +++ b/include/exec/gen-icount.h @@ -5,6 +5,8 @@ /* Helpers for instruction counting code generation. */ +#define ENV_OFFSET offsetof(ArchCPU, env) + static TCGOp *icount_start_insn; static inline void gen_tb_start(TranslationBlock *tb) diff --git a/target/alpha/cpu.h b/target/alpha/cpu.h index 86d3e953b9..361f85c976 100644 --- a/target/alpha/cpu.h +++ b/target/alpha/cpu.h @@ -278,7 +278,6 @@ struct AlphaCPU { QEMUTimer *alarm_timer; }; -#define ENV_OFFSET offsetof(AlphaCPU, env) #ifndef CONFIG_USER_ONLY extern const struct VMStateDescription vmstate_alpha_cpu; diff --git a/target/arm/cpu.h b/target/arm/cpu.h index c7df3816b5..abe6fce7ab 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -917,8 +917,6 @@ void arm_cpu_post_init(Object *obj); uint64_t arm_cpu_mp_affinity(int idx, uint8_t clustersz); -#define ENV_OFFSET offsetof(ARMCPU, env) - #ifndef CONFIG_USER_ONLY extern const struct VMStateDescription vmstate_arm_cpu; #endif diff --git a/target/cris/cpu.h b/target/cris/cpu.h index e9e4e39a40..83c350377a 100644 --- a/target/cris/cpu.h +++ b/target/cris/cpu.h @@ -183,7 +183,6 @@ struct CRISCPU { CPUCRISState env; }; -#define ENV_OFFSET offsetof(CRISCPU, env) #ifndef CONFIG_USER_ONLY extern const struct VMStateDescription vmstate_cris_cpu; diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h index 75e6a91a5e..7f9f54731b 100644 --- a/target/hppa/cpu.h +++ b/target/hppa/cpu.h @@ -222,7 +222,6 @@ struct HPPACPU { QEMUTimer *alarm_timer; }; -#define ENV_OFFSET offsetof(HPPACPU, env) typedef CPUHPPAState CPUArchState; typedef HPPACPU ArchCPU; diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 709d88cfcf..3a155c12d3 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -1480,7 +1480,6 @@ struct X86CPU { int32_t hv_max_vps; }; -#define ENV_OFFSET offsetof(X86CPU, env) #ifndef CONFIG_USER_ONLY extern struct VMStateDescription vmstate_x86_cpu; diff --git a/target/lm32/cpu.h b/target/lm32/cpu.h index 7fb65fb4b6..2c934472d6 100644 --- a/target/lm32/cpu.h +++ b/target/lm32/cpu.h @@ -195,7 +195,6 @@ struct LM32CPU { uint32_t features; }; -#define ENV_OFFSET offsetof(LM32CPU, env) #ifndef CONFIG_USER_ONLY extern const struct VMStateDescription vmstate_lm32_cpu; diff --git a/target/m68k/cpu.h b/target/m68k/cpu.h index 7f3fa8d141..4006663494 100644 --- a/target/m68k/cpu.h +++ b/target/m68k/cpu.h @@ -163,7 +163,6 @@ struct M68kCPU { CPUM68KState env; }; -#define ENV_OFFSET offsetof(M68kCPU, env) void m68k_cpu_do_interrupt(CPUState *cpu); bool m68k_cpu_exec_interrupt(CPUState *cpu, int int_req); diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h index 8402cc81f6..a17c12ca2f 100644 --- a/target/microblaze/cpu.h +++ b/target/microblaze/cpu.h @@ -310,7 +310,6 @@ struct MicroBlazeCPU { CPUMBState env; }; -#define ENV_OFFSET offsetof(MicroBlazeCPU, env) void mb_cpu_do_interrupt(CPUState *cs); bool mb_cpu_exec_interrupt(CPUState *cs, int int_req); diff --git a/target/mips/cpu.h b/target/mips/cpu.h index cb09425476..24fe25f61c 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -1071,7 +1071,6 @@ struct MIPSCPU { CPUMIPSState env; }; -#define ENV_OFFSET offsetof(MIPSCPU, env) void mips_cpu_list(void); diff --git a/target/moxie/cpu.h b/target/moxie/cpu.h index b9f5635e50..3d418c8f1d 100644 --- a/target/moxie/cpu.h +++ b/target/moxie/cpu.h @@ -90,7 +90,6 @@ typedef struct MoxieCPU { CPUMoxieState env; } MoxieCPU; -#define ENV_OFFSET offsetof(MoxieCPU, env) void moxie_cpu_do_interrupt(CPUState *cs); void moxie_cpu_dump_state(CPUState *cpu, FILE *f, int flags); diff --git a/target/nios2/cpu.h b/target/nios2/cpu.h index 9490ba83e4..c96d797dda 100644 --- a/target/nios2/cpu.h +++ b/target/nios2/cpu.h @@ -194,7 +194,6 @@ typedef struct Nios2CPU { uint32_t fast_tlb_miss_addr; } Nios2CPU; -#define ENV_OFFSET offsetof(Nios2CPU, env) void nios2_tcg_init(void); void nios2_cpu_do_interrupt(CPUState *cs); diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h index 9e46ac5266..39e2765aa2 100644 --- a/target/openrisc/cpu.h +++ b/target/openrisc/cpu.h @@ -317,7 +317,6 @@ typedef struct OpenRISCCPU { } OpenRISCCPU; -#define ENV_OFFSET offsetof(OpenRISCCPU, env) void cpu_openrisc_list(void); void openrisc_cpu_do_interrupt(CPUState *cpu); diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index 73ef868a7b..73b92c189c 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -1203,7 +1203,6 @@ struct PowerPCCPU { int32_t mig_slb_nr; }; -#define ENV_OFFSET offsetof(PowerPCCPU, env) PowerPCCPUClass *ppc_cpu_class_by_pvr(uint32_t pvr); PowerPCCPUClass *ppc_cpu_class_by_pvr_mask(uint32_t pvr); diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 29a1e08f03..d9611eaced 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -239,8 +239,6 @@ extern const char * const riscv_fpr_regnames[]; extern const char * const riscv_excp_names[]; extern const char * const riscv_intr_names[]; -#define ENV_OFFSET offsetof(RISCVCPU, env) - void riscv_cpu_do_interrupt(CPUState *cpu); int riscv_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg); int riscv_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); diff --git a/target/s390x/cpu.h b/target/s390x/cpu.h index d18b279d87..dbf13c9221 100644 --- a/target/s390x/cpu.h +++ b/target/s390x/cpu.h @@ -163,7 +163,6 @@ struct S390CPU { uint32_t irqstate_saved_size; }; -#define ENV_OFFSET offsetof(S390CPU, env) #ifndef CONFIG_USER_ONLY extern const struct VMStateDescription vmstate_s390_cpu; diff --git a/target/sh4/cpu.h b/target/sh4/cpu.h index 089eea261c..610a8db6de 100644 --- a/target/sh4/cpu.h +++ b/target/sh4/cpu.h @@ -207,7 +207,6 @@ struct SuperHCPU { CPUSH4State env; }; -#define ENV_OFFSET offsetof(SuperHCPU, env) void superh_cpu_do_interrupt(CPUState *cpu); bool superh_cpu_exec_interrupt(CPUState *cpu, int int_req); diff --git a/target/sparc/cpu.h b/target/sparc/cpu.h index adcd9e3000..0cc36873ce 100644 --- a/target/sparc/cpu.h +++ b/target/sparc/cpu.h @@ -532,7 +532,6 @@ struct SPARCCPU { CPUSPARCState env; }; -#define ENV_OFFSET offsetof(SPARCCPU, env) #ifndef CONFIG_USER_ONLY extern const struct VMStateDescription vmstate_sparc_cpu; diff --git a/target/tilegx/cpu.h b/target/tilegx/cpu.h index 7f8fe7c513..643b7dbd17 100644 --- a/target/tilegx/cpu.h +++ b/target/tilegx/cpu.h @@ -138,7 +138,6 @@ typedef struct TileGXCPU { CPUTLGState env; } TileGXCPU; -#define ENV_OFFSET offsetof(TileGXCPU, env) /* TILE-Gx memory attributes */ #define MMU_USER_IDX 0 /* Current memory operation is in user mode */ diff --git a/target/tricore/cpu.h b/target/tricore/cpu.h index 6a40d37362..9f45bb5c24 100644 --- a/target/tricore/cpu.h +++ b/target/tricore/cpu.h @@ -208,7 +208,6 @@ struct TriCoreCPU { CPUTriCoreState env; }; -#define ENV_OFFSET offsetof(TriCoreCPU, env) hwaddr tricore_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); void tricore_cpu_dump_state(CPUState *cpu, FILE *f, int flags); diff --git a/target/unicore32/cpu.h b/target/unicore32/cpu.h index 595dc43c99..c1130e9548 100644 --- a/target/unicore32/cpu.h +++ b/target/unicore32/cpu.h @@ -76,7 +76,6 @@ struct UniCore32CPU { CPUUniCore32State env; }; -#define ENV_OFFSET offsetof(UniCore32CPU, env) void uc32_cpu_do_interrupt(CPUState *cpu); bool uc32_cpu_exec_interrupt(CPUState *cpu, int int_req); diff --git a/target/xtensa/cpu.h b/target/xtensa/cpu.h index 97b7bae0fe..e89605747a 100644 --- a/target/xtensa/cpu.h +++ b/target/xtensa/cpu.h @@ -559,8 +559,6 @@ struct XtensaCPU { CPUXtensaState env; }; -#define ENV_OFFSET offsetof(XtensaCPU, env) - bool xtensa_cpu_tlb_fill(CPUState *cs, vaddr address, int size, MMUAccessType access_type, int mmu_idx, -- cgit 1.4.1 From 7506ed902eb97fe4e2a1dd16766c621d32ecc40d Mon Sep 17 00:00:00 2001 From: Richard Henderson Date: Thu, 28 Mar 2019 11:26:22 -1000 Subject: cpu: Introduce cpu_set_cpustate_pointers Consolidate some boilerplate from foo_cpu_initfn. Reviewed-by: Alistair Francis Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- include/exec/cpu-all.h | 11 +++++++++++ target/alpha/cpu.c | 3 +-- target/arm/cpu.c | 3 +-- target/cris/cpu.c | 3 +-- target/hppa/cpu.c | 2 +- target/i386/cpu.c | 3 +-- target/lm32/cpu.c | 3 +-- target/m68k/cpu.c | 4 +--- target/microblaze/cpu.c | 3 +-- target/mips/cpu.c | 3 +-- target/moxie/cpu.c | 3 +-- target/nios2/cpu.c | 6 ++---- target/openrisc/cpu.c | 3 +-- target/ppc/translate_init.inc.c | 3 +-- target/riscv/cpu.c | 3 +-- target/s390x/cpu.c | 9 +++++---- target/sh4/cpu.c | 3 +-- target/sparc/cpu.c | 3 +-- target/tilegx/cpu.c | 4 +--- target/tricore/cpu.c | 4 +--- target/unicore32/cpu.c | 3 +-- target/xtensa/cpu.c | 3 +-- 22 files changed, 37 insertions(+), 48 deletions(-) (limited to 'include/exec') diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h index c62f07b354..71154070a7 100644 --- a/include/exec/cpu-all.h +++ b/include/exec/cpu-all.h @@ -371,6 +371,17 @@ int cpu_memory_rw_debug(CPUState *cpu, target_ulong addr, int cpu_exec(CPUState *cpu); +/** + * cpu_set_cpustate_pointers(cpu) + * @cpu: The cpu object + * + * Set the generic pointers in CPUState into the outer object. + */ +static inline void cpu_set_cpustate_pointers(ArchCPU *cpu) +{ + cpu->parent_obj.env_ptr = &cpu->env; +} + /** * env_archcpu(env) * @env: The architecture environment diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c index 7c81be4111..952582567f 100644 --- a/target/alpha/cpu.c +++ b/target/alpha/cpu.c @@ -191,11 +191,10 @@ static void ev67_cpu_initfn(Object *obj) static void alpha_cpu_initfn(Object *obj) { - CPUState *cs = CPU(obj); AlphaCPU *cpu = ALPHA_CPU(obj); CPUAlphaState *env = &cpu->env; - cs->env_ptr = env; + cpu_set_cpustate_pointers(cpu); env->lock_addr = -1; #if defined(CONFIG_USER_ONLY) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 9b23ac2c93..f70e07fd11 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -697,10 +697,9 @@ static void cpreg_hashtable_data_destroy(gpointer data) static void arm_cpu_initfn(Object *obj) { - CPUState *cs = CPU(obj); ARMCPU *cpu = ARM_CPU(obj); - cs->env_ptr = &cpu->env; + cpu_set_cpustate_pointers(cpu); cpu->cp_regs = g_hash_table_new_full(g_int_hash, g_int_equal, g_free, cpreg_hashtable_data_destroy); diff --git a/target/cris/cpu.c b/target/cris/cpu.c index 4e5288ae80..1dce6d10c3 100644 --- a/target/cris/cpu.c +++ b/target/cris/cpu.c @@ -172,12 +172,11 @@ static void cris_disas_set_info(CPUState *cpu, disassemble_info *info) static void cris_cpu_initfn(Object *obj) { - CPUState *cs = CPU(obj); CRISCPU *cpu = CRIS_CPU(obj); CRISCPUClass *ccc = CRIS_CPU_GET_CLASS(obj); CPUCRISState *env = &cpu->env; - cs->env_ptr = env; + cpu_set_cpustate_pointers(cpu); env->pregs[PR_VR] = ccc->vr; diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c index 9717ea1798..ae494abad1 100644 --- a/target/hppa/cpu.c +++ b/target/hppa/cpu.c @@ -134,7 +134,7 @@ static void hppa_cpu_initfn(Object *obj) HPPACPU *cpu = HPPA_CPU(obj); CPUHPPAState *env = &cpu->env; - cs->env_ptr = env; + cpu_set_cpustate_pointers(cpu); cs->exception_index = -1; cpu_hppa_loaded_fr0(env); cpu_hppa_put_psw(env, PSW_W); diff --git a/target/i386/cpu.c b/target/i386/cpu.c index a461d8d92c..b21ecaac17 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -5592,13 +5592,12 @@ static void x86_cpu_get_crash_info_qom(Object *obj, Visitor *v, static void x86_cpu_initfn(Object *obj) { - CPUState *cs = CPU(obj); X86CPU *cpu = X86_CPU(obj); X86CPUClass *xcc = X86_CPU_GET_CLASS(obj); CPUX86State *env = &cpu->env; FeatureWord w; - cs->env_ptr = env; + cpu_set_cpustate_pointers(cpu); object_property_add(obj, "family", "int", x86_cpuid_version_get_family, diff --git a/target/lm32/cpu.c b/target/lm32/cpu.c index 57c50c1578..a14191236f 100644 --- a/target/lm32/cpu.c +++ b/target/lm32/cpu.c @@ -142,11 +142,10 @@ static void lm32_cpu_realizefn(DeviceState *dev, Error **errp) static void lm32_cpu_initfn(Object *obj) { - CPUState *cs = CPU(obj); LM32CPU *cpu = LM32_CPU(obj); CPULM32State *env = &cpu->env; - cs->env_ptr = env; + cpu_set_cpustate_pointers(cpu); env->flags = 0; } diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c index b16957934a..ea38cb46e9 100644 --- a/target/m68k/cpu.c +++ b/target/m68k/cpu.c @@ -238,11 +238,9 @@ static void m68k_cpu_realizefn(DeviceState *dev, Error **errp) static void m68k_cpu_initfn(Object *obj) { - CPUState *cs = CPU(obj); M68kCPU *cpu = M68K_CPU(obj); - CPUM68KState *env = &cpu->env; - cs->env_ptr = env; + cpu_set_cpustate_pointers(cpu); } static const VMStateDescription vmstate_m68k_cpu = { diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c index 0ea549910b..5c537526c0 100644 --- a/target/microblaze/cpu.c +++ b/target/microblaze/cpu.c @@ -221,11 +221,10 @@ static void mb_cpu_realizefn(DeviceState *dev, Error **errp) static void mb_cpu_initfn(Object *obj) { - CPUState *cs = CPU(obj); MicroBlazeCPU *cpu = MICROBLAZE_CPU(obj); CPUMBState *env = &cpu->env; - cs->env_ptr = env; + cpu_set_cpustate_pointers(cpu); set_float_rounding_mode(float_round_nearest_even, &env->fp_status); diff --git a/target/mips/cpu.c b/target/mips/cpu.c index a33058609a..73232b80ad 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -152,12 +152,11 @@ static void mips_cpu_realizefn(DeviceState *dev, Error **errp) static void mips_cpu_initfn(Object *obj) { - CPUState *cs = CPU(obj); MIPSCPU *cpu = MIPS_CPU(obj); CPUMIPSState *env = &cpu->env; MIPSCPUClass *mcc = MIPS_CPU_GET_CLASS(obj); - cs->env_ptr = env; + cpu_set_cpustate_pointers(cpu); env->cpu_model = mcc->cpu_def; } diff --git a/target/moxie/cpu.c b/target/moxie/cpu.c index 02b2b47574..4688cee8c1 100644 --- a/target/moxie/cpu.c +++ b/target/moxie/cpu.c @@ -74,10 +74,9 @@ static void moxie_cpu_realizefn(DeviceState *dev, Error **errp) static void moxie_cpu_initfn(Object *obj) { - CPUState *cs = CPU(obj); MoxieCPU *cpu = MOXIE_CPU(obj); - cs->env_ptr = &cpu->env; + cpu_set_cpustate_pointers(cpu); } static ObjectClass *moxie_cpu_class_by_name(const char *cpu_model) diff --git a/target/nios2/cpu.c b/target/nios2/cpu.c index 186af4913d..b00223e0c7 100644 --- a/target/nios2/cpu.c +++ b/target/nios2/cpu.c @@ -66,14 +66,12 @@ static void nios2_cpu_reset(CPUState *cs) static void nios2_cpu_initfn(Object *obj) { - CPUState *cs = CPU(obj); Nios2CPU *cpu = NIOS2_CPU(obj); - CPUNios2State *env = &cpu->env; - cs->env_ptr = env; + cpu_set_cpustate_pointers(cpu); #if !defined(CONFIG_USER_ONLY) - mmu_init(env); + mmu_init(&cpu->env); #endif } diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c index 3816baee70..d5b0134371 100644 --- a/target/openrisc/cpu.c +++ b/target/openrisc/cpu.c @@ -92,10 +92,9 @@ static void openrisc_cpu_realizefn(DeviceState *dev, Error **errp) static void openrisc_cpu_initfn(Object *obj) { - CPUState *cs = CPU(obj); OpenRISCCPU *cpu = OPENRISC_CPU(obj); - cs->env_ptr = &cpu->env; + cpu_set_cpustate_pointers(cpu); } /* CPU models */ diff --git a/target/ppc/translate_init.inc.c b/target/ppc/translate_init.inc.c index d161e95fb2..b71b7bac20 100644 --- a/target/ppc/translate_init.inc.c +++ b/target/ppc/translate_init.inc.c @@ -10473,12 +10473,11 @@ static bool ppc_cpu_is_big_endian(CPUState *cs) static void ppc_cpu_instance_init(Object *obj) { - CPUState *cs = CPU(obj); PowerPCCPU *cpu = POWERPC_CPU(obj); PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); CPUPPCState *env = &cpu->env; - cs->env_ptr = env; + cpu_set_cpustate_pointers(cpu); cpu->vcpu_id = UNASSIGNED_CPU_INDEX; env->msr_mask = pcc->msr_mask; diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index e29879915f..86fd8693a8 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -367,10 +367,9 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) static void riscv_cpu_init(Object *obj) { - CPUState *cs = CPU(obj); RISCVCPU *cpu = RISCV_CPU(obj); - cs->env_ptr = &cpu->env; + cpu_set_cpustate_pointers(cpu); } static const VMStateDescription vmstate_riscv_cpu = { diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c index 6af1a1530f..4ca66fed1a 100644 --- a/target/s390x/cpu.c +++ b/target/s390x/cpu.c @@ -285,17 +285,18 @@ static void s390_cpu_initfn(Object *obj) { CPUState *cs = CPU(obj); S390CPU *cpu = S390_CPU(obj); - CPUS390XState *env = &cpu->env; - cs->env_ptr = env; + cpu_set_cpustate_pointers(cpu); cs->halted = 1; cs->exception_index = EXCP_HLT; object_property_add(obj, "crash-information", "GuestPanicInformation", s390_cpu_get_crash_info_qom, NULL, NULL, NULL, NULL); s390_cpu_model_register_props(obj); #if !defined(CONFIG_USER_ONLY) - env->tod_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, s390x_tod_timer, cpu); - env->cpu_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, s390x_cpu_timer, cpu); + cpu->env.tod_timer = + timer_new_ns(QEMU_CLOCK_VIRTUAL, s390x_tod_timer, cpu); + cpu->env.cpu_timer = + timer_new_ns(QEMU_CLOCK_VIRTUAL, s390x_cpu_timer, cpu); s390_cpu_set_state(S390_CPU_STATE_STOPPED, cpu); #endif } diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c index c4736a0a73..dfca03f266 100644 --- a/target/sh4/cpu.c +++ b/target/sh4/cpu.c @@ -194,11 +194,10 @@ static void superh_cpu_realizefn(DeviceState *dev, Error **errp) static void superh_cpu_initfn(Object *obj) { - CPUState *cs = CPU(obj); SuperHCPU *cpu = SUPERH_CPU(obj); CPUSH4State *env = &cpu->env; - cs->env_ptr = env; + cpu_set_cpustate_pointers(cpu); env->movcal_backup_tail = &(env->movcal_backup); } diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c index f93ce72eb9..ad2c362c6a 100644 --- a/target/sparc/cpu.c +++ b/target/sparc/cpu.c @@ -774,12 +774,11 @@ static void sparc_cpu_realizefn(DeviceState *dev, Error **errp) static void sparc_cpu_initfn(Object *obj) { - CPUState *cs = CPU(obj); SPARCCPU *cpu = SPARC_CPU(obj); SPARCCPUClass *scc = SPARC_CPU_GET_CLASS(obj); CPUSPARCState *env = &cpu->env; - cs->env_ptr = env; + cpu_set_cpustate_pointers(cpu); if (scc->cpu_def) { env->def = *scc->cpu_def; diff --git a/target/tilegx/cpu.c b/target/tilegx/cpu.c index b209c55387..3567a2b664 100644 --- a/target/tilegx/cpu.c +++ b/target/tilegx/cpu.c @@ -100,11 +100,9 @@ static void tilegx_cpu_realizefn(DeviceState *dev, Error **errp) static void tilegx_cpu_initfn(Object *obj) { - CPUState *cs = CPU(obj); TileGXCPU *cpu = TILEGX_CPU(obj); - CPUTLGState *env = &cpu->env; - cs->env_ptr = env; + cpu_set_cpustate_pointers(cpu); } static void tilegx_cpu_do_interrupt(CPUState *cs) diff --git a/target/tricore/cpu.c b/target/tricore/cpu.c index ea1199d27e..8624103674 100644 --- a/target/tricore/cpu.c +++ b/target/tricore/cpu.c @@ -104,11 +104,9 @@ static void tricore_cpu_realizefn(DeviceState *dev, Error **errp) static void tricore_cpu_initfn(Object *obj) { - CPUState *cs = CPU(obj); TriCoreCPU *cpu = TRICORE_CPU(obj); - CPUTriCoreState *env = &cpu->env; - cs->env_ptr = env; + cpu_set_cpustate_pointers(cpu); } static ObjectClass *tricore_cpu_class_by_name(const char *cpu_model) diff --git a/target/unicore32/cpu.c b/target/unicore32/cpu.c index 3f57c508a0..451082bbe6 100644 --- a/target/unicore32/cpu.c +++ b/target/unicore32/cpu.c @@ -103,11 +103,10 @@ static void uc32_cpu_realizefn(DeviceState *dev, Error **errp) static void uc32_cpu_initfn(Object *obj) { - CPUState *cs = CPU(obj); UniCore32CPU *cpu = UNICORE32_CPU(obj); CPUUniCore32State *env = &cpu->env; - cs->env_ptr = env; + cpu_set_cpustate_pointers(cpu); #ifdef CONFIG_USER_ONLY env->uncached_asr = ASR_MODE_USER; diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c index c79dc75bfe..f3ec66e242 100644 --- a/target/xtensa/cpu.c +++ b/target/xtensa/cpu.c @@ -138,12 +138,11 @@ static void xtensa_cpu_realizefn(DeviceState *dev, Error **errp) static void xtensa_cpu_initfn(Object *obj) { - CPUState *cs = CPU(obj); XtensaCPU *cpu = XTENSA_CPU(obj); XtensaCPUClass *xcc = XTENSA_CPU_GET_CLASS(obj); CPUXtensaState *env = &cpu->env; - cs->env_ptr = env; + cpu_set_cpustate_pointers(cpu); env->config = xcc->config; #ifndef CONFIG_USER_ONLY -- cgit 1.4.1 From 5b146dc716cfd247f99556c04e6e46fbd67565a0 Mon Sep 17 00:00:00 2001 From: Richard Henderson Date: Fri, 22 Mar 2019 17:16:06 -0700 Subject: cpu: Introduce CPUNegativeOffsetState Nothing in there so far, but all of the plumbing done within the target ArchCPU state. Reviewed-by: Alistair Francis Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- include/exec/cpu-all.h | 24 ++++++++++++++++++++++++ include/exec/cpu-defs.h | 8 ++++++++ target/alpha/cpu.h | 1 + target/arm/cpu.h | 1 + target/cris/cpu.h | 1 + target/hppa/cpu.h | 1 + target/i386/cpu.h | 1 + target/lm32/cpu.h | 1 + target/m68k/cpu.h | 1 + target/microblaze/cpu.h | 5 +++-- target/mips/cpu.h | 1 + target/moxie/cpu.h | 1 + target/nios2/cpu.h | 2 ++ target/openrisc/cpu.h | 2 +- target/ppc/cpu.h | 2 ++ target/riscv/cpu.h | 1 + target/s390x/cpu.h | 1 + target/sh4/cpu.h | 1 + target/sparc/cpu.h | 1 + target/tilegx/cpu.h | 1 + target/tricore/cpu.h | 1 + target/unicore32/cpu.h | 1 + target/xtensa/cpu.h | 1 + 23 files changed, 57 insertions(+), 3 deletions(-) (limited to 'include/exec') diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h index 71154070a7..5ae83405c8 100644 --- a/include/exec/cpu-all.h +++ b/include/exec/cpu-all.h @@ -404,4 +404,28 @@ static inline CPUState *env_cpu(CPUArchState *env) return &env_archcpu(env)->parent_obj; } +/** + * env_neg(env) + * @env: The architecture environment + * + * Return the CPUNegativeOffsetState associated with the environment. + */ +static inline CPUNegativeOffsetState *env_neg(CPUArchState *env) +{ + ArchCPU *arch_cpu = container_of(env, ArchCPU, env); + return &arch_cpu->neg; +} + +/** + * cpu_neg(cpu) + * @cpu: The generic CPUState + * + * Return the CPUNegativeOffsetState associated with the cpu. + */ +static inline CPUNegativeOffsetState *cpu_neg(CPUState *cpu) +{ + ArchCPU *arch_cpu = container_of(cpu, ArchCPU, parent_obj); + return &arch_cpu->neg; +} + #endif /* CPU_ALL_H */ diff --git a/include/exec/cpu-defs.h b/include/exec/cpu-defs.h index b9ec261b01..921fbb4c36 100644 --- a/include/exec/cpu-defs.h +++ b/include/exec/cpu-defs.h @@ -227,4 +227,12 @@ typedef struct CPUTLB { #endif /* !CONFIG_USER_ONLY && CONFIG_TCG */ +/* + * This structure must be placed in ArchCPU immedately + * before CPUArchState, as a field named "neg". + */ +typedef struct CPUNegativeOffsetState { + /* Empty */ +} CPUNegativeOffsetState; + #endif diff --git a/target/alpha/cpu.h b/target/alpha/cpu.h index 361f85c976..94fbc00a3b 100644 --- a/target/alpha/cpu.h +++ b/target/alpha/cpu.h @@ -272,6 +272,7 @@ struct AlphaCPU { CPUState parent_obj; /*< public >*/ + CPUNegativeOffsetState neg; CPUAlphaState env; /* This alarm doesn't exist in real hardware; we wish it did. */ diff --git a/target/arm/cpu.h b/target/arm/cpu.h index abe6fce7ab..5965c52f0c 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -721,6 +721,7 @@ struct ARMCPU { CPUState parent_obj; /*< public >*/ + CPUNegativeOffsetState neg; CPUARMState env; /* Coprocessor information */ diff --git a/target/cris/cpu.h b/target/cris/cpu.h index 83c350377a..ad93d1a9ee 100644 --- a/target/cris/cpu.h +++ b/target/cris/cpu.h @@ -180,6 +180,7 @@ struct CRISCPU { CPUState parent_obj; /*< public >*/ + CPUNegativeOffsetState neg; CPUCRISState env; }; diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h index 7f9f54731b..f7c6205218 100644 --- a/target/hppa/cpu.h +++ b/target/hppa/cpu.h @@ -218,6 +218,7 @@ struct HPPACPU { CPUState parent_obj; /*< public >*/ + CPUNegativeOffsetState neg; CPUHPPAState env; QEMUTimer *alarm_timer; }; diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 3a155c12d3..e7580a86e5 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -1369,6 +1369,7 @@ struct X86CPU { CPUState parent_obj; /*< public >*/ + CPUNegativeOffsetState neg; CPUX86State env; bool hyperv_vapic; diff --git a/target/lm32/cpu.h b/target/lm32/cpu.h index 2c934472d6..324bc90f81 100644 --- a/target/lm32/cpu.h +++ b/target/lm32/cpu.h @@ -186,6 +186,7 @@ struct LM32CPU { CPUState parent_obj; /*< public >*/ + CPUNegativeOffsetState neg; CPULM32State env; uint32_t revision; diff --git a/target/m68k/cpu.h b/target/m68k/cpu.h index 4006663494..d92263b750 100644 --- a/target/m68k/cpu.h +++ b/target/m68k/cpu.h @@ -160,6 +160,7 @@ struct M68kCPU { CPUState parent_obj; /*< public >*/ + CPUNegativeOffsetState neg; CPUM68KState env; }; diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h index a17c12ca2f..d90c4fbcb5 100644 --- a/target/microblaze/cpu.h +++ b/target/microblaze/cpu.h @@ -287,6 +287,9 @@ struct MicroBlazeCPU { /*< public >*/ + CPUNegativeOffsetState neg; + CPUMBState env; + /* Microblaze Configuration Settings */ struct { bool stackprot; @@ -306,8 +309,6 @@ struct MicroBlazeCPU { char *version; uint8_t pvr; } cfg; - - CPUMBState env; }; diff --git a/target/mips/cpu.h b/target/mips/cpu.h index 24fe25f61c..62af24937d 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -1068,6 +1068,7 @@ struct MIPSCPU { CPUState parent_obj; /*< public >*/ + CPUNegativeOffsetState neg; CPUMIPSState env; }; diff --git a/target/moxie/cpu.h b/target/moxie/cpu.h index 3d418c8f1d..c6b681531d 100644 --- a/target/moxie/cpu.h +++ b/target/moxie/cpu.h @@ -87,6 +87,7 @@ typedef struct MoxieCPU { CPUState parent_obj; /*< public >*/ + CPUNegativeOffsetState neg; CPUMoxieState env; } MoxieCPU; diff --git a/target/nios2/cpu.h b/target/nios2/cpu.h index c96d797dda..8cc3d4971e 100644 --- a/target/nios2/cpu.h +++ b/target/nios2/cpu.h @@ -182,7 +182,9 @@ typedef struct Nios2CPU { CPUState parent_obj; /*< public >*/ + CPUNegativeOffsetState neg; CPUNios2State env; + bool mmu_present; uint32_t pid_num_bits; uint32_t tlb_num_ways; diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h index 39e2765aa2..51723e9312 100644 --- a/target/openrisc/cpu.h +++ b/target/openrisc/cpu.h @@ -313,8 +313,8 @@ typedef struct OpenRISCCPU { CPUState parent_obj; /*< public >*/ + CPUNegativeOffsetState neg; CPUOpenRISCState env; - } OpenRISCCPU; diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index 73b92c189c..e8962e4655 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -1184,7 +1184,9 @@ struct PowerPCCPU { CPUState parent_obj; /*< public >*/ + CPUNegativeOffsetState neg; CPUPPCState env; + int vcpu_id; uint32_t compat_pvr; PPCVirtualHypervisor *vhyp; diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index d9611eaced..0ed7031915 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -210,6 +210,7 @@ typedef struct RISCVCPU { /*< private >*/ CPUState parent_obj; /*< public >*/ + CPUNegativeOffsetState neg; CPURISCVState env; /* Configuration Settings */ diff --git a/target/s390x/cpu.h b/target/s390x/cpu.h index dbf13c9221..21688b7c8c 100644 --- a/target/s390x/cpu.h +++ b/target/s390x/cpu.h @@ -156,6 +156,7 @@ struct S390CPU { CPUState parent_obj; /*< public >*/ + CPUNegativeOffsetState neg; CPUS390XState env; S390CPUModel *model; /* needed for live migration */ diff --git a/target/sh4/cpu.h b/target/sh4/cpu.h index 610a8db6de..e266db411f 100644 --- a/target/sh4/cpu.h +++ b/target/sh4/cpu.h @@ -204,6 +204,7 @@ struct SuperHCPU { CPUState parent_obj; /*< public >*/ + CPUNegativeOffsetState neg; CPUSH4State env; }; diff --git a/target/sparc/cpu.h b/target/sparc/cpu.h index 0cc36873ce..a3c4f47d40 100644 --- a/target/sparc/cpu.h +++ b/target/sparc/cpu.h @@ -529,6 +529,7 @@ struct SPARCCPU { CPUState parent_obj; /*< public >*/ + CPUNegativeOffsetState neg; CPUSPARCState env; }; diff --git a/target/tilegx/cpu.h b/target/tilegx/cpu.h index 643b7dbd17..deb3e836ea 100644 --- a/target/tilegx/cpu.h +++ b/target/tilegx/cpu.h @@ -135,6 +135,7 @@ typedef struct TileGXCPU { CPUState parent_obj; /*< public >*/ + CPUNegativeOffsetState neg; CPUTLGState env; } TileGXCPU; diff --git a/target/tricore/cpu.h b/target/tricore/cpu.h index 9f45bb5c24..03b293c1f6 100644 --- a/target/tricore/cpu.h +++ b/target/tricore/cpu.h @@ -205,6 +205,7 @@ struct TriCoreCPU { CPUState parent_obj; /*< public >*/ + CPUNegativeOffsetState neg; CPUTriCoreState env; }; diff --git a/target/unicore32/cpu.h b/target/unicore32/cpu.h index c1130e9548..39beb32366 100644 --- a/target/unicore32/cpu.h +++ b/target/unicore32/cpu.h @@ -73,6 +73,7 @@ struct UniCore32CPU { CPUState parent_obj; /*< public >*/ + CPUNegativeOffsetState neg; CPUUniCore32State env; }; diff --git a/target/xtensa/cpu.h b/target/xtensa/cpu.h index e89605747a..e2d7e8371d 100644 --- a/target/xtensa/cpu.h +++ b/target/xtensa/cpu.h @@ -556,6 +556,7 @@ struct XtensaCPU { CPUState parent_obj; /*< public >*/ + CPUNegativeOffsetState neg; CPUXtensaState env; }; -- cgit 1.4.1 From 5e1401969b25f676fee6b1c564441759cf967a43 Mon Sep 17 00:00:00 2001 From: Richard Henderson Date: Thu, 28 Mar 2019 11:54:23 -1000 Subject: cpu: Move icount_decr to CPUNegativeOffsetState Amusingly, we had already ignored the comment to keep this value at the end of CPUState. This restores the minimum negative offset from TCG_AREG0 for code generation. For the couple of uses within qom/cpu.c, without NEED_CPU_H, add a pointer from the CPUState object to the IcountDecr object within CPUNegativeOffsetState. Reviewed-by: Alistair Francis Signed-off-by: Richard Henderson --- accel/tcg/cpu-exec.c | 23 ++++++++++++----------- accel/tcg/tcg-all.c | 6 ++---- accel/tcg/translate-all.c | 8 ++++---- cpus.c | 9 +++++---- include/exec/cpu-all.h | 1 + include/exec/cpu-defs.h | 3 ++- include/exec/gen-icount.h | 16 ++++++++++------ include/qom/cpu.h | 40 ++++++++++++++++++---------------------- qom/cpu.c | 4 ++-- 9 files changed, 56 insertions(+), 54 deletions(-) (limited to 'include/exec') diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index 45ef41ebb2..032a62672e 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -54,7 +54,7 @@ typedef struct SyncClocks { #define MAX_DELAY_PRINT_RATE 2000000000LL #define MAX_NB_PRINTS 100 -static void align_clocks(SyncClocks *sc, const CPUState *cpu) +static void align_clocks(SyncClocks *sc, CPUState *cpu) { int64_t cpu_icount; @@ -62,7 +62,7 @@ static void align_clocks(SyncClocks *sc, const CPUState *cpu) return; } - cpu_icount = cpu->icount_extra + cpu->icount_decr.u16.low; + cpu_icount = cpu->icount_extra + cpu_neg(cpu)->icount_decr.u16.low; sc->diff_clk += cpu_icount_to_ns(sc->last_cpu_icount - cpu_icount); sc->last_cpu_icount = cpu_icount; @@ -105,15 +105,15 @@ static void print_delay(const SyncClocks *sc) } } -static void init_delay_params(SyncClocks *sc, - const CPUState *cpu) +static void init_delay_params(SyncClocks *sc, CPUState *cpu) { if (!icount_align_option) { return; } sc->realtime_clock = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL_RT); sc->diff_clk = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) - sc->realtime_clock; - sc->last_cpu_icount = cpu->icount_extra + cpu->icount_decr.u16.low; + sc->last_cpu_icount + = cpu->icount_extra + cpu_neg(cpu)->icount_decr.u16.low; if (sc->diff_clk < max_delay) { max_delay = sc->diff_clk; } @@ -467,7 +467,7 @@ static inline bool cpu_handle_exception(CPUState *cpu, int *ret) if (cpu->exception_index < 0) { #ifndef CONFIG_USER_ONLY if (replay_has_exception() - && cpu->icount_decr.u16.low + cpu->icount_extra == 0) { + && cpu_neg(cpu)->icount_decr.u16.low + cpu->icount_extra == 0) { /* try to cause an exception pending in the log */ cpu_exec_nocache(cpu, 1, tb_find(cpu, NULL, 0, curr_cflags()), true); } @@ -525,7 +525,7 @@ static inline bool cpu_handle_interrupt(CPUState *cpu, * Ensure zeroing happens before reading cpu->exit_request or * cpu->interrupt_request (see also smp_wmb in cpu_exit()) */ - atomic_mb_set(&cpu->icount_decr.u16.high, 0); + atomic_mb_set(&cpu_neg(cpu)->icount_decr.u16.high, 0); if (unlikely(atomic_read(&cpu->interrupt_request))) { int interrupt_request; @@ -596,8 +596,9 @@ static inline bool cpu_handle_interrupt(CPUState *cpu, } /* Finally, check if we need to exit to the main loop. */ - if (unlikely(atomic_read(&cpu->exit_request) - || (use_icount && cpu->icount_decr.u16.low + cpu->icount_extra == 0))) { + if (unlikely(atomic_read(&cpu->exit_request)) + || (use_icount + && cpu_neg(cpu)->icount_decr.u16.low + cpu->icount_extra == 0)) { atomic_set(&cpu->exit_request, 0); if (cpu->exception_index == -1) { cpu->exception_index = EXCP_INTERRUPT; @@ -624,7 +625,7 @@ static inline void cpu_loop_exec_tb(CPUState *cpu, TranslationBlock *tb, } *last_tb = NULL; - insns_left = atomic_read(&cpu->icount_decr.u32); + insns_left = atomic_read(&cpu_neg(cpu)->icount_decr.u32); if (insns_left < 0) { /* Something asked us to stop executing chained TBs; just * continue round the main loop. Whatever requested the exit @@ -643,7 +644,7 @@ static inline void cpu_loop_exec_tb(CPUState *cpu, TranslationBlock *tb, cpu_update_icount(cpu); /* Refill decrementer and continue execution. */ insns_left = MIN(0xffff, cpu->icount_budget); - cpu->icount_decr.u16.low = insns_left; + cpu_neg(cpu)->icount_decr.u16.low = insns_left; cpu->icount_extra = cpu->icount_budget - insns_left; if (!cpu->icount_extra) { /* Execute any remaining instructions, then let the main loop diff --git a/accel/tcg/tcg-all.c b/accel/tcg/tcg-all.c index 3d25bdcc17..9b215dcc5a 100644 --- a/accel/tcg/tcg-all.c +++ b/accel/tcg/tcg-all.c @@ -28,13 +28,12 @@ #include "sysemu/sysemu.h" #include "qom/object.h" #include "qemu-common.h" -#include "qom/cpu.h" +#include "cpu.h" #include "sysemu/cpus.h" #include "qemu/main-loop.h" unsigned long tcg_tb_size; -#ifndef CONFIG_USER_ONLY /* mask must never be zero, except for A20 change call */ static void tcg_handle_interrupt(CPUState *cpu, int mask) { @@ -51,7 +50,7 @@ static void tcg_handle_interrupt(CPUState *cpu, int mask) if (!qemu_cpu_is_self(cpu)) { qemu_cpu_kick(cpu); } else { - atomic_set(&cpu->icount_decr.u16.high, -1); + atomic_set(&cpu_neg(cpu)->icount_decr.u16.high, -1); if (use_icount && !cpu->can_do_io && (mask & ~old_mask) != 0) { @@ -59,7 +58,6 @@ static void tcg_handle_interrupt(CPUState *cpu, int mask) } } } -#endif static int tcg_init(MachineState *ms) { diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index 52d94facf0..e24ee3a172 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -364,7 +364,7 @@ static int cpu_restore_state_from_tb(CPUState *cpu, TranslationBlock *tb, assert(use_icount); /* Reset the cycle counter to the start of the block and shift if to the number of actually executed instructions */ - cpu->icount_decr.u16.low += num_insns - i; + cpu_neg(cpu)->icount_decr.u16.low += num_insns - i; } restore_state_to_opc(env, tb, data); @@ -2200,7 +2200,7 @@ void cpu_io_recompile(CPUState *cpu, uintptr_t retaddr) if ((env->hflags & MIPS_HFLAG_BMASK) != 0 && env->active_tc.PC != tb->pc) { env->active_tc.PC -= (env->hflags & MIPS_HFLAG_B16 ? 2 : 4); - cpu->icount_decr.u16.low++; + cpu_neg(cpu)->icount_decr.u16.low++; env->hflags &= ~MIPS_HFLAG_BMASK; n = 2; } @@ -2208,7 +2208,7 @@ void cpu_io_recompile(CPUState *cpu, uintptr_t retaddr) if ((env->flags & ((DELAY_SLOT | DELAY_SLOT_CONDITIONAL))) != 0 && env->pc != tb->pc) { env->pc -= 2; - cpu->icount_decr.u16.low++; + cpu_neg(cpu)->icount_decr.u16.low++; env->flags &= ~(DELAY_SLOT | DELAY_SLOT_CONDITIONAL); n = 2; } @@ -2382,7 +2382,7 @@ void cpu_interrupt(CPUState *cpu, int mask) { g_assert(qemu_mutex_iothread_locked()); cpu->interrupt_request |= mask; - atomic_set(&cpu->icount_decr.u16.high, -1); + atomic_set(&cpu_neg(cpu)->icount_decr.u16.high, -1); } /* diff --git a/cpus.c b/cpus.c index ffc57119ca..111ca4ed1c 100644 --- a/cpus.c +++ b/cpus.c @@ -239,7 +239,8 @@ void qemu_tcg_configure(QemuOpts *opts, Error **errp) */ static int64_t cpu_get_icount_executed(CPUState *cpu) { - return cpu->icount_budget - (cpu->icount_decr.u16.low + cpu->icount_extra); + return (cpu->icount_budget - + (cpu_neg(cpu)->icount_decr.u16.low + cpu->icount_extra)); } /* @@ -1389,12 +1390,12 @@ static void prepare_icount_for_run(CPUState *cpu) * each vCPU execution. However u16.high can be raised * asynchronously by cpu_exit/cpu_interrupt/tcg_handle_interrupt */ - g_assert(cpu->icount_decr.u16.low == 0); + g_assert(cpu_neg(cpu)->icount_decr.u16.low == 0); g_assert(cpu->icount_extra == 0); cpu->icount_budget = tcg_get_icount_limit(); insns_left = MIN(0xffff, cpu->icount_budget); - cpu->icount_decr.u16.low = insns_left; + cpu_neg(cpu)->icount_decr.u16.low = insns_left; cpu->icount_extra = cpu->icount_budget - insns_left; replay_mutex_lock(); @@ -1408,7 +1409,7 @@ static void process_icount_data(CPUState *cpu) cpu_update_icount(cpu); /* Reset the counters */ - cpu->icount_decr.u16.low = 0; + cpu_neg(cpu)->icount_decr.u16.low = 0; cpu->icount_extra = 0; cpu->icount_budget = 0; diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h index 5ae83405c8..253dd1d9a5 100644 --- a/include/exec/cpu-all.h +++ b/include/exec/cpu-all.h @@ -380,6 +380,7 @@ int cpu_exec(CPUState *cpu); static inline void cpu_set_cpustate_pointers(ArchCPU *cpu) { cpu->parent_obj.env_ptr = &cpu->env; + cpu->parent_obj.icount_decr_ptr = &cpu->neg.icount_decr; } /** diff --git a/include/exec/cpu-defs.h b/include/exec/cpu-defs.h index 921fbb4c36..c067994e5c 100644 --- a/include/exec/cpu-defs.h +++ b/include/exec/cpu-defs.h @@ -33,6 +33,7 @@ #include "exec/hwaddr.h" #endif #include "exec/memattrs.h" +#include "qom/cpu.h" #include "cpu-param.h" @@ -232,7 +233,7 @@ typedef struct CPUTLB { * before CPUArchState, as a field named "neg". */ typedef struct CPUNegativeOffsetState { - /* Empty */ + IcountDecr icount_decr; } CPUNegativeOffsetState; #endif diff --git a/include/exec/gen-icount.h b/include/exec/gen-icount.h index 9cfa6ccce5..f7669b6841 100644 --- a/include/exec/gen-icount.h +++ b/include/exec/gen-icount.h @@ -5,8 +5,6 @@ /* Helpers for instruction counting code generation. */ -#define ENV_OFFSET offsetof(ArchCPU, env) - static TCGOp *icount_start_insn; static inline void gen_tb_start(TranslationBlock *tb) @@ -21,7 +19,8 @@ static inline void gen_tb_start(TranslationBlock *tb) } tcg_gen_ld_i32(count, cpu_env, - -ENV_OFFSET + offsetof(CPUState, icount_decr.u32)); + offsetof(ArchCPU, neg.icount_decr.u32) - + offsetof(ArchCPU, env)); if (tb_cflags(tb) & CF_USE_ICOUNT) { imm = tcg_temp_new_i32(); @@ -39,7 +38,8 @@ static inline void gen_tb_start(TranslationBlock *tb) if (tb_cflags(tb) & CF_USE_ICOUNT) { tcg_gen_st16_i32(count, cpu_env, - -ENV_OFFSET + offsetof(CPUState, icount_decr.u16.low)); + offsetof(ArchCPU, neg.icount_decr.u16.low) - + offsetof(ArchCPU, env)); } tcg_temp_free_i32(count); @@ -60,14 +60,18 @@ static inline void gen_tb_end(TranslationBlock *tb, int num_insns) static inline void gen_io_start(void) { TCGv_i32 tmp = tcg_const_i32(1); - tcg_gen_st_i32(tmp, cpu_env, -ENV_OFFSET + offsetof(CPUState, can_do_io)); + tcg_gen_st_i32(tmp, cpu_env, + offsetof(ArchCPU, parent_obj.can_do_io) - + offsetof(ArchCPU, env)); tcg_temp_free_i32(tmp); } static inline void gen_io_end(void) { TCGv_i32 tmp = tcg_const_i32(0); - tcg_gen_st_i32(tmp, cpu_env, -ENV_OFFSET + offsetof(CPUState, can_do_io)); + tcg_gen_st_i32(tmp, cpu_env, + offsetof(ArchCPU, parent_obj.can_do_io) - + offsetof(ArchCPU, env)); tcg_temp_free_i32(tmp); } diff --git a/include/qom/cpu.h b/include/qom/cpu.h index 98e12d914c..5ee0046b62 100644 --- a/include/qom/cpu.h +++ b/include/qom/cpu.h @@ -232,17 +232,25 @@ typedef struct CPUClass { bool gdb_stop_before_watchpoint; } CPUClass; +/* + * Low 16 bits: number of cycles left, used only in icount mode. + * High 16 bits: Set to -1 to force TCG to stop executing linked TBs + * for this CPU and return to its top level loop (even in non-icount mode). + * This allows a single read-compare-cbranch-write sequence to test + * for both decrementer underflow and exceptions. + */ +typedef union IcountDecr { + uint32_t u32; + struct { #ifdef HOST_WORDS_BIGENDIAN -typedef struct icount_decr_u16 { - uint16_t high; - uint16_t low; -} icount_decr_u16; + uint16_t high; + uint16_t low; #else -typedef struct icount_decr_u16 { - uint16_t low; - uint16_t high; -} icount_decr_u16; + uint16_t low; + uint16_t high; #endif + } u16; +} IcountDecr; typedef struct CPUBreakpoint { vaddr pc; @@ -314,11 +322,6 @@ struct qemu_work_item; * @crash_occurred: Indicates the OS reported a crash (panic) for this CPU * @singlestep_enabled: Flags for single-stepping. * @icount_extra: Instructions until next timer event. - * @icount_decr: Low 16 bits: number of cycles left, only used in icount mode. - * High 16 bits: Set to -1 to force TCG to stop executing linked TBs for this - * CPU and return to its top level loop (even in non-icount mode). - * This allows a single read-compare-cbranch-write sequence to test - * for both decrementer underflow and exceptions. * @can_do_io: Nonzero if memory-mapped IO is safe. Deterministic execution * requires that IO only be performed on the last instruction of a TB * so that interrupts take effect immediately. @@ -328,6 +331,7 @@ struct qemu_work_item; * @as: Pointer to the first AddressSpace, for the convenience of targets which * only have a single AddressSpace * @env_ptr: Pointer to subclass-specific CPUArchState field. + * @icount_decr_ptr: Pointer to IcountDecr field within subclass. * @gdb_regs: Additional GDB registers. * @gdb_num_regs: Number of total registers accessible to GDB. * @gdb_num_g_regs: Number of registers in GDB 'g' packets. @@ -387,6 +391,7 @@ struct CPUState { MemoryRegion *memory; void *env_ptr; /* CPUArchState */ + IcountDecr *icount_decr_ptr; /* Accessed in parallel; all accesses must be atomic */ struct TranslationBlock *tb_jmp_cache[TB_JMP_CACHE_SIZE]; @@ -441,15 +446,6 @@ struct CPUState { bool ignore_memory_transaction_failures; - /* Note that this is accessed at the start of every TB via a negative - offset from AREG0. Leave this field at the end so as to make the - (absolute value) offset as small as possible. This reduces code - size, especially for hosts without large memory offsets. */ - union { - uint32_t u32; - icount_decr_u16 u16; - } icount_decr; - struct hax_vcpu_state *hax_vcpu; int hvf_fd; diff --git a/qom/cpu.c b/qom/cpu.c index 3c5493c96c..6b4632abda 100644 --- a/qom/cpu.c +++ b/qom/cpu.c @@ -115,7 +115,7 @@ void cpu_exit(CPUState *cpu) atomic_set(&cpu->exit_request, 1); /* Ensure cpu_exec will see the exit request after TCG has exited. */ smp_wmb(); - atomic_set(&cpu->icount_decr.u16.high, -1); + atomic_set(&cpu->icount_decr_ptr->u16.high, -1); } int cpu_write_elf32_qemunote(WriteCoreDumpFunction f, CPUState *cpu, @@ -264,7 +264,7 @@ static void cpu_common_reset(CPUState *cpu) cpu->mem_io_pc = 0; cpu->mem_io_vaddr = 0; cpu->icount_extra = 0; - atomic_set(&cpu->icount_decr.u32, 0); + atomic_set(&cpu->icount_decr_ptr->u32, 0); cpu->can_do_io = 1; cpu->exception_index = -1; cpu->crash_occurred = false; -- cgit 1.4.1 From 269bd5d8f61c6b0825ed3c6a5fe01a3ad71c3b4a Mon Sep 17 00:00:00 2001 From: Richard Henderson Date: Fri, 22 Mar 2019 22:03:39 -0700 Subject: cpu: Move the softmmu tlb to CPUNegativeOffsetState We have for some time had code within the tcg backends to handle large positive offsets from env. This move makes sure that need not happen. Indeed, we are able to assert at build time that simple offsets suffice for all hosts. Reviewed-by: Alistair Francis Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- include/exec/cpu-all.h | 11 +++++++++++ include/exec/cpu-defs.h | 20 +++++++++++++------- tcg/aarch64/tcg-target.inc.c | 29 ++++++----------------------- tcg/arm/tcg-target.inc.c | 40 ++++++++-------------------------------- tcg/i386/tcg-target.inc.c | 6 ++++-- tcg/mips/tcg-target.inc.c | 39 +++++++++------------------------------ tcg/ppc/tcg-target.inc.c | 30 +++++++++--------------------- tcg/riscv/tcg-target.inc.c | 31 +++++++------------------------ tcg/s390/tcg-target.inc.c | 11 ++++++----- tcg/sparc/tcg-target.inc.c | 32 ++++++++++---------------------- 10 files changed, 83 insertions(+), 166 deletions(-) (limited to 'include/exec') diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h index 253dd1d9a5..f4fed7d82e 100644 --- a/include/exec/cpu-all.h +++ b/include/exec/cpu-all.h @@ -429,4 +429,15 @@ static inline CPUNegativeOffsetState *cpu_neg(CPUState *cpu) return &arch_cpu->neg; } +/** + * env_tlb(env) + * @env: The architecture environment + * + * Return the CPUTLB state associated with the environment. + */ +static inline CPUTLB *env_tlb(CPUArchState *env) +{ + return &env_neg(env)->tlb; +} + #endif /* CPU_ALL_H */ diff --git a/include/exec/cpu-defs.h b/include/exec/cpu-defs.h index c067994e5c..006f8db9cf 100644 --- a/include/exec/cpu-defs.h +++ b/include/exec/cpu-defs.h @@ -178,13 +178,14 @@ typedef struct CPUTLBDesc { /* * Data elements that are per MMU mode, accessed by the fast path. + * The structure is aligned to aid loading the pair with one insn. */ typedef struct CPUTLBDescFast { /* Contains (n_entries - 1) << CPU_TLB_ENTRY_BITS */ uintptr_t mask; /* The array of tlb entries itself. */ CPUTLBEntry *table; -} CPUTLBDescFast; +} CPUTLBDescFast QEMU_ALIGNED(2 * sizeof(void *)); /* * Data elements that are shared between all MMU modes. @@ -211,28 +212,33 @@ typedef struct CPUTLBCommon { /* * The entire softmmu tlb, for all MMU modes. * The meaning of each of the MMU modes is defined in the target code. + * Since this is placed within CPUNegativeOffsetState, the smallest + * negative offsets are at the end of the struct. */ typedef struct CPUTLB { - CPUTLBDescFast f[NB_MMU_MODES]; - CPUTLBDesc d[NB_MMU_MODES]; CPUTLBCommon c; + CPUTLBDesc d[NB_MMU_MODES]; + CPUTLBDescFast f[NB_MMU_MODES]; } CPUTLB; -/* There are target-specific members named "tlb". This is temporary. */ -#define CPU_COMMON CPUTLB tlb_; -#define env_tlb(ENV) (&(ENV)->tlb_) +/* This will be used by TCG backends to compute offsets. */ +#define TLB_MASK_TABLE_OFS(IDX) \ + ((int)offsetof(ArchCPU, neg.tlb.f[IDX]) - (int)offsetof(ArchCPU, env)) #else -#define CPU_COMMON /* Nothing */ +typedef struct CPUTLB { } CPUTLB; #endif /* !CONFIG_USER_ONLY && CONFIG_TCG */ +#define CPU_COMMON /* Nothing */ + /* * This structure must be placed in ArchCPU immedately * before CPUArchState, as a field named "neg". */ typedef struct CPUNegativeOffsetState { + CPUTLB tlb; IcountDecr icount_decr; } CPUNegativeOffsetState; diff --git a/tcg/aarch64/tcg-target.inc.c b/tcg/aarch64/tcg-target.inc.c index 90957593a3..57c297f9d7 100644 --- a/tcg/aarch64/tcg-target.inc.c +++ b/tcg/aarch64/tcg-target.inc.c @@ -1637,9 +1637,9 @@ static void add_qemu_ldst_label(TCGContext *s, bool is_ld, TCGMemOpIdx oi, label->label_ptr[0] = label_ptr; } -/* We expect to use a 24-bit unsigned offset from ENV. */ -QEMU_BUILD_BUG_ON(offsetof(CPUArchState, tlb_.f[NB_MMU_MODES - 1].table) - > 0xffffff); +/* We expect to use a 7-bit scaled negative offset from ENV. */ +QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) > 0); +QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) < -512); /* Load and compare a TLB entry, emitting the conditional jump to the slow path for the failure case, which will be patched later when finalizing @@ -1649,8 +1649,9 @@ static void tcg_out_tlb_read(TCGContext *s, TCGReg addr_reg, TCGMemOp opc, tcg_insn_unit **label_ptr, int mem_index, bool is_read) { - int mask_ofs = offsetof(CPUArchState, tlb_.f[mem_index].mask); - int table_ofs = offsetof(CPUArchState, tlb_.f[mem_index].table); + int fast_ofs = TLB_MASK_TABLE_OFS(mem_index); + int mask_ofs = fast_ofs + offsetof(CPUTLBDescFast, mask); + int table_ofs = fast_ofs + offsetof(CPUTLBDescFast, table); unsigned a_bits = get_alignment_bits(opc); unsigned s_bits = opc & MO_SIZE; unsigned a_mask = (1u << a_bits) - 1; @@ -1659,24 +1660,6 @@ static void tcg_out_tlb_read(TCGContext *s, TCGReg addr_reg, TCGMemOp opc, TCGType mask_type; uint64_t compare_mask; - if (table_ofs > 0xfff) { - int table_hi = table_ofs & ~0xfff; - int mask_hi = mask_ofs & ~0xfff; - - table_base = TCG_REG_X1; - if (mask_hi == table_hi) { - mask_base = table_base; - } else if (mask_hi) { - mask_base = TCG_REG_X0; - tcg_out_insn(s, 3401, ADDI, TCG_TYPE_I64, - mask_base, TCG_AREG0, mask_hi); - } - tcg_out_insn(s, 3401, ADDI, TCG_TYPE_I64, - table_base, TCG_AREG0, table_hi); - mask_ofs -= mask_hi; - table_ofs -= table_hi; - } - mask_type = (TARGET_PAGE_BITS + CPU_TLB_DYN_MAX_BITS > 32 ? TCG_TYPE_I64 : TCG_TYPE_I32); diff --git a/tcg/arm/tcg-target.inc.c b/tcg/arm/tcg-target.inc.c index 38de6d59c7..b066e30f0e 100644 --- a/tcg/arm/tcg-target.inc.c +++ b/tcg/arm/tcg-target.inc.c @@ -1220,9 +1220,9 @@ static TCGReg tcg_out_arg_reg64(TCGContext *s, TCGReg argreg, #define TLB_SHIFT (CPU_TLB_ENTRY_BITS + CPU_TLB_BITS) -/* We expect to use a 20-bit unsigned offset from ENV. */ -QEMU_BUILD_BUG_ON(offsetof(CPUArchState, tlb_.f[NB_MMU_MODES - 1].table) - > 0xfffff); +/* We expect to use an 9-bit sign-magnitude negative offset from ENV. */ +QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) > 0); +QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) < -256); /* Load and compare a TLB entry, leaving the flags set. Returns the register containing the addend of the tlb entry. Clobbers R0, R1, R2, TMP. */ @@ -1232,39 +1232,15 @@ static TCGReg tcg_out_tlb_read(TCGContext *s, TCGReg addrlo, TCGReg addrhi, { int cmp_off = (is_load ? offsetof(CPUTLBEntry, addr_read) : offsetof(CPUTLBEntry, addr_write)); - int mask_off = offsetof(CPUArchState, tlb_.f[mem_index].mask); - int table_off = offsetof(CPUArchState, tlb_.f[mem_index].table); - TCGReg mask_base = TCG_AREG0, table_base = TCG_AREG0; + int fast_off = TLB_MASK_TABLE_OFS(mem_index); + int mask_off = fast_off + offsetof(CPUTLBDescFast, mask); + int table_off = fast_off + offsetof(CPUTLBDescFast, table); unsigned s_bits = opc & MO_SIZE; unsigned a_bits = get_alignment_bits(opc); - if (table_off > 0xfff) { - int mask_hi = mask_off & ~0xfff; - int table_hi = table_off & ~0xfff; - int rot; - - table_base = TCG_REG_R2; - if (mask_hi == table_hi) { - mask_base = table_base; - } else if (mask_hi) { - mask_base = TCG_REG_TMP; - rot = encode_imm(mask_hi); - assert(rot >= 0); - tcg_out_dat_imm(s, COND_AL, ARITH_ADD, mask_base, TCG_AREG0, - rotl(mask_hi, rot) | (rot << 7)); - } - rot = encode_imm(table_hi); - assert(rot >= 0); - tcg_out_dat_imm(s, COND_AL, ARITH_ADD, table_base, TCG_AREG0, - rotl(table_hi, rot) | (rot << 7)); - - mask_off -= mask_hi; - table_off -= table_hi; - } - /* Load tlb_mask[mmu_idx] and tlb_table[mmu_idx]. */ - tcg_out_ld(s, TCG_TYPE_I32, TCG_REG_TMP, mask_base, mask_off); - tcg_out_ld(s, TCG_TYPE_I32, TCG_REG_R2, table_base, table_off); + tcg_out_ld(s, TCG_TYPE_I32, TCG_REG_TMP, TCG_AREG0, mask_off); + tcg_out_ld(s, TCG_TYPE_I32, TCG_REG_R2, TCG_AREG0, table_off); /* Extract the tlb index from the address into TMP. */ tcg_out_dat_reg(s, COND_AL, ARITH_AND, TCG_REG_TMP, TCG_REG_TMP, addrlo, diff --git a/tcg/i386/tcg-target.inc.c b/tcg/i386/tcg-target.inc.c index 5f5b886c04..6ddeebf4bc 100644 --- a/tcg/i386/tcg-target.inc.c +++ b/tcg/i386/tcg-target.inc.c @@ -1730,10 +1730,12 @@ static inline void tcg_out_tlb_load(TCGContext *s, TCGReg addrlo, TCGReg addrhi, TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS); tcg_out_modrm_offset(s, OPC_AND_GvEv + trexw, r0, TCG_AREG0, - offsetof(CPUArchState, tlb_.f[mem_index].mask)); + TLB_MASK_TABLE_OFS(mem_index) + + offsetof(CPUTLBDescFast, mask)); tcg_out_modrm_offset(s, OPC_ADD_GvEv + hrexw, r0, TCG_AREG0, - offsetof(CPUArchState, tlb_.f[mem_index].table)); + TLB_MASK_TABLE_OFS(mem_index) + + offsetof(CPUTLBDescFast, table)); /* If the required alignment is at least as large as the access, simply copy the address and mask. For lesser alignments, check that we don't diff --git a/tcg/mips/tcg-target.inc.c b/tcg/mips/tcg-target.inc.c index ef6633587e..41bff32fb4 100644 --- a/tcg/mips/tcg-target.inc.c +++ b/tcg/mips/tcg-target.inc.c @@ -1202,6 +1202,10 @@ static int tcg_out_call_iarg_reg2(TCGContext *s, int i, TCGReg al, TCGReg ah) return i; } +/* We expect to use a 16-bit negative offset from ENV. */ +QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) > 0); +QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) < -32768); + /* * Perform the tlb comparison operation. * The complete host address is placed in BASE. @@ -1215,42 +1219,17 @@ static void tcg_out_tlb_load(TCGContext *s, TCGReg base, TCGReg addrl, unsigned s_bits = opc & MO_SIZE; unsigned a_bits = get_alignment_bits(opc); int mem_index = get_mmuidx(oi); - int mask_off = offsetof(CPUArchState, tlb_.f[mem_index].mask); - int table_off = offsetof(CPUArchState, tlb_.f[mem_index].mask); + int fast_off = TLB_MASK_TABLE_OFS(mem_index); + int mask_off = fast_off + offsetof(CPUTLBDescFast, mask); + int table_off = fast_off + offsetof(CPUTLBDescFast, table); int add_off = offsetof(CPUTLBEntry, addend); int cmp_off = (is_load ? offsetof(CPUTLBEntry, addr_read) : offsetof(CPUTLBEntry, addr_write)); - TCGReg mask_base = TCG_AREG0, table_base = TCG_AREG0; target_ulong mask; - if (table_off > 0x7fff) { - int mask_hi = mask_off - (int16_t)mask_off; - int table_hi = table_off - (int16_t)table_off; - - table_base = TCG_TMP1; - if (likely(mask_hi == table_hi)) { - mask_base = table_base; - tcg_out_opc_imm(s, OPC_LUI, mask_base, TCG_REG_ZERO, mask_hi >> 16); - tcg_out_opc_reg(s, ALIAS_PADD, mask_base, mask_base, TCG_AREG0); - mask_off -= mask_hi; - table_off -= mask_hi; - } else { - if (mask_hi != 0) { - mask_base = TCG_TMP0; - tcg_out_opc_imm(s, OPC_LUI, - mask_base, TCG_REG_ZERO, mask_hi >> 16); - tcg_out_opc_reg(s, ALIAS_PADD, - mask_base, mask_base, TCG_AREG0); - } - table_off -= mask_off; - mask_off -= mask_hi; - tcg_out_opc_imm(s, ALIAS_PADDI, table_base, mask_base, mask_off); - } - } - /* Load tlb_mask[mmu_idx] and tlb_table[mmu_idx]. */ - tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP0, mask_base, mask_off); - tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP1, table_base, table_off); + tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP0, TCG_AREG0, mask_off); + tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP1, TCG_AREG0, table_off); /* Extract the TLB index from the address into TMP3. */ tcg_out_opc_sa(s, ALIAS_TSRL, TCG_TMP3, addrl, diff --git a/tcg/ppc/tcg-target.inc.c b/tcg/ppc/tcg-target.inc.c index d69c18ac1e..852b8940fb 100644 --- a/tcg/ppc/tcg-target.inc.c +++ b/tcg/ppc/tcg-target.inc.c @@ -1498,6 +1498,10 @@ static void * const qemu_st_helpers[16] = { [MO_BEQ] = helper_be_stq_mmu, }; +/* We expect to use a 16-bit negative offset from ENV. */ +QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) > 0); +QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) < -32768); + /* Perform the TLB load and compare. Places the result of the comparison in CR7, loads the addend of the TLB into R3, and returns the register containing the guest address (zero-extended into R4). Clobbers R0 and R2. */ @@ -1510,31 +1514,15 @@ static TCGReg tcg_out_tlb_read(TCGContext *s, TCGMemOp opc, = (is_read ? offsetof(CPUTLBEntry, addr_read) : offsetof(CPUTLBEntry, addr_write)); - int mask_off = offsetof(CPUArchState, tlb_.f[mem_index].mask); - int table_off = offsetof(CPUArchState, tlb_.f[mem_index].table); - TCGReg mask_base = TCG_AREG0, table_base = TCG_AREG0; + int fast_off = TLB_MASK_TABLE_OFS(mem_index); + int mask_off = fast_off + offsetof(CPUTLBDescFast, mask); + int table_off = fast_off + offsetof(CPUTLBDescFast, table); unsigned s_bits = opc & MO_SIZE; unsigned a_bits = get_alignment_bits(opc); - if (table_off > 0x7fff) { - int mask_hi = mask_off - (int16_t)mask_off; - int table_hi = table_off - (int16_t)table_off; - - table_base = TCG_REG_R4; - if (mask_hi == table_hi) { - mask_base = table_base; - } else if (mask_hi) { - mask_base = TCG_REG_R3; - tcg_out32(s, ADDIS | TAI(mask_base, TCG_AREG0, mask_hi >> 16)); - } - tcg_out32(s, ADDIS | TAI(table_base, TCG_AREG0, table_hi >> 16)); - mask_off -= mask_hi; - table_off -= table_hi; - } - /* Load tlb_mask[mmu_idx] and tlb_table[mmu_idx]. */ - tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_R3, mask_base, mask_off); - tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_R4, table_base, table_off); + tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_R3, TCG_AREG0, mask_off); + tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_R4, TCG_AREG0, table_off); /* Extract the page index, shifted into place for tlb index. */ if (TCG_TARGET_REG_BITS == 32) { diff --git a/tcg/riscv/tcg-target.inc.c b/tcg/riscv/tcg-target.inc.c index 96c33bf621..1f0ae64aae 100644 --- a/tcg/riscv/tcg-target.inc.c +++ b/tcg/riscv/tcg-target.inc.c @@ -962,6 +962,10 @@ static void * const qemu_st_helpers[16] = { /* We don't support oversize guests */ QEMU_BUILD_BUG_ON(TCG_TARGET_REG_BITS < TARGET_LONG_BITS); +/* We expect to use a 12-bit negative offset from ENV. */ +QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) > 0); +QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) < -(1 << 11)); + static void tcg_out_tlb_load(TCGContext *s, TCGReg addrl, TCGReg addrh, TCGMemOpIdx oi, tcg_insn_unit **label_ptr, bool is_load) @@ -971,32 +975,11 @@ static void tcg_out_tlb_load(TCGContext *s, TCGReg addrl, unsigned a_bits = get_alignment_bits(opc); tcg_target_long compare_mask; int mem_index = get_mmuidx(oi); - int mask_off, table_off; + int fast_ofs = TLB_MASK_TABLE_OFS(mem_index); + int mask_ofs = fast_ofs + offsetof(CPUTLBDescFast, mask); + int table_ofs = fast_ofs + offsetof(CPUTLBDescFast, table); TCGReg mask_base = TCG_AREG0, table_base = TCG_AREG0; - mask_off = offsetof(CPUArchState, tlb_.f[mem_index].mask); - table_off = offsetof(CPUArchState, tlb_.f[mem_index].table); - if (table_off > 0x7ff) { - int mask_hi = mask_off - sextreg(mask_off, 0, 12); - int table_hi = table_off - sextreg(table_off, 0, 12); - - if (likely(mask_hi == table_hi)) { - mask_base = table_base = TCG_REG_TMP1; - tcg_out_opc_upper(s, OPC_LUI, mask_base, mask_hi); - tcg_out_opc_reg(s, OPC_ADD, mask_base, mask_base, TCG_AREG0); - mask_off -= mask_hi; - table_off -= mask_hi; - } else { - mask_base = TCG_REG_TMP0; - table_base = TCG_REG_TMP1; - tcg_out_opc_upper(s, OPC_LUI, mask_base, mask_hi); - tcg_out_opc_reg(s, OPC_ADD, mask_base, mask_base, TCG_AREG0); - table_off -= mask_off; - mask_off -= mask_hi; - tcg_out_opc_imm(s, OPC_ADDI, table_base, mask_base, mask_off); - } - } - tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP0, mask_base, mask_off); tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP1, table_base, table_off); diff --git a/tcg/s390/tcg-target.inc.c b/tcg/s390/tcg-target.inc.c index 4d896d0b58..fe42939d98 100644 --- a/tcg/s390/tcg-target.inc.c +++ b/tcg/s390/tcg-target.inc.c @@ -1538,9 +1538,9 @@ static void tcg_out_qemu_st_direct(TCGContext *s, TCGMemOp opc, TCGReg data, #if defined(CONFIG_SOFTMMU) #include "tcg-ldst.inc.c" -/* We're expecting to use a 20-bit signed offset on the tlb memory ops. */ -QEMU_BUILD_BUG_ON(offsetof(CPUArchState, tlb_.f[NB_MMU_MODES - 1].table) - > 0x7ffff); +/* We're expecting to use a 20-bit negative offset on the tlb memory ops. */ +QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) > 0); +QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) < -(1 << 19)); /* Load and compare a TLB entry, leaving the flags set. Loads the TLB addend into R2. Returns a register with the santitized guest address. */ @@ -1551,8 +1551,9 @@ static TCGReg tcg_out_tlb_read(TCGContext* s, TCGReg addr_reg, TCGMemOp opc, unsigned a_bits = get_alignment_bits(opc); unsigned s_mask = (1 << s_bits) - 1; unsigned a_mask = (1 << a_bits) - 1; - int mask_off = offsetof(CPUArchState, tlb_.f[mem_index].mask); - int table_off = offsetof(CPUArchState, tlb_.f[mem_index].table); + int fast_off = TLB_MASK_TABLE_OFS(mem_index); + int mask_off = fast_off + offsetof(CPUTLBDescFast, mask); + int table_off = fast_off + offsetof(CPUTLBDescFast, table); int ofs, a_off; uint64_t tlb_mask; diff --git a/tcg/sparc/tcg-target.inc.c b/tcg/sparc/tcg-target.inc.c index 066cb0e892..10b1cea63b 100644 --- a/tcg/sparc/tcg-target.inc.c +++ b/tcg/sparc/tcg-target.inc.c @@ -1062,6 +1062,11 @@ static void tcg_out_nop_fill(tcg_insn_unit *p, int count) } #if defined(CONFIG_SOFTMMU) + +/* We expect to use a 13-bit negative offset from ENV. */ +QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) > 0); +QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) < -(1 << 12)); + /* Perform the TLB load and compare. Inputs: @@ -1078,9 +1083,9 @@ static void tcg_out_nop_fill(tcg_insn_unit *p, int count) static TCGReg tcg_out_tlb_load(TCGContext *s, TCGReg addr, int mem_index, TCGMemOp opc, int which) { - int mask_off = offsetof(CPUArchState, tlb_.f[mem_index].mask); - int table_off = offsetof(CPUArchState, tlb_.f[mem_index].table); - TCGReg base = TCG_AREG0; + int fast_off = TLB_MASK_TABLE_OFS(mem_index); + int mask_off = fast_off + offsetof(CPUTLBDescFast, mask); + int table_off = fast_off + offsetof(CPUTLBDescFast, table); const TCGReg r0 = TCG_REG_O0; const TCGReg r1 = TCG_REG_O1; const TCGReg r2 = TCG_REG_O2; @@ -1088,26 +1093,9 @@ static TCGReg tcg_out_tlb_load(TCGContext *s, TCGReg addr, int mem_index, unsigned a_bits = get_alignment_bits(opc); tcg_target_long compare_mask; - if (!check_fit_i32(table_off, 13)) { - int table_hi; - - base = r1; - if (table_off <= 2 * 0xfff) { - table_hi = 0xfff; - tcg_out_arithi(s, base, TCG_AREG0, table_hi, ARITH_ADD); - } else { - table_hi = table_off & ~0x3ff; - tcg_out_sethi(s, base, table_hi); - tcg_out_arith(s, base, TCG_AREG0, base, ARITH_ADD); - } - mask_off -= table_hi; - table_off -= table_hi; - tcg_debug_assert(check_fit_i32(mask_off, 13)); - } - /* Load tlb_mask[mmu_idx] and tlb_table[mmu_idx]. */ - tcg_out_ld(s, TCG_TYPE_PTR, r0, base, mask_off); - tcg_out_ld(s, TCG_TYPE_PTR, r1, base, table_off); + tcg_out_ld(s, TCG_TYPE_PTR, r0, TCG_AREG0, mask_off); + tcg_out_ld(s, TCG_TYPE_PTR, r1, TCG_AREG0, table_off); /* Extract the page index, shifted into place for tlb index. */ tcg_out_arithi(s, r2, addr, TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS, -- cgit 1.4.1 From e8b5fae5161c48e0d0e8b35eaf9dd8f35d692088 Mon Sep 17 00:00:00 2001 From: Richard Henderson Date: Sat, 23 Mar 2019 11:35:53 -0700 Subject: cpu: Remove CPU_COMMON This macro is now always empty, so remove it. This leaves the entire contents of CPUArchState under the control of the guest architecture. Reviewed-by: Alistair Francis Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- include/exec/cpu-defs.h | 2 -- target/alpha/cpu.h | 3 --- target/arm/cpu.h | 4 +--- target/cris/cpu.h | 2 -- target/hppa/cpu.h | 3 --- target/i386/cpu.h | 4 +--- target/lm32/cpu.h | 2 -- target/m68k/cpu.h | 2 -- target/microblaze/cpu.h | 2 -- target/mips/cpu.h | 2 -- target/moxie/cpu.h | 3 --- target/nios2/cpu.h | 2 -- target/openrisc/cpu.h | 2 -- target/ppc/cpu.h | 2 -- target/riscv/cpu.h | 3 --- target/s390x/cpu.h | 2 -- target/sh4/cpu.h | 2 -- target/sparc/cpu.h | 2 -- target/tilegx/cpu.h | 2 -- target/tricore/cpu.h | 2 -- target/unicore32/cpu.h | 2 -- target/xtensa/cpu.h | 2 -- 22 files changed, 2 insertions(+), 50 deletions(-) (limited to 'include/exec') diff --git a/include/exec/cpu-defs.h b/include/exec/cpu-defs.h index 006f8db9cf..9bc713a70b 100644 --- a/include/exec/cpu-defs.h +++ b/include/exec/cpu-defs.h @@ -231,8 +231,6 @@ typedef struct CPUTLB { } CPUTLB; #endif /* !CONFIG_USER_ONLY && CONFIG_TCG */ -#define CPU_COMMON /* Nothing */ - /* * This structure must be placed in ArchCPU immedately * before CPUArchState, as a field named "neg". diff --git a/target/alpha/cpu.h b/target/alpha/cpu.h index 94fbc00a3b..5d6fb222b5 100644 --- a/target/alpha/cpu.h +++ b/target/alpha/cpu.h @@ -251,9 +251,6 @@ struct CPUAlphaState { /* This alarm doesn't exist in real hardware; we wish it did. */ uint64_t alarm_expire; - /* Those resources are used only in QEMU core */ - CPU_COMMON - int error_code; uint32_t features; diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 5965c52f0c..8fa9772c9d 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -645,9 +645,7 @@ typedef struct CPUARMState { /* Fields up to this point are cleared by a CPU reset */ struct {} end_reset_fields; - CPU_COMMON - - /* Fields after CPU_COMMON are preserved across CPU reset. */ + /* Fields after this point are preserved across CPU reset. */ /* Internal CPU feature flags. */ uint64_t features; diff --git a/target/cris/cpu.h b/target/cris/cpu.h index ad93d1a9ee..9d2a80d995 100644 --- a/target/cris/cpu.h +++ b/target/cris/cpu.h @@ -163,8 +163,6 @@ typedef struct CPUCRISState { /* Fields up to this point are cleared by a CPU reset */ struct {} end_reset_fields; - CPU_COMMON - /* Members from load_info on are preserved across resets. */ void *load_info; } CPUCRISState; diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h index f7c6205218..c7db2eca9a 100644 --- a/target/hppa/cpu.h +++ b/target/hppa/cpu.h @@ -197,9 +197,6 @@ struct CPUHPPAState { target_ureg cr_back[2]; /* back of cr17/cr18 */ target_ureg shadow[7]; /* shadow registers */ - /* Those resources are used only in QEMU core */ - CPU_COMMON - /* ??? The number of entries isn't specified by the architecture. */ /* ??? Implement a unified itlb/dtlb for the moment. */ /* ??? We should use a more intelligent data structure. */ diff --git a/target/i386/cpu.h b/target/i386/cpu.h index e7580a86e5..edad6e1efb 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -1289,9 +1289,7 @@ typedef struct CPUX86State { /* Fields up to this point are cleared by a CPU reset */ struct {} end_reset_fields; - CPU_COMMON - - /* Fields after CPU_COMMON are preserved across CPU reset. */ + /* Fields after this point are preserved across CPU reset. */ /* processor features (e.g. for CPUID insn) */ /* Minimum level/xlevel/xlevel2, based on CPU model + features */ diff --git a/target/lm32/cpu.h b/target/lm32/cpu.h index 324bc90f81..3e10a693a3 100644 --- a/target/lm32/cpu.h +++ b/target/lm32/cpu.h @@ -159,8 +159,6 @@ struct CPULM32State { /* Fields up to this point are cleared by a CPU reset */ struct {} end_reset_fields; - CPU_COMMON - /* Fields from here on are preserved across CPU reset. */ uint32_t eba; /* exception base address */ uint32_t deba; /* debug exception base address */ diff --git a/target/m68k/cpu.h b/target/m68k/cpu.h index d92263b750..1ebd360afb 100644 --- a/target/m68k/cpu.h +++ b/target/m68k/cpu.h @@ -143,8 +143,6 @@ typedef struct CPUM68KState { /* Fields up to this point are cleared by a CPU reset */ struct {} end_reset_fields; - CPU_COMMON - /* Fields from here on are preserved across CPU reset. */ uint32_t features; } CPUM68KState; diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h index d90c4fbcb5..98b4d915d7 100644 --- a/target/microblaze/cpu.h +++ b/target/microblaze/cpu.h @@ -266,8 +266,6 @@ struct CPUMBState { /* Fields up to this point are cleared by a CPU reset */ struct {} end_reset_fields; - CPU_COMMON - /* These fields are preserved on reset. */ struct { diff --git a/target/mips/cpu.h b/target/mips/cpu.h index 62af24937d..bbf1aa8b0d 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -1041,8 +1041,6 @@ struct CPUMIPSState { /* Fields up to this point are cleared by a CPU reset */ struct {} end_reset_fields; - CPU_COMMON - /* Fields from here on are preserved across CPU reset. */ CPUMIPSMVPContext *mvp; #if !defined(CONFIG_USER_ONLY) diff --git a/target/moxie/cpu.h b/target/moxie/cpu.h index c6b681531d..2b596d5d45 100644 --- a/target/moxie/cpu.h +++ b/target/moxie/cpu.h @@ -45,9 +45,6 @@ typedef struct CPUMoxieState { /* Fields up to this point are cleared by a CPU reset */ struct {} end_reset_fields; - - CPU_COMMON - } CPUMoxieState; #include "qom/cpu.h" diff --git a/target/nios2/cpu.h b/target/nios2/cpu.h index 8cc3d4971e..e40ee27e53 100644 --- a/target/nios2/cpu.h +++ b/target/nios2/cpu.h @@ -167,8 +167,6 @@ struct CPUNios2State { uint32_t irq_pending; #endif - - CPU_COMMON }; /** diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h index 51723e9312..9b80834d68 100644 --- a/target/openrisc/cpu.h +++ b/target/openrisc/cpu.h @@ -286,8 +286,6 @@ typedef struct CPUOpenRISCState { /* Fields up to this point are cleared by a CPU reset */ struct {} end_reset_fields; - CPU_COMMON - /* Fields from here on are preserved across CPU reset. */ uint32_t cpucfgr; /* CPU configure register */ diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index e8962e4655..c93ebc4c10 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -999,8 +999,6 @@ struct CPUPPCState { /* when a memory exception occurs, the access type is stored here */ int access_type; - CPU_COMMON - /* MMU context - only relevant for full system emulation */ #if !defined(CONFIG_USER_ONLY) #if defined(TARGET_PPC64) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 0ed7031915..a935b17dbd 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -171,9 +171,6 @@ struct CPURISCVState { float_status fp_status; - /* QEMU */ - CPU_COMMON - /* Fields from here on are preserved across CPU reset. */ QEMUTimer *timer; /* Internal timer */ }; diff --git a/target/s390x/cpu.h b/target/s390x/cpu.h index 21688b7c8c..cb103bc3e7 100644 --- a/target/s390x/cpu.h +++ b/target/s390x/cpu.h @@ -114,8 +114,6 @@ struct CPUS390XState { /* Fields up to this point are cleared by a CPU reset */ struct {} end_reset_fields; - CPU_COMMON - #if !defined(CONFIG_USER_ONLY) uint32_t core_id; /* PoP "CPU address", same as cpu_index */ uint64_t cpuid; diff --git a/target/sh4/cpu.h b/target/sh4/cpu.h index e266db411f..08cf275f79 100644 --- a/target/sh4/cpu.h +++ b/target/sh4/cpu.h @@ -179,8 +179,6 @@ typedef struct CPUSH4State { /* Fields up to this point are cleared by a CPU reset */ struct {} end_reset_fields; - CPU_COMMON - /* Fields from here on are preserved over CPU reset. */ int id; /* CPU model */ diff --git a/target/sparc/cpu.h b/target/sparc/cpu.h index a3c4f47d40..49e0349a81 100644 --- a/target/sparc/cpu.h +++ b/target/sparc/cpu.h @@ -446,8 +446,6 @@ struct CPUSPARCState { /* Fields up to this point are cleared by a CPU reset */ struct {} end_reset_fields; - CPU_COMMON - /* Fields from here on are preserved across CPU reset. */ target_ulong version; uint32_t nwindows; diff --git a/target/tilegx/cpu.h b/target/tilegx/cpu.h index deb3e836ea..c2acb43c2b 100644 --- a/target/tilegx/cpu.h +++ b/target/tilegx/cpu.h @@ -93,8 +93,6 @@ typedef struct CPUTLGState { /* Fields up to this point are cleared by a CPU reset */ struct {} end_reset_fields; - - CPU_COMMON } CPUTLGState; #include "qom/cpu.h" diff --git a/target/tricore/cpu.h b/target/tricore/cpu.h index 03b293c1f6..52b07c73bf 100644 --- a/target/tricore/cpu.h +++ b/target/tricore/cpu.h @@ -184,8 +184,6 @@ struct CPUTriCoreState { int error_code; uint32_t hflags; /* CPU State */ - CPU_COMMON - /* Internal CPU feature flags. */ uint64_t features; diff --git a/target/unicore32/cpu.h b/target/unicore32/cpu.h index 39beb32366..6b459dacde 100644 --- a/target/unicore32/cpu.h +++ b/target/unicore32/cpu.h @@ -55,8 +55,6 @@ typedef struct CPUUniCore32State { float_status fp_status; } ucf64; - CPU_COMMON - /* Internal CPU feature flags. */ uint32_t features; diff --git a/target/xtensa/cpu.h b/target/xtensa/cpu.h index e2d7e8371d..bfc6604b76 100644 --- a/target/xtensa/cpu.h +++ b/target/xtensa/cpu.h @@ -541,8 +541,6 @@ typedef struct CPUXtensaState { /* Watchpoints for DBREAK registers */ struct CPUWatchpoint *cpu_watchpoint[MAX_NDBREAK]; - - CPU_COMMON } CPUXtensaState; /** -- cgit 1.4.1