From 93afeade09680c657e109bf192dbf70233e4ebbe Mon Sep 17 00:00:00 2001 From: Andreas Färber Date: Mon, 26 Aug 2013 03:41:01 +0200 Subject: cpu: Move mem_io_{pc,vaddr} fields from CPU_COMMON to CPUState MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Reset them. Signed-off-by: Andreas Färber --- include/exec/cpu-defs.h | 7 ------- include/exec/softmmu_template.h | 8 ++++---- 2 files changed, 4 insertions(+), 11 deletions(-) (limited to 'include/exec') diff --git a/include/exec/cpu-defs.h b/include/exec/cpu-defs.h index 66a3d46938..bdcfefb3fb 100644 --- a/include/exec/cpu-defs.h +++ b/include/exec/cpu-defs.h @@ -146,13 +146,6 @@ typedef struct CPUWatchpoint { #define CPU_TEMP_BUF_NLONGS 128 #define CPU_COMMON \ /* soft mmu support */ \ - /* in order to avoid passing too many arguments to the MMIO \ - helpers, we store some rarely used information in the CPU \ - context) */ \ - uintptr_t mem_io_pc; /* host pc at which the memory was \ - accessed */ \ - target_ulong mem_io_vaddr; /* target virtual addr at which the \ - memory was accessed */ \ CPU_COMMON_TLB \ struct TranslationBlock *tb_jmp_cache[TB_JMP_CACHE_SIZE]; \ \ diff --git a/include/exec/softmmu_template.h b/include/exec/softmmu_template.h index c14a04d7e9..c7cd93774d 100644 --- a/include/exec/softmmu_template.h +++ b/include/exec/softmmu_template.h @@ -126,12 +126,12 @@ static inline DATA_TYPE glue(io_read, SUFFIX)(CPUArchState *env, MemoryRegion *mr = iotlb_to_region(cpu->as, physaddr); physaddr = (physaddr & TARGET_PAGE_MASK) + addr; - env->mem_io_pc = retaddr; + cpu->mem_io_pc = retaddr; if (mr != &io_mem_rom && mr != &io_mem_notdirty && !can_do_io(env)) { cpu_io_recompile(env, retaddr); } - env->mem_io_vaddr = addr; + cpu->mem_io_vaddr = addr; io_mem_read(mr, physaddr, &val, 1 << SHIFT); return val; } @@ -337,8 +337,8 @@ static inline void glue(io_write, SUFFIX)(CPUArchState *env, cpu_io_recompile(env, retaddr); } - env->mem_io_vaddr = addr; - env->mem_io_pc = retaddr; + cpu->mem_io_vaddr = addr; + cpu->mem_io_pc = retaddr; io_mem_write(mr, physaddr, val, 1 << SHIFT); } -- cgit 1.4.1 From 99df7dce8ae81e4a42dac98094ccca3a32dcf8f8 Mon Sep 17 00:00:00 2001 From: Andreas Färber Date: Mon, 26 Aug 2013 05:15:23 +0200 Subject: cpu: Move can_do_io field from CPU_COMMON to CPUState MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Rename can_do_io() to cpu_can_do_io() and change argument to CPUState. Signed-off-by: Andreas Färber --- cpus.c | 2 +- include/exec/cpu-defs.h | 1 - include/exec/exec-all.h | 21 +++++++++++++-------- include/exec/gen-icount.h | 4 ++-- include/exec/softmmu_template.h | 4 ++-- include/qom/cpu.h | 2 ++ qom/cpu.c | 1 + translate-all.c | 5 +++-- 8 files changed, 24 insertions(+), 16 deletions(-) (limited to 'include/exec') diff --git a/cpus.c b/cpus.c index eda6d02bcc..05016dc9c7 100644 --- a/cpus.c +++ b/cpus.c @@ -140,7 +140,7 @@ static int64_t cpu_get_icount_locked(void) icount = qemu_icount; if (cpu) { CPUArchState *env = cpu->env_ptr; - if (!can_do_io(env)) { + if (!cpu_can_do_io(cpu)) { fprintf(stderr, "Bad clock read\n"); } icount -= (env->icount_decr.u16.low + env->icount_extra); diff --git a/include/exec/cpu-defs.h b/include/exec/cpu-defs.h index bdcfefb3fb..068b6c168f 100644 --- a/include/exec/cpu-defs.h +++ b/include/exec/cpu-defs.h @@ -157,7 +157,6 @@ typedef struct CPUWatchpoint { uint32_t u32; \ icount_decr_u16 u16; \ } icount_decr; \ - uint32_t can_do_io; /* nonzero if memory mapped IO is safe. */ \ \ /* from this point: preserved by CPU reset */ \ /* ice debug support */ \ diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index a387922df4..2179329916 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -380,20 +380,25 @@ extern int singlestep; /* cpu-exec.c */ extern volatile sig_atomic_t exit_request; -/* Deterministic execution requires that IO only be performed on the last - instruction of a TB so that interrupts take effect immediately. */ -static inline int can_do_io(CPUArchState *env) +/** + * cpu_can_do_io: + * @cpu: The CPU for which to check IO. + * + * Deterministic execution requires that IO only be performed on the last + * instruction of a TB so that interrupts take effect immediately. + * + * Returns: %true if memory-mapped IO is safe, %false otherwise. + */ +static inline bool cpu_can_do_io(CPUState *cpu) { - CPUState *cpu = ENV_GET_CPU(env); - if (!use_icount) { - return 1; + return true; } /* If not executing code then assume we are ok. */ if (cpu->current_tb == NULL) { - return 1; + return true; } - return env->can_do_io != 0; + return cpu->can_do_io != 0; } #endif diff --git a/include/exec/gen-icount.h b/include/exec/gen-icount.h index 39a6b61e4f..f0dace3034 100644 --- a/include/exec/gen-icount.h +++ b/include/exec/gen-icount.h @@ -51,14 +51,14 @@ static void gen_tb_end(TranslationBlock *tb, int num_insns) static inline void gen_io_start(void) { TCGv_i32 tmp = tcg_const_i32(1); - tcg_gen_st_i32(tmp, cpu_env, offsetof(CPUArchState, can_do_io)); + tcg_gen_st_i32(tmp, cpu_env, -ENV_OFFSET + offsetof(CPUState, can_do_io)); tcg_temp_free_i32(tmp); } static inline void gen_io_end(void) { TCGv_i32 tmp = tcg_const_i32(0); - tcg_gen_st_i32(tmp, cpu_env, offsetof(CPUArchState, can_do_io)); + tcg_gen_st_i32(tmp, cpu_env, -ENV_OFFSET + offsetof(CPUState, can_do_io)); tcg_temp_free_i32(tmp); } diff --git a/include/exec/softmmu_template.h b/include/exec/softmmu_template.h index c7cd93774d..ac825d251c 100644 --- a/include/exec/softmmu_template.h +++ b/include/exec/softmmu_template.h @@ -127,7 +127,7 @@ static inline DATA_TYPE glue(io_read, SUFFIX)(CPUArchState *env, physaddr = (physaddr & TARGET_PAGE_MASK) + addr; cpu->mem_io_pc = retaddr; - if (mr != &io_mem_rom && mr != &io_mem_notdirty && !can_do_io(env)) { + if (mr != &io_mem_rom && mr != &io_mem_notdirty && !cpu_can_do_io(cpu)) { cpu_io_recompile(env, retaddr); } @@ -333,7 +333,7 @@ static inline void glue(io_write, SUFFIX)(CPUArchState *env, MemoryRegion *mr = iotlb_to_region(cpu->as, physaddr); physaddr = (physaddr & TARGET_PAGE_MASK) + addr; - if (mr != &io_mem_rom && mr != &io_mem_notdirty && !can_do_io(env)) { + if (mr != &io_mem_rom && mr != &io_mem_notdirty && !cpu_can_do_io(cpu)) { cpu_io_recompile(env, retaddr); } diff --git a/include/qom/cpu.h b/include/qom/cpu.h index 9d52cf3a34..f80036e99b 100644 --- a/include/qom/cpu.h +++ b/include/qom/cpu.h @@ -157,6 +157,7 @@ struct kvm_run; * @tcg_exit_req: Set to force TCG to stop executing linked TBs for this * CPU and return to its top level loop. * @singlestep_enabled: Flags for single-stepping. + * @can_do_io: Nonzero if memory-mapped IO is safe. * @env_ptr: Pointer to subclass-specific CPUArchState field. * @current_tb: Currently executing TB. * @gdb_regs: Additional GDB registers. @@ -220,6 +221,7 @@ struct CPUState { /* TODO Move common fields from CPUArchState here. */ int cpu_index; /* used by alpha TCG */ uint32_t halted; /* used by alpha, cris, ppc TCG */ + uint32_t can_do_io; }; QTAILQ_HEAD(CPUTailQ, CPUState); diff --git a/qom/cpu.c b/qom/cpu.c index 4d60c03182..e7d59997ee 100644 --- a/qom/cpu.c +++ b/qom/cpu.c @@ -241,6 +241,7 @@ static void cpu_common_reset(CPUState *cpu) cpu->halted = 0; cpu->mem_io_pc = 0; cpu->mem_io_vaddr = 0; + cpu->can_do_io = 0; } static bool cpu_common_has_work(CPUState *cs) diff --git a/translate-all.c b/translate-all.c index dc35caab8e..a1af5ef393 100644 --- a/translate-all.c +++ b/translate-all.c @@ -200,6 +200,7 @@ int cpu_gen_code(CPUArchState *env, TranslationBlock *tb, int *gen_code_size_ptr static int cpu_restore_state_from_tb(TranslationBlock *tb, CPUArchState *env, uintptr_t searched_pc) { + CPUState *cpu = ENV_GET_CPU(env); TCGContext *s = &tcg_ctx; int j; uintptr_t tc_ptr; @@ -218,7 +219,7 @@ static int cpu_restore_state_from_tb(TranslationBlock *tb, CPUArchState *env, /* Reset the cycle counter to the start of the block. */ env->icount_decr.u16.low += tb->icount; /* Clear the IO flag. */ - env->can_do_io = 0; + cpu->can_do_io = 0; } /* find opc index corresponding to search_pc */ @@ -1409,7 +1410,7 @@ static void tcg_handle_interrupt(CPUState *cpu, int mask) if (use_icount) { env->icount_decr.u16.high = 0xffff; - if (!can_do_io(env) + if (!cpu_can_do_io(cpu) && (mask & ~old_mask) != 0) { cpu_abort(env, "Raised interrupt while not in I/O function"); } -- cgit 1.4.1 From efee734004c42ba185098086e5185d8a85ed02af Mon Sep 17 00:00:00 2001 From: Andreas Färber Date: Mon, 26 Aug 2013 05:39:29 +0200 Subject: cpu: Move icount_extra field from CPU_COMMON to CPUState MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Reset it. Signed-off-by: Andreas Färber --- cpu-exec.c | 10 +++++----- cpus.c | 14 +++++++------- include/exec/cpu-defs.h | 1 - include/qom/cpu.h | 2 ++ qom/cpu.c | 1 + 5 files changed, 15 insertions(+), 13 deletions(-) (limited to 'include/exec') diff --git a/cpu-exec.c b/cpu-exec.c index 6559d5e922..4a03d83cba 100644 --- a/cpu-exec.c +++ b/cpu-exec.c @@ -650,15 +650,15 @@ int cpu_exec(CPUArchState *env) int insns_left; tb = (TranslationBlock *)(next_tb & ~TB_EXIT_MASK); insns_left = env->icount_decr.u32; - if (env->icount_extra && insns_left >= 0) { + if (cpu->icount_extra && insns_left >= 0) { /* Refill decrementer and continue execution. */ - env->icount_extra += insns_left; - if (env->icount_extra > 0xffff) { + cpu->icount_extra += insns_left; + if (cpu->icount_extra > 0xffff) { insns_left = 0xffff; } else { - insns_left = env->icount_extra; + insns_left = cpu->icount_extra; } - env->icount_extra -= insns_left; + cpu->icount_extra -= insns_left; env->icount_decr.u16.low = insns_left; } else { if (insns_left > 0) { diff --git a/cpus.c b/cpus.c index 05016dc9c7..e9c17ae942 100644 --- a/cpus.c +++ b/cpus.c @@ -143,7 +143,7 @@ static int64_t cpu_get_icount_locked(void) if (!cpu_can_do_io(cpu)) { fprintf(stderr, "Bad clock read\n"); } - icount -= (env->icount_decr.u16.low + env->icount_extra); + icount -= (env->icount_decr.u16.low + cpu->icount_extra); } return qemu_icount_bias + (icount << icount_time_shift); } @@ -1236,6 +1236,7 @@ int vm_stop_force_state(RunState state) static int tcg_cpu_exec(CPUArchState *env) { + CPUState *cpu = ENV_GET_CPU(env); int ret; #ifdef CONFIG_PROFILER int64_t ti; @@ -1248,9 +1249,9 @@ static int tcg_cpu_exec(CPUArchState *env) int64_t count; int64_t deadline; int decr; - qemu_icount -= (env->icount_decr.u16.low + env->icount_extra); + qemu_icount -= (env->icount_decr.u16.low + cpu->icount_extra); env->icount_decr.u16.low = 0; - env->icount_extra = 0; + cpu->icount_extra = 0; deadline = qemu_clock_deadline_ns_all(QEMU_CLOCK_VIRTUAL); /* Maintain prior (possibly buggy) behaviour where if no deadline @@ -1267,7 +1268,7 @@ static int tcg_cpu_exec(CPUArchState *env) decr = (count > 0xffff) ? 0xffff : count; count -= decr; env->icount_decr.u16.low = decr; - env->icount_extra = count; + cpu->icount_extra = count; } ret = cpu_exec(env); #ifdef CONFIG_PROFILER @@ -1276,10 +1277,9 @@ static int tcg_cpu_exec(CPUArchState *env) if (use_icount) { /* Fold pending instructions back into the instruction counter, and clear the interrupt flag. */ - qemu_icount -= (env->icount_decr.u16.low - + env->icount_extra); + qemu_icount -= (env->icount_decr.u16.low + cpu->icount_extra); env->icount_decr.u32 = 0; - env->icount_extra = 0; + cpu->icount_extra = 0; } return ret; } diff --git a/include/exec/cpu-defs.h b/include/exec/cpu-defs.h index 068b6c168f..8f9871c40e 100644 --- a/include/exec/cpu-defs.h +++ b/include/exec/cpu-defs.h @@ -149,7 +149,6 @@ typedef struct CPUWatchpoint { CPU_COMMON_TLB \ struct TranslationBlock *tb_jmp_cache[TB_JMP_CACHE_SIZE]; \ \ - int64_t icount_extra; /* Instructions until next timer event. */ \ /* Number of cycles left, with interrupt flag in high bit. \ This allows a single read-compare-cbranch-write sequence to test \ for both decrementer underflow and exceptions. */ \ diff --git a/include/qom/cpu.h b/include/qom/cpu.h index f80036e99b..012a7e6e79 100644 --- a/include/qom/cpu.h +++ b/include/qom/cpu.h @@ -157,6 +157,7 @@ struct kvm_run; * @tcg_exit_req: Set to force TCG to stop executing linked TBs for this * CPU and return to its top level loop. * @singlestep_enabled: Flags for single-stepping. + * @icount_extra: Instructions until next timer event. * @can_do_io: Nonzero if memory-mapped IO is safe. * @env_ptr: Pointer to subclass-specific CPUArchState field. * @current_tb: Currently executing TB. @@ -196,6 +197,7 @@ struct CPUState { volatile sig_atomic_t tcg_exit_req; uint32_t interrupt_request; int singlestep_enabled; + int64_t icount_extra; AddressSpace *as; MemoryListener *tcg_as_listener; diff --git a/qom/cpu.c b/qom/cpu.c index e7d59997ee..a4f6a784af 100644 --- a/qom/cpu.c +++ b/qom/cpu.c @@ -241,6 +241,7 @@ static void cpu_common_reset(CPUState *cpu) cpu->halted = 0; cpu->mem_io_pc = 0; cpu->mem_io_vaddr = 0; + cpu->icount_extra = 0; cpu->can_do_io = 0; } -- cgit 1.4.1 From 28ecfd7a62fafe8f4f0b35a157005f4d13913043 Mon Sep 17 00:00:00 2001 From: Andreas Färber Date: Mon, 26 Aug 2013 05:51:49 +0200 Subject: cpu: Move icount_decr field from CPU_COMMON to CPUState MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Andreas Färber --- cpu-exec.c | 4 ++-- cpus.c | 13 ++++++------- include/exec/cpu-defs.h | 20 -------------------- include/exec/gen-icount.h | 6 ++++-- include/qom/cpu.h | 19 +++++++++++++++++++ qom/cpu.c | 1 + translate-all.c | 15 ++++++++------- 7 files changed, 40 insertions(+), 38 deletions(-) (limited to 'include/exec') diff --git a/cpu-exec.c b/cpu-exec.c index 4a03d83cba..9d98f210a4 100644 --- a/cpu-exec.c +++ b/cpu-exec.c @@ -649,7 +649,7 @@ int cpu_exec(CPUArchState *env) /* Instruction counter expired. */ int insns_left; tb = (TranslationBlock *)(next_tb & ~TB_EXIT_MASK); - insns_left = env->icount_decr.u32; + insns_left = cpu->icount_decr.u32; if (cpu->icount_extra && insns_left >= 0) { /* Refill decrementer and continue execution. */ cpu->icount_extra += insns_left; @@ -659,7 +659,7 @@ int cpu_exec(CPUArchState *env) insns_left = cpu->icount_extra; } cpu->icount_extra -= insns_left; - env->icount_decr.u16.low = insns_left; + cpu->icount_decr.u16.low = insns_left; } else { if (insns_left > 0) { /* Execute remaining instructions. */ diff --git a/cpus.c b/cpus.c index e9c17ae942..1104d6175c 100644 --- a/cpus.c +++ b/cpus.c @@ -139,11 +139,10 @@ static int64_t cpu_get_icount_locked(void) icount = qemu_icount; if (cpu) { - CPUArchState *env = cpu->env_ptr; if (!cpu_can_do_io(cpu)) { fprintf(stderr, "Bad clock read\n"); } - icount -= (env->icount_decr.u16.low + cpu->icount_extra); + icount -= (cpu->icount_decr.u16.low + cpu->icount_extra); } return qemu_icount_bias + (icount << icount_time_shift); } @@ -1249,8 +1248,8 @@ static int tcg_cpu_exec(CPUArchState *env) int64_t count; int64_t deadline; int decr; - qemu_icount -= (env->icount_decr.u16.low + cpu->icount_extra); - env->icount_decr.u16.low = 0; + qemu_icount -= (cpu->icount_decr.u16.low + cpu->icount_extra); + cpu->icount_decr.u16.low = 0; cpu->icount_extra = 0; deadline = qemu_clock_deadline_ns_all(QEMU_CLOCK_VIRTUAL); @@ -1267,7 +1266,7 @@ static int tcg_cpu_exec(CPUArchState *env) qemu_icount += count; decr = (count > 0xffff) ? 0xffff : count; count -= decr; - env->icount_decr.u16.low = decr; + cpu->icount_decr.u16.low = decr; cpu->icount_extra = count; } ret = cpu_exec(env); @@ -1277,8 +1276,8 @@ static int tcg_cpu_exec(CPUArchState *env) if (use_icount) { /* Fold pending instructions back into the instruction counter, and clear the interrupt flag. */ - qemu_icount -= (env->icount_decr.u16.low + cpu->icount_extra); - env->icount_decr.u32 = 0; + qemu_icount -= (cpu->icount_decr.u16.low + cpu->icount_extra); + cpu->icount_decr.u32 = 0; cpu->icount_extra = 0; } return ret; diff --git a/include/exec/cpu-defs.h b/include/exec/cpu-defs.h index 8f9871c40e..d036e8e350 100644 --- a/include/exec/cpu-defs.h +++ b/include/exec/cpu-defs.h @@ -118,18 +118,6 @@ QEMU_BUILD_BUG_ON(sizeof(CPUTLBEntry) != (1 << CPU_TLB_ENTRY_BITS)); #endif -#ifdef HOST_WORDS_BIGENDIAN -typedef struct icount_decr_u16 { - uint16_t high; - uint16_t low; -} icount_decr_u16; -#else -typedef struct icount_decr_u16 { - uint16_t low; - uint16_t high; -} icount_decr_u16; -#endif - typedef struct CPUBreakpoint { target_ulong pc; int flags; /* BP_* */ @@ -149,14 +137,6 @@ typedef struct CPUWatchpoint { CPU_COMMON_TLB \ struct TranslationBlock *tb_jmp_cache[TB_JMP_CACHE_SIZE]; \ \ - /* Number of cycles left, with interrupt flag in high bit. \ - This allows a single read-compare-cbranch-write sequence to test \ - for both decrementer underflow and exceptions. */ \ - union { \ - uint32_t u32; \ - icount_decr_u16 u16; \ - } icount_decr; \ - \ /* from this point: preserved by CPU reset */ \ /* ice debug support */ \ QTAILQ_HEAD(breakpoints_head, CPUBreakpoint) breakpoints; \ diff --git a/include/exec/gen-icount.h b/include/exec/gen-icount.h index f0dace3034..da53395de6 100644 --- a/include/exec/gen-icount.h +++ b/include/exec/gen-icount.h @@ -26,13 +26,15 @@ static inline void gen_tb_start(void) icount_label = gen_new_label(); count = tcg_temp_local_new_i32(); - tcg_gen_ld_i32(count, cpu_env, offsetof(CPUArchState, icount_decr.u32)); + tcg_gen_ld_i32(count, cpu_env, + -ENV_OFFSET + offsetof(CPUState, icount_decr.u32)); /* This is a horrid hack to allow fixing up the value later. */ icount_arg = tcg_ctx.gen_opparam_ptr + 1; tcg_gen_subi_i32(count, count, 0xdeadbeef); tcg_gen_brcondi_i32(TCG_COND_LT, count, 0, icount_label); - tcg_gen_st16_i32(count, cpu_env, offsetof(CPUArchState, icount_decr.u16.low)); + tcg_gen_st16_i32(count, cpu_env, + -ENV_OFFSET + offsetof(CPUState, icount_decr.u16.low)); tcg_temp_free_i32(count); } diff --git a/include/qom/cpu.h b/include/qom/cpu.h index 012a7e6e79..3156b16ad1 100644 --- a/include/qom/cpu.h +++ b/include/qom/cpu.h @@ -138,6 +138,18 @@ typedef struct CPUClass { const char *gdb_core_xml_file; } CPUClass; +#ifdef HOST_WORDS_BIGENDIAN +typedef struct icount_decr_u16 { + uint16_t high; + uint16_t low; +} icount_decr_u16; +#else +typedef struct icount_decr_u16 { + uint16_t low; + uint16_t high; +} icount_decr_u16; +#endif + struct KVMState; struct kvm_run; @@ -158,6 +170,9 @@ struct kvm_run; * CPU and return to its top level loop. * @singlestep_enabled: Flags for single-stepping. * @icount_extra: Instructions until next timer event. + * @icount_decr: Number of cycles left, with interrupt flag in high bit. + * This allows a single read-compare-cbranch-write sequence to test + * for both decrementer underflow and exceptions. * @can_do_io: Nonzero if memory-mapped IO is safe. * @env_ptr: Pointer to subclass-specific CPUArchState field. * @current_tb: Currently executing TB. @@ -223,6 +238,10 @@ struct CPUState { /* TODO Move common fields from CPUArchState here. */ int cpu_index; /* used by alpha TCG */ uint32_t halted; /* used by alpha, cris, ppc TCG */ + union { + uint32_t u32; + icount_decr_u16 u16; + } icount_decr; uint32_t can_do_io; }; diff --git a/qom/cpu.c b/qom/cpu.c index a4f6a784af..a4c5073951 100644 --- a/qom/cpu.c +++ b/qom/cpu.c @@ -242,6 +242,7 @@ static void cpu_common_reset(CPUState *cpu) cpu->mem_io_pc = 0; cpu->mem_io_vaddr = 0; cpu->icount_extra = 0; + cpu->icount_decr.u32 = 0; cpu->can_do_io = 0; } diff --git a/translate-all.c b/translate-all.c index a1af5ef393..6bb3933523 100644 --- a/translate-all.c +++ b/translate-all.c @@ -217,7 +217,7 @@ static int cpu_restore_state_from_tb(TranslationBlock *tb, CPUArchState *env, if (use_icount) { /* Reset the cycle counter to the start of the block. */ - env->icount_decr.u16.low += tb->icount; + cpu->icount_decr.u16.low += tb->icount; /* Clear the IO flag. */ cpu->can_do_io = 0; } @@ -242,7 +242,7 @@ static int cpu_restore_state_from_tb(TranslationBlock *tb, CPUArchState *env, while (s->gen_opc_instr_start[j] == 0) { j--; } - env->icount_decr.u16.low -= s->gen_opc_icount[j]; + cpu->icount_decr.u16.low -= s->gen_opc_icount[j]; restore_state_to_opc(env, tb, j); @@ -1409,7 +1409,7 @@ static void tcg_handle_interrupt(CPUState *cpu, int mask) } if (use_icount) { - env->icount_decr.u16.high = 0xffff; + cpu->icount_decr.u16.high = 0xffff; if (!cpu_can_do_io(cpu) && (mask & ~old_mask) != 0) { cpu_abort(env, "Raised interrupt while not in I/O function"); @@ -1425,6 +1425,7 @@ CPUInterruptHandler cpu_interrupt_handler = tcg_handle_interrupt; must be at the end of the TB */ void cpu_io_recompile(CPUArchState *env, uintptr_t retaddr) { + CPUState *cpu = ENV_GET_CPU(env); TranslationBlock *tb; uint32_t n, cflags; target_ulong pc, cs_base; @@ -1435,11 +1436,11 @@ void cpu_io_recompile(CPUArchState *env, uintptr_t retaddr) cpu_abort(env, "cpu_io_recompile: could not find TB for pc=%p", (void *)retaddr); } - n = env->icount_decr.u16.low + tb->icount; + n = cpu->icount_decr.u16.low + tb->icount; cpu_restore_state_from_tb(tb, env, retaddr); /* Calculate how many instructions had been executed before the fault occurred. */ - n = n - env->icount_decr.u16.low; + n = n - cpu->icount_decr.u16.low; /* Generate a new TB ending on the I/O insn. */ n++; /* On MIPS and SH, delay slot instructions can only be restarted if @@ -1449,14 +1450,14 @@ void cpu_io_recompile(CPUArchState *env, uintptr_t retaddr) #if defined(TARGET_MIPS) if ((env->hflags & MIPS_HFLAG_BMASK) != 0 && n > 1) { env->active_tc.PC -= 4; - env->icount_decr.u16.low++; + cpu->icount_decr.u16.low++; env->hflags &= ~MIPS_HFLAG_BMASK; } #elif defined(TARGET_SH4) if ((env->flags & ((DELAY_SLOT | DELAY_SLOT_CONDITIONAL))) != 0 && n > 1) { env->pc -= 2; - env->icount_decr.u16.low++; + cpu->icount_decr.u16.low++; env->flags &= ~(DELAY_SLOT | DELAY_SLOT_CONDITIONAL); } #endif -- cgit 1.4.1 From 8cd70437f385fc53f34481d506cf4a18ebe75976 Mon Sep 17 00:00:00 2001 From: Andreas Färber Date: Mon, 26 Aug 2013 06:03:38 +0200 Subject: cpu: Move tb_jmp_cache field from CPU_COMMON to CPUState MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Clear it on reset. Signed-off-by: Andreas Färber --- cpu-exec.c | 6 ++++-- cputlb.c | 2 +- include/exec/cpu-defs.h | 4 ---- include/qom/cpu.h | 4 ++++ qom/cpu.c | 1 + translate-all.c | 15 ++++++--------- 6 files changed, 16 insertions(+), 16 deletions(-) (limited to 'include/exec') diff --git a/cpu-exec.c b/cpu-exec.c index 9d98f210a4..dd8da531d0 100644 --- a/cpu-exec.c +++ b/cpu-exec.c @@ -118,6 +118,7 @@ static TranslationBlock *tb_find_slow(CPUArchState *env, target_ulong cs_base, uint64_t flags) { + CPUState *cpu = ENV_GET_CPU(env); TranslationBlock *tb, **ptb1; unsigned int h; tb_page_addr_t phys_pc, phys_page1; @@ -165,12 +166,13 @@ static TranslationBlock *tb_find_slow(CPUArchState *env, tcg_ctx.tb_ctx.tb_phys_hash[h] = tb; } /* we add the TB in the virtual pc hash table */ - env->tb_jmp_cache[tb_jmp_cache_hash_func(pc)] = tb; + cpu->tb_jmp_cache[tb_jmp_cache_hash_func(pc)] = tb; return tb; } static inline TranslationBlock *tb_find_fast(CPUArchState *env) { + CPUState *cpu = ENV_GET_CPU(env); TranslationBlock *tb; target_ulong cs_base, pc; int flags; @@ -179,7 +181,7 @@ static inline TranslationBlock *tb_find_fast(CPUArchState *env) always be the same before a given translated block is executed. */ cpu_get_tb_cpu_state(env, &pc, &cs_base, &flags); - tb = env->tb_jmp_cache[tb_jmp_cache_hash_func(pc)]; + tb = cpu->tb_jmp_cache[tb_jmp_cache_hash_func(pc)]; if (unlikely(!tb || tb->pc != pc || tb->cs_base != cs_base || tb->flags != flags)) { tb = tb_find_slow(env, pc, cs_base, flags); diff --git a/cputlb.c b/cputlb.c index 0fbaa39412..0eb1801cc2 100644 --- a/cputlb.c +++ b/cputlb.c @@ -58,7 +58,7 @@ void tlb_flush(CPUArchState *env, int flush_global) cpu->current_tb = NULL; memset(env->tlb_table, -1, sizeof(env->tlb_table)); - memset(env->tb_jmp_cache, 0, sizeof(env->tb_jmp_cache)); + memset(cpu->tb_jmp_cache, 0, sizeof(cpu->tb_jmp_cache)); env->tlb_flush_addr = -1; env->tlb_flush_mask = 0; diff --git a/include/exec/cpu-defs.h b/include/exec/cpu-defs.h index d036e8e350..42720948a1 100644 --- a/include/exec/cpu-defs.h +++ b/include/exec/cpu-defs.h @@ -61,9 +61,6 @@ typedef uint64_t target_ulong; #define EXCP_HALTED 0x10003 /* cpu is halted (waiting for external event) */ #define EXCP_YIELD 0x10004 /* cpu wants to yield timeslice to another */ -#define TB_JMP_CACHE_BITS 12 -#define TB_JMP_CACHE_SIZE (1 << TB_JMP_CACHE_BITS) - /* Only the bottom TB_JMP_PAGE_BITS of the jump cache hash bits vary for addresses on the same page. The top bits are the same. This allows TLB invalidation to quickly clear a subset of the hash table. */ @@ -135,7 +132,6 @@ typedef struct CPUWatchpoint { #define CPU_COMMON \ /* soft mmu support */ \ CPU_COMMON_TLB \ - struct TranslationBlock *tb_jmp_cache[TB_JMP_CACHE_SIZE]; \ \ /* from this point: preserved by CPU reset */ \ /* ice debug support */ \ diff --git a/include/qom/cpu.h b/include/qom/cpu.h index 3156b16ad1..ada8a5afbf 100644 --- a/include/qom/cpu.h +++ b/include/qom/cpu.h @@ -153,6 +153,9 @@ typedef struct icount_decr_u16 { struct KVMState; struct kvm_run; +#define TB_JMP_CACHE_BITS 12 +#define TB_JMP_CACHE_SIZE (1 << TB_JMP_CACHE_BITS) + /** * CPUState: * @cpu_index: CPU index (informative). @@ -219,6 +222,7 @@ struct CPUState { void *env_ptr; /* CPUArchState */ struct TranslationBlock *current_tb; + struct TranslationBlock *tb_jmp_cache[TB_JMP_CACHE_SIZE]; struct GDBRegisterState *gdb_regs; int gdb_num_regs; int gdb_num_g_regs; diff --git a/qom/cpu.c b/qom/cpu.c index a4c5073951..fada2d4b92 100644 --- a/qom/cpu.c +++ b/qom/cpu.c @@ -244,6 +244,7 @@ static void cpu_common_reset(CPUState *cpu) cpu->icount_extra = 0; cpu->icount_decr.u32 = 0; cpu->can_do_io = 0; + memset(cpu->tb_jmp_cache, 0, TB_JMP_CACHE_SIZE * sizeof(void *)); } static bool cpu_common_has_work(CPUState *cs) diff --git a/translate-all.c b/translate-all.c index 6bb3933523..c067011684 100644 --- a/translate-all.c +++ b/translate-all.c @@ -704,9 +704,7 @@ void tb_flush(CPUArchState *env1) tcg_ctx.tb_ctx.nb_tbs = 0; CPU_FOREACH(cpu) { - CPUArchState *env = cpu->env_ptr; - - memset(env->tb_jmp_cache, 0, sizeof(env->tb_jmp_cache)); + memset(cpu->tb_jmp_cache, 0, sizeof(cpu->tb_jmp_cache)); } memset(tcg_ctx.tb_ctx.tb_phys_hash, 0, sizeof(tcg_ctx.tb_ctx.tb_phys_hash)); @@ -857,10 +855,8 @@ void tb_phys_invalidate(TranslationBlock *tb, tb_page_addr_t page_addr) /* remove the TB from the hash list */ h = tb_jmp_cache_hash_func(tb->pc); CPU_FOREACH(cpu) { - CPUArchState *env = cpu->env_ptr; - - if (env->tb_jmp_cache[h] == tb) { - env->tb_jmp_cache[h] = NULL; + if (cpu->tb_jmp_cache[h] == tb) { + cpu->tb_jmp_cache[h] = NULL; } } @@ -1484,16 +1480,17 @@ void cpu_io_recompile(CPUArchState *env, uintptr_t retaddr) void tb_flush_jmp_cache(CPUArchState *env, target_ulong addr) { + CPUState *cpu = ENV_GET_CPU(env); unsigned int i; /* Discard jump cache entries for any tb which might potentially overlap the flushed page. */ i = tb_jmp_cache_hash_page(addr - TARGET_PAGE_SIZE); - memset(&env->tb_jmp_cache[i], 0, + memset(&cpu->tb_jmp_cache[i], 0, TB_JMP_PAGE_SIZE * sizeof(TranslationBlock *)); i = tb_jmp_cache_hash_page(addr); - memset(&env->tb_jmp_cache[i], 0, + memset(&cpu->tb_jmp_cache[i], 0, TB_JMP_PAGE_SIZE * sizeof(TranslationBlock *)); } -- cgit 1.4.1 From 6f03bef0ffc5cd75ac5ffcca0383c489ae48108c Mon Sep 17 00:00:00 2001 From: Andreas Färber Date: Mon, 26 Aug 2013 06:22:03 +0200 Subject: cpu: Move jmp_env field from CPU_COMMON to CPUState MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Andreas Färber --- cpu-exec.c | 8 +++++--- include/exec/cpu-defs.h | 2 -- include/qom/cpu.h | 2 ++ user-exec.c | 3 ++- 4 files changed, 9 insertions(+), 6 deletions(-) (limited to 'include/exec') diff --git a/cpu-exec.c b/cpu-exec.c index dd8da531d0..3e17ff534d 100644 --- a/cpu-exec.c +++ b/cpu-exec.c @@ -28,7 +28,7 @@ void cpu_loop_exit(CPUArchState *env) CPUState *cpu = ENV_GET_CPU(env); cpu->current_tb = NULL; - siglongjmp(env->jmp_env, 1); + siglongjmp(cpu->jmp_env, 1); } /* exit the current TB from a signal handler. The host registers are @@ -37,10 +37,12 @@ void cpu_loop_exit(CPUArchState *env) #if defined(CONFIG_SOFTMMU) void cpu_resume_from_signal(CPUArchState *env, void *puc) { + CPUState *cpu = ENV_GET_CPU(env); + /* XXX: restore cpu registers saved in host registers */ env->exception_index = -1; - siglongjmp(env->jmp_env, 1); + siglongjmp(cpu->jmp_env, 1); } #endif @@ -284,7 +286,7 @@ int cpu_exec(CPUArchState *env) /* prepare setjmp context for exception handling */ for(;;) { - if (sigsetjmp(env->jmp_env, 0) == 0) { + if (sigsetjmp(cpu->jmp_env, 0) == 0) { /* if an exception is pending, we execute it here */ if (env->exception_index >= 0) { if (env->exception_index >= EXCP_INTERRUPT) { diff --git a/include/exec/cpu-defs.h b/include/exec/cpu-defs.h index 42720948a1..5fbdc9c4a9 100644 --- a/include/exec/cpu-defs.h +++ b/include/exec/cpu-defs.h @@ -24,7 +24,6 @@ #endif #include "config.h" -#include #include #include "qemu/osdep.h" #include "qemu/queue.h" @@ -141,7 +140,6 @@ typedef struct CPUWatchpoint { CPUWatchpoint *watchpoint_hit; \ \ /* Core interrupt code */ \ - sigjmp_buf jmp_env; \ int exception_index; \ \ /* user data */ \ diff --git a/include/qom/cpu.h b/include/qom/cpu.h index ada8a5afbf..04bfd72326 100644 --- a/include/qom/cpu.h +++ b/include/qom/cpu.h @@ -21,6 +21,7 @@ #define QEMU_CPU_H #include +#include #include "hw/qdev-core.h" #include "exec/hwaddr.h" #include "qemu/queue.h" @@ -216,6 +217,7 @@ struct CPUState { uint32_t interrupt_request; int singlestep_enabled; int64_t icount_extra; + sigjmp_buf jmp_env; AddressSpace *as; MemoryListener *tcg_as_listener; diff --git a/user-exec.c b/user-exec.c index d850d41d45..dec636eb1e 100644 --- a/user-exec.c +++ b/user-exec.c @@ -52,6 +52,7 @@ static void exception_action(CPUArchState *env1) */ void cpu_resume_from_signal(CPUArchState *env1, void *puc) { + CPUState *cpu = ENV_GET_CPU(env1); #ifdef __linux__ struct ucontext *uc = puc; #elif defined(__OpenBSD__) @@ -71,7 +72,7 @@ void cpu_resume_from_signal(CPUArchState *env1, void *puc) #endif } env1->exception_index = -1; - siglongjmp(env1->jmp_env, 1); + siglongjmp(cpu->jmp_env, 1); } /* 'pc' is the host PC at which the exception was raised. 'address' is -- cgit 1.4.1 From 27103424c40ce71053c07d8a54ef431365fa9b7f Mon Sep 17 00:00:00 2001 From: Andreas Färber Date: Mon, 26 Aug 2013 08:31:06 +0200 Subject: cpu: Move exception_index field from CPU_COMMON to CPUState MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Andreas Färber --- cpu-exec.c | 50 +++++++++++++++++++++--------------------- exec.c | 2 +- hw/ppc/e500.c | 3 +-- hw/ppc/ppce500_spin.c | 2 +- hw/ppc/spapr_hcall.c | 2 +- hw/s390x/s390-virtio.c | 8 +++---- include/exec/cpu-defs.h | 3 --- include/qom/cpu.h | 1 + linux-user/signal.c | 7 +++--- target-alpha/helper.c | 18 ++++++++++----- target-alpha/mem_helper.c | 4 +++- target-arm/helper.c | 25 ++++++++++----------- target-arm/op_helper.c | 20 ++++++++++++----- target-cris/helper.c | 18 +++++++-------- target-cris/op_helper.c | 6 +++-- target-i386/excp_helper.c | 4 +++- target-i386/helper.c | 6 ++--- target-i386/mem_helper.c | 5 +++-- target-i386/misc_helper.c | 9 +++++--- target-i386/seg_helper.c | 8 ++++--- target-i386/svm_helper.c | 12 +++++----- target-lm32/helper.c | 12 +++++----- target-lm32/op_helper.c | 6 +++-- target-m68k/helper.c | 2 +- target-m68k/op_helper.c | 22 +++++++++---------- target-m68k/qregs.def | 1 - target-m68k/translate.c | 5 +++++ target-microblaze/helper.c | 16 ++++++-------- target-microblaze/op_helper.c | 4 +++- target-mips/helper.c | 31 ++++++++++++++------------ target-mips/op_helper.c | 9 +++++--- target-mips/translate.c | 4 +--- target-moxie/helper.c | 21 ++++++++++-------- target-openrisc/cpu.c | 2 +- target-openrisc/exception.c | 4 +++- target-openrisc/interrupt.c | 12 +++++----- target-openrisc/mmu.c | 3 ++- target-ppc/excp_helper.c | 19 +++++++++------- target-ppc/fpu_helper.c | 26 +++++++++++++++------- target-ppc/kvm.c | 2 +- target-ppc/mmu-hash32.c | 24 ++++++++++---------- target-ppc/mmu-hash64.c | 15 +++++++------ target-ppc/mmu_helper.c | 43 ++++++++++++++++++------------------ target-ppc/translate_init.c | 2 +- target-ppc/user_only_helper.c | 2 +- target-s390x/helper.c | 39 ++++++++++++++++----------------- target-s390x/mem_helper.c | 9 ++++---- target-s390x/misc_helper.c | 15 +++++++++---- target-sh4/helper.c | 51 +++++++++++++++++++++---------------------- target-sh4/op_helper.c | 4 +++- target-sparc/helper.c | 10 ++++++--- target-sparc/int32_helper.c | 8 +++---- target-sparc/int64_helper.c | 6 ++--- target-sparc/ldst_helper.c | 2 +- target-sparc/mmu_helper.c | 22 +++++++++---------- target-unicore32/op_helper.c | 4 +++- target-unicore32/softmmu.c | 8 +++---- target-xtensa/helper.c | 20 +++++++++-------- target-xtensa/op_helper.c | 4 +++- user-exec.c | 6 +++-- 60 files changed, 389 insertions(+), 319 deletions(-) (limited to 'include/exec') diff --git a/cpu-exec.c b/cpu-exec.c index 3e17ff534d..798dc084d9 100644 --- a/cpu-exec.c +++ b/cpu-exec.c @@ -41,7 +41,7 @@ void cpu_resume_from_signal(CPUArchState *env, void *puc) /* XXX: restore cpu registers saved in host registers */ - env->exception_index = -1; + cpu->exception_index = -1; siglongjmp(cpu->jmp_env, 1); } #endif @@ -282,16 +282,16 @@ int cpu_exec(CPUArchState *env) #else #error unsupported target CPU #endif - env->exception_index = -1; + cpu->exception_index = -1; /* prepare setjmp context for exception handling */ for(;;) { if (sigsetjmp(cpu->jmp_env, 0) == 0) { /* if an exception is pending, we execute it here */ - if (env->exception_index >= 0) { - if (env->exception_index >= EXCP_INTERRUPT) { + if (cpu->exception_index >= 0) { + if (cpu->exception_index >= EXCP_INTERRUPT) { /* exit request from the cpu execution loop */ - ret = env->exception_index; + ret = cpu->exception_index; if (ret == EXCP_DEBUG) { cpu_handle_debug_exception(env); } @@ -304,11 +304,11 @@ int cpu_exec(CPUArchState *env) #if defined(TARGET_I386) cc->do_interrupt(cpu); #endif - ret = env->exception_index; + ret = cpu->exception_index; break; #else cc->do_interrupt(cpu); - env->exception_index = -1; + cpu->exception_index = -1; #endif } } @@ -323,7 +323,7 @@ int cpu_exec(CPUArchState *env) } if (interrupt_request & CPU_INTERRUPT_DEBUG) { cpu->interrupt_request &= ~CPU_INTERRUPT_DEBUG; - env->exception_index = EXCP_DEBUG; + cpu->exception_index = EXCP_DEBUG; cpu_loop_exit(env); } #if defined(TARGET_ARM) || defined(TARGET_SPARC) || defined(TARGET_MIPS) || \ @@ -332,7 +332,7 @@ int cpu_exec(CPUArchState *env) if (interrupt_request & CPU_INTERRUPT_HALT) { cpu->interrupt_request &= ~CPU_INTERRUPT_HALT; cpu->halted = 1; - env->exception_index = EXCP_HLT; + cpu->exception_index = EXCP_HLT; cpu_loop_exit(env); } #endif @@ -347,7 +347,7 @@ int cpu_exec(CPUArchState *env) cpu_svm_check_intercept_param(env, SVM_EXIT_INIT, 0); do_cpu_init(x86_cpu); - env->exception_index = EXCP_HALTED; + cpu->exception_index = EXCP_HALTED; cpu_loop_exit(env); } else if (interrupt_request & CPU_INTERRUPT_SIPI) { do_cpu_sipi(x86_cpu); @@ -419,7 +419,7 @@ int cpu_exec(CPUArchState *env) #elif defined(TARGET_LM32) if ((interrupt_request & CPU_INTERRUPT_HARD) && (env->ie & IE_IE)) { - env->exception_index = EXCP_IRQ; + cpu->exception_index = EXCP_IRQ; cc->do_interrupt(cpu); next_tb = 0; } @@ -428,7 +428,7 @@ int cpu_exec(CPUArchState *env) && (env->sregs[SR_MSR] & MSR_IE) && !(env->sregs[SR_MSR] & (MSR_EIP | MSR_BIP)) && !(env->iflags & (D_FLAG | IMM_FLAG))) { - env->exception_index = EXCP_IRQ; + cpu->exception_index = EXCP_IRQ; cc->do_interrupt(cpu); next_tb = 0; } @@ -436,7 +436,7 @@ int cpu_exec(CPUArchState *env) if ((interrupt_request & CPU_INTERRUPT_HARD) && cpu_mips_hw_interrupts_pending(env)) { /* Raise it */ - env->exception_index = EXCP_EXT_INTERRUPT; + cpu->exception_index = EXCP_EXT_INTERRUPT; env->error_code = 0; cc->do_interrupt(cpu); next_tb = 0; @@ -453,7 +453,7 @@ int cpu_exec(CPUArchState *env) idx = EXCP_TICK; } if (idx >= 0) { - env->exception_index = idx; + cpu->exception_index = idx; cc->do_interrupt(cpu); next_tb = 0; } @@ -468,7 +468,7 @@ int cpu_exec(CPUArchState *env) if (((type == TT_EXTINT) && cpu_pil_allowed(env, pil)) || type != TT_EXTINT) { - env->exception_index = env->interrupt_index; + cpu->exception_index = env->interrupt_index; cc->do_interrupt(cpu); next_tb = 0; } @@ -477,7 +477,7 @@ int cpu_exec(CPUArchState *env) #elif defined(TARGET_ARM) if (interrupt_request & CPU_INTERRUPT_FIQ && !(env->daif & PSTATE_F)) { - env->exception_index = EXCP_FIQ; + cpu->exception_index = EXCP_FIQ; cc->do_interrupt(cpu); next_tb = 0; } @@ -493,14 +493,14 @@ int cpu_exec(CPUArchState *env) if (interrupt_request & CPU_INTERRUPT_HARD && ((IS_M(env) && env->regs[15] < 0xfffffff0) || !(env->daif & PSTATE_I))) { - env->exception_index = EXCP_IRQ; + cpu->exception_index = EXCP_IRQ; cc->do_interrupt(cpu); next_tb = 0; } #elif defined(TARGET_UNICORE32) if (interrupt_request & CPU_INTERRUPT_HARD && !(env->uncached_asr & ASR_I)) { - env->exception_index = UC32_EXCP_INTR; + cpu->exception_index = UC32_EXCP_INTR; cc->do_interrupt(cpu); next_tb = 0; } @@ -535,7 +535,7 @@ int cpu_exec(CPUArchState *env) } } if (idx >= 0) { - env->exception_index = idx; + cpu->exception_index = idx; env->error_code = 0; cc->do_interrupt(cpu); next_tb = 0; @@ -545,7 +545,7 @@ int cpu_exec(CPUArchState *env) if (interrupt_request & CPU_INTERRUPT_HARD && (env->pregs[PR_CCS] & I_FLAG) && !env->locked_irq) { - env->exception_index = EXCP_IRQ; + cpu->exception_index = EXCP_IRQ; cc->do_interrupt(cpu); next_tb = 0; } @@ -557,7 +557,7 @@ int cpu_exec(CPUArchState *env) m_flag_archval = M_FLAG_V32; } if ((env->pregs[PR_CCS] & m_flag_archval)) { - env->exception_index = EXCP_NMI; + cpu->exception_index = EXCP_NMI; cc->do_interrupt(cpu); next_tb = 0; } @@ -571,7 +571,7 @@ int cpu_exec(CPUArchState *env) hardware doesn't rely on this, so we provide/save the vector when the interrupt is first signalled. */ - env->exception_index = env->pending_vector; + cpu->exception_index = env->pending_vector; do_interrupt_m68k_hardirq(env); next_tb = 0; } @@ -583,7 +583,7 @@ int cpu_exec(CPUArchState *env) } #elif defined(TARGET_XTENSA) if (interrupt_request & CPU_INTERRUPT_HARD) { - env->exception_index = EXC_IRQ; + cpu->exception_index = EXC_IRQ; cc->do_interrupt(cpu); next_tb = 0; } @@ -599,7 +599,7 @@ int cpu_exec(CPUArchState *env) } if (unlikely(cpu->exit_request)) { cpu->exit_request = 0; - env->exception_index = EXCP_INTERRUPT; + cpu->exception_index = EXCP_INTERRUPT; cpu_loop_exit(env); } spin_lock(&tcg_ctx.tb_ctx.tb_lock); @@ -669,7 +669,7 @@ int cpu_exec(CPUArchState *env) /* Execute remaining instructions. */ cpu_exec_nocache(env, insns_left, tb); } - env->exception_index = EXCP_INTERRUPT; + cpu->exception_index = EXCP_INTERRUPT; next_tb = 0; cpu_loop_exit(env); } diff --git a/exec.c b/exec.c index 6666f6d396..26ed9ccd0c 100644 --- a/exec.c +++ b/exec.c @@ -1595,7 +1595,7 @@ static void check_watchpoint(int offset, int len_mask, int flags) env->watchpoint_hit = wp; tb_check_watchpoint(env); if (wp->flags & BP_STOP_BEFORE_ACCESS) { - env->exception_index = EXCP_DEBUG; + cpu->exception_index = EXCP_DEBUG; cpu_loop_exit(env); } else { cpu_get_tb_cpu_state(env, &pc, &cs_base, &cpu_flags); diff --git a/hw/ppc/e500.c b/hw/ppc/e500.c index 8a08752613..d7ba25f379 100644 --- a/hw/ppc/e500.c +++ b/hw/ppc/e500.c @@ -472,14 +472,13 @@ static void ppce500_cpu_reset_sec(void *opaque) { PowerPCCPU *cpu = opaque; CPUState *cs = CPU(cpu); - CPUPPCState *env = &cpu->env; cpu_reset(cs); /* Secondary CPU starts in halted state for now. Needs to change when implementing non-kernel boot. */ cs->halted = 1; - env->exception_index = EXCP_HLT; + cs->exception_index = EXCP_HLT; } static void ppce500_cpu_reset(void *opaque) diff --git a/hw/ppc/ppce500_spin.c b/hw/ppc/ppce500_spin.c index 78b23fa597..f9fdc8c548 100644 --- a/hw/ppc/ppce500_spin.c +++ b/hw/ppc/ppce500_spin.c @@ -117,7 +117,7 @@ static void spin_kick(void *data) mmubooke_create_initial_mapping(env, 0, map_start, map_size); cpu->halted = 0; - env->exception_index = -1; + cpu->exception_index = -1; cpu->stopped = false; qemu_cpu_kick(cpu); } diff --git a/hw/ppc/spapr_hcall.c b/hw/ppc/spapr_hcall.c index 1de82f831c..e999bbaea0 100644 --- a/hw/ppc/spapr_hcall.c +++ b/hw/ppc/spapr_hcall.c @@ -529,7 +529,7 @@ static target_ulong h_cede(PowerPCCPU *cpu, sPAPREnvironment *spapr, hreg_compute_hflags(env); if (!cpu_has_work(cs)) { cs->halted = 1; - env->exception_index = EXCP_HLT; + cs->exception_index = EXCP_HLT; cs->exit_request = 1; } return H_SUCCESS; diff --git a/hw/s390x/s390-virtio.c b/hw/s390x/s390-virtio.c index 0f03fd18b9..aef200310c 100644 --- a/hw/s390x/s390-virtio.c +++ b/hw/s390x/s390-virtio.c @@ -135,25 +135,23 @@ static unsigned s390_running_cpus; void s390_add_running_cpu(S390CPU *cpu) { CPUState *cs = CPU(cpu); - CPUS390XState *env = &cpu->env; if (cs->halted) { s390_running_cpus++; cs->halted = 0; - env->exception_index = -1; + cs->exception_index = -1; } } unsigned s390_del_running_cpu(S390CPU *cpu) { CPUState *cs = CPU(cpu); - CPUS390XState *env = &cpu->env; if (cs->halted == 0) { assert(s390_running_cpus >= 1); s390_running_cpus--; cs->halted = 1; - env->exception_index = EXCP_HLT; + cs->exception_index = EXCP_HLT; } return s390_running_cpus; } @@ -196,7 +194,7 @@ void s390_init_cpus(const char *cpu_model, uint8_t *storage_keys) ipi_states[i] = cpu; cs->halted = 1; - cpu->env.exception_index = EXCP_HLT; + cs->exception_index = EXCP_HLT; cpu->env.storage_keys = storage_keys; } } diff --git a/include/exec/cpu-defs.h b/include/exec/cpu-defs.h index 5fbdc9c4a9..bec06e8f99 100644 --- a/include/exec/cpu-defs.h +++ b/include/exec/cpu-defs.h @@ -139,9 +139,6 @@ typedef struct CPUWatchpoint { QTAILQ_HEAD(watchpoints_head, CPUWatchpoint) watchpoints; \ CPUWatchpoint *watchpoint_hit; \ \ - /* Core interrupt code */ \ - int exception_index; \ - \ /* user data */ \ void *opaque; \ diff --git a/include/qom/cpu.h b/include/qom/cpu.h index 04bfd72326..a385b9f71d 100644 --- a/include/qom/cpu.h +++ b/include/qom/cpu.h @@ -249,6 +249,7 @@ struct CPUState { icount_decr_u16 u16; } icount_decr; uint32_t can_do_io; + int32_t exception_index; /* used by m68k TCG */ }; QTAILQ_HEAD(CPUTailQ, CPUState); diff --git a/linux-user/signal.c b/linux-user/signal.c index c8a1da0749..acf10328ee 100644 --- a/linux-user/signal.c +++ b/linux-user/signal.c @@ -774,8 +774,9 @@ static int setup_sigcontext(struct target_sigcontext *sc, struct target_fpstate *fpstate, CPUX86State *env, abi_ulong mask, abi_ulong fpstate_addr) { - int err = 0; - uint16_t magic; + CPUState *cs = CPU(x86_env_get_cpu(env)); + int err = 0; + uint16_t magic; /* already locked in setup_frame() */ err |= __put_user(env->segs[R_GS].selector, (unsigned int *)&sc->gs); @@ -790,7 +791,7 @@ setup_sigcontext(struct target_sigcontext *sc, struct target_fpstate *fpstate, err |= __put_user(env->regs[R_EDX], &sc->edx); err |= __put_user(env->regs[R_ECX], &sc->ecx); err |= __put_user(env->regs[R_EAX], &sc->eax); - err |= __put_user(env->exception_index, &sc->trapno); + err |= __put_user(cs->exception_index, &sc->trapno); err |= __put_user(env->error_code, &sc->err); err |= __put_user(env->eip, &sc->eip); err |= __put_user(env->segs[R_CS].selector, (unsigned int *)&sc->cs); diff --git a/target-alpha/helper.c b/target-alpha/helper.c index 9c94b4382c..14f59a27a8 100644 --- a/target-alpha/helper.c +++ b/target-alpha/helper.c @@ -173,7 +173,7 @@ int alpha_cpu_handle_mmu_fault(CPUState *cs, vaddr address, { AlphaCPU *cpu = ALPHA_CPU(cs); - cpu->env.exception_index = EXCP_MMFAULT; + cs->exception_index = EXCP_MMFAULT; cpu->env.trap_arg0 = address; return 1; } @@ -338,7 +338,7 @@ int alpha_cpu_handle_mmu_fault(CPUState *cs, vaddr addr, int rw, fail = get_physical_address(env, addr, 1 << rw, mmu_idx, &phys, &prot); if (unlikely(fail >= 0)) { - env->exception_index = EXCP_MMFAULT; + cs->exception_index = EXCP_MMFAULT; env->trap_arg0 = addr; env->trap_arg1 = fail; env->trap_arg2 = (rw == 2 ? -1 : rw); @@ -355,7 +355,7 @@ void alpha_cpu_do_interrupt(CPUState *cs) { AlphaCPU *cpu = ALPHA_CPU(cs); CPUAlphaState *env = &cpu->env; - int i = env->exception_index; + int i = cs->exception_index; if (qemu_loglevel_mask(CPU_LOG_INT)) { static int count; @@ -406,7 +406,7 @@ void alpha_cpu_do_interrupt(CPUState *cs) ++count, name, env->error_code, env->pc, env->ir[IR_SP]); } - env->exception_index = -1; + cs->exception_index = -1; #if !defined(CONFIG_USER_ONLY) switch (i) { @@ -508,7 +508,10 @@ void alpha_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf, We expect that ENV->PC has already been updated. */ void QEMU_NORETURN helper_excp(CPUAlphaState *env, int excp, int error) { - env->exception_index = excp; + AlphaCPU *cpu = alpha_env_get_cpu(env); + CPUState *cs = CPU(cpu); + + cs->exception_index = excp; env->error_code = error; cpu_loop_exit(env); } @@ -517,7 +520,10 @@ void QEMU_NORETURN helper_excp(CPUAlphaState *env, int excp, int error) void QEMU_NORETURN dynamic_excp(CPUAlphaState *env, uintptr_t retaddr, int excp, int error) { - env->exception_index = excp; + AlphaCPU *cpu = alpha_env_get_cpu(env); + CPUState *cs = CPU(cpu); + + cs->exception_index = excp; env->error_code = error; if (retaddr) { cpu_restore_state(env, retaddr); diff --git a/target-alpha/mem_helper.c b/target-alpha/mem_helper.c index d195935a96..23878bad80 100644 --- a/target-alpha/mem_helper.c +++ b/target-alpha/mem_helper.c @@ -99,6 +99,8 @@ uint64_t helper_stq_c_phys(CPUAlphaState *env, uint64_t p, uint64_t v) static void do_unaligned_access(CPUAlphaState *env, target_ulong addr, int is_write, int is_user, uintptr_t retaddr) { + AlphaCPU *cpu = alpha_env_get_cpu(env); + CPUState *cs = CPU(cpu); uint64_t pc; uint32_t insn; @@ -112,7 +114,7 @@ static void do_unaligned_access(CPUAlphaState *env, target_ulong addr, env->trap_arg0 = addr; env->trap_arg1 = insn >> 26; /* opcode */ env->trap_arg2 = (insn >> 21) & 31; /* dest regno */ - env->exception_index = EXCP_UNALIGN; + cs->exception_index = EXCP_UNALIGN; env->error_code = 0; cpu_loop_exit(env); } diff --git a/target-arm/helper.c b/target-arm/helper.c index d3e68a6e24..0d173ebfcf 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -2649,10 +2649,7 @@ uint32_t HELPER(rbit)(uint32_t x) void arm_cpu_do_interrupt(CPUState *cs) { - ARMCPU *cpu = ARM_CPU(cs); - CPUARMState *env = &cpu->env; - - env->exception_index = -1; + cs->exception_index = -1; } int arm_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw, @@ -2662,10 +2659,10 @@ int arm_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw, CPUARMState *env = &cpu->env; if (rw == 2) { - env->exception_index = EXCP_PREFETCH_ABORT; + cs->exception_index = EXCP_PREFETCH_ABORT; env->cp15.c6_insn = address; } else { - env->exception_index = EXCP_DATA_ABORT; + cs->exception_index = EXCP_DATA_ABORT; env->cp15.c6_data = address; } return 1; @@ -2851,7 +2848,7 @@ void arm_v7m_cpu_do_interrupt(CPUState *cs) uint32_t lr; uint32_t addr; - arm_log_exception(env->exception_index); + arm_log_exception(cs->exception_index); lr = 0xfffffff1; if (env->v7m.current_sp) @@ -2863,7 +2860,7 @@ void arm_v7m_cpu_do_interrupt(CPUState *cs) handle it. */ /* TODO: Need to escalate if the current priority is higher than the one we're raising. */ - switch (env->exception_index) { + switch (cs->exception_index) { case EXCP_UDEF: armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE); return; @@ -2895,7 +2892,7 @@ void arm_v7m_cpu_do_interrupt(CPUState *cs) do_v7m_exception_exit(env); return; default: - cpu_abort(env, "Unhandled exception 0x%x\n", env->exception_index); + cpu_abort(env, "Unhandled exception 0x%x\n", cs->exception_index); return; /* Never happens. Keep compiler happy. */ } @@ -2936,10 +2933,10 @@ void arm_cpu_do_interrupt(CPUState *cs) assert(!IS_M(env)); - arm_log_exception(env->exception_index); + arm_log_exception(cs->exception_index); /* TODO: Vectored interrupt controller. */ - switch (env->exception_index) { + switch (cs->exception_index) { case EXCP_UDEF: new_mode = ARM_CPU_MODE_UND; addr = 0x04; @@ -3020,7 +3017,7 @@ void arm_cpu_do_interrupt(CPUState *cs) offset = 4; break; default: - cpu_abort(env, "Unhandled exception 0x%x\n", env->exception_index); + cpu_abort(env, "Unhandled exception 0x%x\n", cs->exception_index); return; /* Never happens. Keep compiler happy. */ } /* High vectors. */ @@ -3650,13 +3647,13 @@ int arm_cpu_handle_mmu_fault(CPUState *cs, vaddr address, if (access_type == 2) { env->cp15.c5_insn = ret; env->cp15.c6_insn = address; - env->exception_index = EXCP_PREFETCH_ABORT; + cs->exception_index = EXCP_PREFETCH_ABORT; } else { env->cp15.c5_data = ret; if (access_type == 1 && arm_feature(env, ARM_FEATURE_V6)) env->cp15.c5_data |= (1 << 11); env->cp15.c6_data = address; - env->exception_index = EXCP_DATA_ABORT; + cs->exception_index = EXCP_DATA_ABORT; } return 1; } diff --git a/target-arm/op_helper.c b/target-arm/op_helper.c index ced6a7b83c..931536ea4f 100644 --- a/target-arm/op_helper.c +++ b/target-arm/op_helper.c @@ -24,7 +24,10 @@ static void raise_exception(CPUARMState *env, int tt) { - env->exception_index = tt; + ARMCPU *cpu = arm_env_get_cpu(env); + CPUState *cs = CPU(cpu); + + cs->exception_index = tt; cpu_loop_exit(env); } @@ -75,15 +78,16 @@ void tlb_fill(CPUARMState *env, target_ulong addr, int is_write, int mmu_idx, uintptr_t retaddr) { ARMCPU *cpu = arm_env_get_cpu(env); + CPUState *cs = CPU(cpu); int ret; - ret = arm_cpu_handle_mmu_fault(CPU(cpu), addr, is_write, mmu_idx); + ret = arm_cpu_handle_mmu_fault(cs, addr, is_write, mmu_idx); if (unlikely(ret)) { if (retaddr) { /* now we have a real cpu fault */ cpu_restore_state(env, retaddr); } - raise_exception(env, env->exception_index); + raise_exception(env, cs->exception_index); } } #endif @@ -221,23 +225,27 @@ void HELPER(wfi)(CPUARMState *env) { CPUState *cs = CPU(arm_env_get_cpu(env)); - env->exception_index = EXCP_HLT; + cs->exception_index = EXCP_HLT; cs->halted = 1; cpu_loop_exit(env); } void HELPER(wfe)(CPUARMState *env) { + CPUState *cs = CPU(arm_env_get_cpu(env)); + /* Don't actually halt the CPU, just yield back to top * level loop */ - env->exception_index = EXCP_YIELD; + cs->exception_index = EXCP_YIELD; cpu_loop_exit(env); } void HELPER(exception)(CPUARMState *env, uint32_t excp) { - env->exception_index = excp; + CPUState *cs = CPU(arm_env_get_cpu(env)); + + cs->exception_index = excp; cpu_loop_exit(env); } diff --git a/target-cris/helper.c b/target-cris/helper.c index 857cc99b29..d7fdc33647 100644 --- a/target-cris/helper.c +++ b/target-cris/helper.c @@ -41,7 +41,7 @@ void cris_cpu_do_interrupt(CPUState *cs) CRISCPU *cpu = CRIS_CPU(cs); CPUCRISState *env = &cpu->env; - env->exception_index = -1; + cs->exception_index = -1; env->pregs[PR_ERP] = env->pc; } @@ -55,7 +55,7 @@ int cris_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw, { CRISCPU *cpu = CRIS_CPU(cs); - cpu->env.exception_index = 0xaa; + cs->exception_index = 0xaa; cpu->env.pregs[PR_EDA] = address; cpu_dump_state(cs, stderr, fprintf, 0); return 1; @@ -88,7 +88,7 @@ int cris_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw, miss = cris_mmu_translate(&res, env, address & TARGET_PAGE_MASK, rw, mmu_idx, 0); if (miss) { - if (env->exception_index == EXCP_BUSFAULT) { + if (cs->exception_index == EXCP_BUSFAULT) { cpu_abort(env, "CRIS: Illegal recursive bus fault." "addr=%" VADDR_PRIx " rw=%d\n", @@ -96,7 +96,7 @@ int cris_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw, } env->pregs[PR_EDA] = address; - env->exception_index = EXCP_BUSFAULT; + cs->exception_index = EXCP_BUSFAULT; env->fault_vector = res.bf_vec; r = 1; } else { @@ -125,7 +125,7 @@ void crisv10_cpu_do_interrupt(CPUState *cs) int ex_vec = -1; D_LOG("exception index=%d interrupt_req=%d\n", - env->exception_index, + cs->exception_index, cs->interrupt_request); if (env->dslot) { @@ -134,7 +134,7 @@ void crisv10_cpu_do_interrupt(CPUState *cs) } assert(!(env->pregs[PR_CCS] & PFIX_FLAG)); - switch (env->exception_index) { + switch (cs->exception_index) { case EXCP_BREAK: /* These exceptions are genereated by the core itself. ERP should point to the insn following the brk. */ @@ -187,10 +187,10 @@ void cris_cpu_do_interrupt(CPUState *cs) int ex_vec = -1; D_LOG("exception index=%d interrupt_req=%d\n", - env->exception_index, + cs->exception_index, cs->interrupt_request); - switch (env->exception_index) { + switch (cs->exception_index) { case EXCP_BREAK: /* These exceptions are genereated by the core itself. ERP should point to the insn following the brk. */ @@ -253,7 +253,7 @@ void cris_cpu_do_interrupt(CPUState *cs) /* Clear the excption_index to avoid spurios hw_aborts for recursive bus faults. */ - env->exception_index = -1; + cs->exception_index = -1; D_LOG("%s isr=%x vec=%x ccs=%x pid=%d erp=%x\n", __func__, env->pc, ex_vec, diff --git a/target-cris/op_helper.c b/target-cris/op_helper.c index 4a6215d5d6..9b20b94d9b 100644 --- a/target-cris/op_helper.c +++ b/target-cris/op_helper.c @@ -79,8 +79,10 @@ void tlb_fill(CPUCRISState *env, target_ulong addr, int is_write, int mmu_idx, void helper_raise_exception(CPUCRISState *env, uint32_t index) { - env->exception_index = index; - cpu_loop_exit(env); + CPUState *cs = CPU(cris_env_get_cpu(env)); + + cs->exception_index = index; + cpu_loop_exit(env); } void helper_tlb_flush_pid(CPUCRISState *env, uint32_t pid) diff --git a/target-i386/excp_helper.c b/target-i386/excp_helper.c index 5319aef7df..ec76eba760 100644 --- a/target-i386/excp_helper.c +++ b/target-i386/excp_helper.c @@ -94,6 +94,8 @@ static void QEMU_NORETURN raise_interrupt2(CPUX86State *env, int intno, int is_int, int error_code, int next_eip_addend) { + CPUState *cs = CPU(x86_env_get_cpu(env)); + if (!is_int) { cpu_svm_check_intercept_param(env, SVM_EXIT_EXCP_BASE + intno, error_code); @@ -102,7 +104,7 @@ static void QEMU_NORETURN raise_interrupt2(CPUX86State *env, int intno, cpu_svm_check_intercept_param(env, SVM_EXIT_SWINT, 0); } - env->exception_index = intno; + cs->exception_index = intno; env->error_code = error_code; env->exception_is_int = is_int; env->exception_next_eip = env->eip + next_eip_addend; diff --git a/target-i386/helper.c b/target-i386/helper.c index 4910e40c17..6d9bd71a3a 100644 --- a/target-i386/helper.c +++ b/target-i386/helper.c @@ -496,7 +496,7 @@ int x86_cpu_handle_mmu_fault(CPUState *cs, vaddr addr, env->cr[2] = addr; env->error_code = (is_write << PG_ERROR_W_BIT); env->error_code |= PG_ERROR_U_MASK; - env->exception_index = EXCP0E_PAGE; + cs->exception_index = EXCP0E_PAGE; return 1; } @@ -561,7 +561,7 @@ int x86_cpu_handle_mmu_fault(CPUState *cs, vaddr addr, sext = (int64_t)addr >> 47; if (sext != 0 && sext != -1) { env->error_code = 0; - env->exception_index = EXCP0D_GPF; + cs->exception_index = EXCP0D_GPF; return 1; } @@ -892,7 +892,7 @@ int x86_cpu_handle_mmu_fault(CPUState *cs, vaddr addr, env->cr[2] = addr; } env->error_code = error_code; - env->exception_index = EXCP0E_PAGE; + cs->exception_index = EXCP0E_PAGE; return 1; } diff --git a/target-i386/mem_helper.c b/target-i386/mem_helper.c index 5b25ccd605..c0d3b45552 100644 --- a/target-i386/mem_helper.c +++ b/target-i386/mem_helper.c @@ -136,15 +136,16 @@ void tlb_fill(CPUX86State *env, target_ulong addr, int is_write, int mmu_idx, uintptr_t retaddr) { X86CPU *cpu = x86_env_get_cpu(env); + CPUState *cs = CPU(cpu); int ret; - ret = x86_cpu_handle_mmu_fault(CPU(cpu), addr, is_write, mmu_idx); + ret = x86_cpu_handle_mmu_fault(cs, addr, is_write, mmu_idx); if (ret) { if (retaddr) { /* now we have a real cpu fault */ cpu_restore_state(env, retaddr); } - raise_exception_err(env, env->exception_index, env->error_code); + raise_exception_err(env, cs->exception_index, env->error_code); } } #endif diff --git a/target-i386/misc_helper.c b/target-i386/misc_helper.c index 47f6a2f7c1..582ad34ffe 100644 --- a/target-i386/misc_helper.c +++ b/target-i386/misc_helper.c @@ -568,10 +568,11 @@ void helper_rdmsr(CPUX86State *env) static void do_pause(X86CPU *cpu) { + CPUState *cs = CPU(cpu); CPUX86State *env = &cpu->env; /* Just let another CPU run. */ - env->exception_index = EXCP_INTERRUPT; + cs->exception_index = EXCP_INTERRUPT; cpu_loop_exit(env); } @@ -582,7 +583,7 @@ static void do_hlt(X86CPU *cpu) env->hflags &= ~HF_INHIBIT_IRQ_MASK; /* needed if sti is just before */ cs->halted = 1; - env->exception_index = EXCP_HLT; + cs->exception_index = EXCP_HLT; cpu_loop_exit(env); } @@ -638,6 +639,8 @@ void helper_pause(CPUX86State *env, int next_eip_addend) void helper_debug(CPUX86State *env) { - env->exception_index = EXCP_DEBUG; + CPUState *cs = CPU(x86_env_get_cpu(env)); + + cs->exception_index = EXCP_DEBUG; cpu_loop_exit(env); } diff --git a/target-i386/seg_helper.c b/target-i386/seg_helper.c index 9dda02d2f1..c8fd572d99 100644 --- a/target-i386/seg_helper.c +++ b/target-i386/seg_helper.c @@ -935,7 +935,9 @@ static void do_interrupt64(CPUX86State *env, int intno, int is_int, #if defined(CONFIG_USER_ONLY) void helper_syscall(CPUX86State *env, int next_eip_addend) { - env->exception_index = EXCP_SYSCALL; + CPUState *cs = CPU(x86_env_get_cpu(env)); + + cs->exception_index = EXCP_SYSCALL; env->exception_next_eip = env->eip + next_eip_addend; cpu_loop_exit(env); } @@ -1248,7 +1250,7 @@ void x86_cpu_do_interrupt(CPUState *cs) /* if user mode only, we simulate a fake exception which will be handled outside the cpu execution loop */ - do_interrupt_user(env, env->exception_index, + do_interrupt_user(env, cs->exception_index, env->exception_is_int, env->error_code, env->exception_next_eip); @@ -1258,7 +1260,7 @@ void x86_cpu_do_interrupt(CPUState *cs) /* simulate a real cpu exception. On i386, it can trigger new exceptions, but we do not handle double or triple faults yet. */ - do_interrupt_all(cpu, env->exception_index, + do_interrupt_all(cpu, cs->exception_index, env->exception_is_int, env->error_code, env->exception_next_eip, 0); diff --git a/target-i386/svm_helper.c b/target-i386/svm_helper.c index bc33e61672..5e0504d7f0 100644 --- a/target-i386/svm_helper.c +++ b/target-i386/svm_helper.c @@ -320,7 +320,7 @@ void helper_vmrun(CPUX86State *env, int aflag, int next_eip_addend) /* FIXME: need to implement valid_err */ switch (event_inj & SVM_EVTINJ_TYPE_MASK) { case SVM_EVTINJ_TYPE_INTR: - env->exception_index = vector; + cs->exception_index = vector; env->error_code = event_inj_err; env->exception_is_int = 0; env->exception_next_eip = -1; @@ -329,7 +329,7 @@ void helper_vmrun(CPUX86State *env, int aflag, int next_eip_addend) do_interrupt_x86_hardirq(env, vector, 1); break; case SVM_EVTINJ_TYPE_NMI: - env->exception_index = EXCP02_NMI; + cs->exception_index = EXCP02_NMI; env->error_code = event_inj_err; env->exception_is_int = 0; env->exception_next_eip = env->eip; @@ -337,7 +337,7 @@ void helper_vmrun(CPUX86State *env, int aflag, int next_eip_addend) cpu_loop_exit(env); break; case SVM_EVTINJ_TYPE_EXEPT: - env->exception_index = vector; + cs->exception_index = vector; env->error_code = event_inj_err; env->exception_is_int = 0; env->exception_next_eip = -1; @@ -345,7 +345,7 @@ void helper_vmrun(CPUX86State *env, int aflag, int next_eip_addend) cpu_loop_exit(env); break; case SVM_EVTINJ_TYPE_SOFT: - env->exception_index = vector; + cs->exception_index = vector; env->error_code = event_inj_err; env->exception_is_int = 1; env->exception_next_eip = env->eip; @@ -353,7 +353,7 @@ void helper_vmrun(CPUX86State *env, int aflag, int next_eip_addend) cpu_loop_exit(env); break; } - qemu_log_mask(CPU_LOG_TB_IN_ASM, " %#x %#x\n", env->exception_index, + qemu_log_mask(CPU_LOG_TB_IN_ASM, " %#x %#x\n", cs->exception_index, env->error_code); } } @@ -768,7 +768,7 @@ void helper_vmexit(CPUX86State *env, uint32_t exit_code, uint64_t exit_info_1) #GP fault is delivered inside the host. */ /* remove any pending exception */ - env->exception_index = -1; + cs->exception_index = -1; env->error_code = 0; env->old_exception = -1; diff --git a/target-lm32/helper.c b/target-lm32/helper.c index ce6dd45552..e5536c0ecb 100644 --- a/target-lm32/helper.c +++ b/target-lm32/helper.c @@ -147,9 +147,9 @@ void lm32_cpu_do_interrupt(CPUState *cs) CPULM32State *env = &cpu->env; qemu_log_mask(CPU_LOG_INT, - "exception at pc=%x type=%x\n", env->pc, env->exception_index); + "exception at pc=%x type=%x\n", env->pc, cs->exception_index); - switch (env->exception_index) { + switch (cs->exception_index) { case EXCP_INSN_BUS_ERROR: case EXCP_DATA_BUS_ERROR: case EXCP_DIVIDE_BY_ZERO: @@ -160,9 +160,9 @@ void lm32_cpu_do_interrupt(CPUState *cs) env->ie |= (env->ie & IE_IE) ? IE_EIE : 0; env->ie &= ~IE_IE; if (env->dc & DC_RE) { - env->pc = env->deba + (env->exception_index * 32); + env->pc = env->deba + (cs->exception_index * 32); } else { - env->pc = env->eba + (env->exception_index * 32); + env->pc = env->eba + (cs->exception_index * 32); } log_cpu_state_mask(CPU_LOG_INT, cs, 0); break; @@ -172,12 +172,12 @@ void lm32_cpu_do_interrupt(CPUState *cs) env->regs[R_BA] = env->pc; env->ie |= (env->ie & IE_IE) ? IE_BIE : 0; env->ie &= ~IE_IE; - env->pc = env->deba + (env->exception_index * 32); + env->pc = env->deba + (cs->exception_index * 32); log_cpu_state_mask(CPU_LOG_INT, cs, 0); break; default: cpu_abort(env, "unhandled exception type=%d\n", - env->exception_index); + cs->exception_index); break; } } diff --git a/target-lm32/op_helper.c b/target-lm32/op_helper.c index 774dc65cf2..3b513a7edb 100644 --- a/target-lm32/op_helper.c +++ b/target-lm32/op_helper.c @@ -25,7 +25,9 @@ void raise_exception(CPULM32State *env, int index) { - env->exception_index = index; + CPUState *cs = CPU(lm32_env_get_cpu(env)); + + cs->exception_index = index; cpu_loop_exit(env); } @@ -39,7 +41,7 @@ void HELPER(hlt)(CPULM32State *env) CPUState *cs = CPU(lm32_env_get_cpu(env)); cs->halted = 1; - env->exception_index = EXCP_HLT; + cs->exception_index = EXCP_HLT; cpu_loop_exit(env); } diff --git a/target-m68k/helper.c b/target-m68k/helper.c index 0ffb861d08..fb43b81505 100644 --- a/target-m68k/helper.c +++ b/target-m68k/helper.c @@ -282,7 +282,7 @@ int m68k_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw, { M68kCPU *cpu = M68K_CPU(cs); - cpu->env.exception_index = EXCP_ACCESS; + cs->exception_index = EXCP_ACCESS; cpu->env.mmu.ar = address; return 1; } diff --git a/target-m68k/op_helper.c b/target-m68k/op_helper.c index 539d1d6724..930d7c8d04 100644 --- a/target-m68k/op_helper.c +++ b/target-m68k/op_helper.c @@ -23,10 +23,7 @@ void m68k_cpu_do_interrupt(CPUState *cs) { - M68kCPU *cpu = M68K_CPU(cs); - CPUM68KState *env = &cpu->env; - - env->exception_index = -1; + cs->exception_index = -1; } void do_interrupt_m68k_hardirq(CPUM68KState *env) @@ -88,7 +85,7 @@ static void do_rte(CPUM68KState *env) static void do_interrupt_all(CPUM68KState *env, int is_hw) { - CPUState *cs; + CPUState *cs = CPU(m68k_env_get_cpu(env)); uint32_t sp; uint32_t fmt; uint32_t retaddr; @@ -98,7 +95,7 @@ static void do_interrupt_all(CPUM68KState *env, int is_hw) retaddr = env->pc; if (!is_hw) { - switch (env->exception_index) { + switch (cs->exception_index) { case EXCP_RTE: /* Return from an exception. */ do_rte(env); @@ -113,20 +110,19 @@ static void do_interrupt_all(CPUM68KState *env, int is_hw) do_m68k_semihosting(env, env->dregs[0]); return; } - cs = CPU(m68k_env_get_cpu(env)); cs->halted = 1; - env->exception_index = EXCP_HLT; + cs->exception_index = EXCP_HLT; cpu_loop_exit(env); return; } - if (env->exception_index >= EXCP_TRAP0 - && env->exception_index <= EXCP_TRAP15) { + if (cs->exception_index >= EXCP_TRAP0 + && cs->exception_index <= EXCP_TRAP15) { /* Move the PC after the trap instruction. */ retaddr += 2; } } - vector = env->exception_index << 2; + vector = cs->exception_index << 2; sp = env->aregs[7]; @@ -169,7 +165,9 @@ void do_interrupt_m68k_hardirq(CPUM68KState *env) static void raise_exception(CPUM68KState *env, int tt) { - env->exception_index = tt; + CPUState *cs = CPU(m68k_env_get_cpu(env)); + + cs->exception_index = tt; cpu_loop_exit(env); } diff --git a/target-m68k/qregs.def b/target-m68k/qregs.def index 4235b02764..204663e1aa 100644 --- a/target-m68k/qregs.def +++ b/target-m68k/qregs.def @@ -7,6 +7,5 @@ DEFO32(CC_SRC, cc_src) DEFO32(CC_X, cc_x) DEFO32(DIV1, div1) DEFO32(DIV2, div2) -DEFO32(EXCEPTION, exception_index) DEFO32(MACSR, macsr) DEFO32(MAC_MASK, mac_mask) diff --git a/target-m68k/translate.c b/target-m68k/translate.c index f747c13d5f..4f06443532 100644 --- a/target-m68k/translate.c +++ b/target-m68k/translate.c @@ -43,6 +43,7 @@ #undef DEFF64 static TCGv_i32 cpu_halted; +static TCGv_i32 cpu_exception_index; static TCGv_ptr cpu_env; @@ -81,6 +82,10 @@ void m68k_tcg_init(void) cpu_halted = tcg_global_mem_new_i32(TCG_AREG0, -offsetof(M68kCPU, env) + offsetof(CPUState, halted), "HALTED"); + cpu_exception_index = tcg_global_mem_new_i32(TCG_AREG0, + -offsetof(M68kCPU, env) + + offsetof(CPUState, exception_index), + "EXCEPTION"); cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env"); diff --git a/target-microblaze/helper.c b/target-microblaze/helper.c index d03f3690bb..48254154d3 100644 --- a/target-microblaze/helper.c +++ b/target-microblaze/helper.c @@ -31,7 +31,7 @@ void mb_cpu_do_interrupt(CPUState *cs) MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs); CPUMBState *env = &cpu->env; - env->exception_index = -1; + cs->exception_index = -1; env->res_addr = RES_ADDR_NONE; env->regs[14] = env->sregs[SR_PC]; } @@ -39,9 +39,7 @@ void mb_cpu_do_interrupt(CPUState *cs) int mb_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw, int mmu_idx) { - MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs); - - cpu->env.exception_index = 0xaa; + cs->exception_index = 0xaa; cpu_dump_state(cs, stderr, fprintf, 0); return 1; } @@ -99,12 +97,12 @@ int mb_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw, break; } - if (env->exception_index == EXCP_MMU) { + if (cs->exception_index == EXCP_MMU) { cpu_abort(env, "recursive faults\n"); } /* TLB miss. */ - env->exception_index = EXCP_MMU; + cs->exception_index = EXCP_MMU; } } else { /* MMU disabled or not available. */ @@ -127,7 +125,7 @@ void mb_cpu_do_interrupt(CPUState *cs) assert(!(env->iflags & (DRTI_FLAG | DRTE_FLAG | DRTB_FLAG))); /* assert(env->sregs[SR_MSR] & (MSR_EE)); Only for HW exceptions. */ env->res_addr = RES_ADDR_NONE; - switch (env->exception_index) { + switch (cs->exception_index) { case EXCP_HW_EXCP: if (!(env->pvr.regs[0] & PVR0_USE_EXC_MASK)) { qemu_log("Exception raised on system without exceptions!\n"); @@ -253,7 +251,7 @@ void mb_cpu_do_interrupt(CPUState *cs) env->sregs[SR_MSR] &= ~(MSR_VMS | MSR_UMS | MSR_VM | MSR_UM); env->sregs[SR_MSR] |= t; env->sregs[SR_MSR] |= MSR_BIP; - if (env->exception_index == EXCP_HW_BREAK) { + if (cs->exception_index == EXCP_HW_BREAK) { env->regs[16] = env->sregs[SR_PC]; env->sregs[SR_MSR] |= MSR_BIP; env->sregs[SR_PC] = cpu->base_vectors + 0x18; @@ -262,7 +260,7 @@ void mb_cpu_do_interrupt(CPUState *cs) break; default: cpu_abort(env, "unhandled exception type=%d\n", - env->exception_index); + cs->exception_index); break; } } diff --git a/target-microblaze/op_helper.c b/target-microblaze/op_helper.c index b70b2ea99c..318185a5df 100644 --- a/target-microblaze/op_helper.c +++ b/target-microblaze/op_helper.c @@ -95,7 +95,9 @@ uint32_t helper_get(uint32_t id, uint32_t ctrl) void helper_raise_exception(CPUMBState *env, uint32_t index) { - env->exception_index = index; + CPUState *cs = CPU(mb_env_get_cpu(env)); + + cs->exception_index = index; cpu_loop_exit(env); } diff --git a/target-mips/helper.c b/target-mips/helper.c index d8e9166c2c..698c3d1adb 100644 --- a/target-mips/helper.c +++ b/target-mips/helper.c @@ -204,6 +204,7 @@ static int get_physical_address (CPUMIPSState *env, hwaddr *physical, static void raise_mmu_exception(CPUMIPSState *env, target_ulong address, int rw, int tlb_error) { + CPUState *cs = CPU(mips_env_get_cpu(env)); int exception = 0, error_code = 0; switch (tlb_error) { @@ -249,7 +250,7 @@ static void raise_mmu_exception(CPUMIPSState *env, target_ulong address, ((address & 0xC00000000000ULL) >> (55 - env->SEGBITS)) | ((address & ((1ULL << env->SEGBITS) - 1) & 0xFFFFFFFFFFFFE000ULL) >> 9); #endif - env->exception_index = exception; + cs->exception_index = exception; env->error_code = error_code; } @@ -404,27 +405,29 @@ static void set_hflags_for_handler (CPUMIPSState *env) void mips_cpu_do_interrupt(CPUState *cs) { +#if !defined(CONFIG_USER_ONLY) MIPSCPU *cpu = MIPS_CPU(cs); CPUMIPSState *env = &cpu->env; -#if !defined(CONFIG_USER_ONLY) target_ulong offset; int cause = -1; const char *name; - if (qemu_log_enabled() && env->exception_index != EXCP_EXT_INTERRUPT) { - if (env->exception_index < 0 || env->exception_index > EXCP_LAST) + if (qemu_log_enabled() && cs->exception_index != EXCP_EXT_INTERRUPT) { + if (cs->exception_index < 0 || cs->exception_index > EXCP_LAST) { name = "unknown"; - else - name = excp_names[env->exception_index]; + } else { + name = excp_names[cs->exception_index]; + } qemu_log("%s enter: PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx " %s exception\n", __func__, env->active_tc.PC, env->CP0_EPC, name); } - if (env->exception_index == EXCP_EXT_INTERRUPT && - (env->hflags & MIPS_HFLAG_DM)) - env->exception_index = EXCP_DINT; + if (cs->exception_index == EXCP_EXT_INTERRUPT && + (env->hflags & MIPS_HFLAG_DM)) { + cs->exception_index = EXCP_DINT; + } offset = 0x180; - switch (env->exception_index) { + switch (cs->exception_index) { case EXCP_DSS: env->CP0_Debug |= 1 << CP0DB_DSS; /* Debug single step cannot be raised inside a delay slot and @@ -632,11 +635,11 @@ void mips_cpu_do_interrupt(CPUState *cs) env->CP0_Cause = (env->CP0_Cause & ~(0x1f << CP0Ca_EC)) | (cause << CP0Ca_EC); break; default: - qemu_log("Invalid MIPS exception %d. Exiting\n", env->exception_index); - printf("Invalid MIPS exception %d. Exiting\n", env->exception_index); + qemu_log("Invalid MIPS exception %d. Exiting\n", cs->exception_index); + printf("Invalid MIPS exception %d. Exiting\n", cs->exception_index); exit(1); } - if (qemu_log_enabled() && env->exception_index != EXCP_EXT_INTERRUPT) { + if (qemu_log_enabled() && cs->exception_index != EXCP_EXT_INTERRUPT) { qemu_log("%s: PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx " cause %d\n" " S %08x C %08x A " TARGET_FMT_lx " D " TARGET_FMT_lx "\n", __func__, env->active_tc.PC, env->CP0_EPC, cause, @@ -644,7 +647,7 @@ void mips_cpu_do_interrupt(CPUState *cs) env->CP0_DEPC); } #endif - env->exception_index = EXCP_NONE; + cs->exception_index = EXCP_NONE; } #if !defined(CONFIG_USER_ONLY) diff --git a/target-mips/op_helper.c b/target-mips/op_helper.c index a62496cc3b..5a4a656f3d 100644 --- a/target-mips/op_helper.c +++ b/target-mips/op_helper.c @@ -38,10 +38,12 @@ static inline void QEMU_NORETURN do_raise_exception_err(CPUMIPSState *env, int error_code, uintptr_t pc) { + CPUState *cs = CPU(mips_env_get_cpu(env)); + if (exception < EXCP_SC) { qemu_log("%s: %d %d\n", __func__, exception, error_code); } - env->exception_index = exception; + cs->exception_index = exception; env->error_code = error_code; if (pc) { @@ -2147,11 +2149,12 @@ void tlb_fill(CPUMIPSState *env, target_ulong addr, int is_write, int mmu_idx, uintptr_t retaddr) { MIPSCPU *cpu = mips_env_get_cpu(env); + CPUState *cs = CPU(cpu); int ret; - ret = mips_cpu_handle_mmu_fault(CPU(cpu), addr, is_write, mmu_idx); + ret = mips_cpu_handle_mmu_fault(cs, addr, is_write, mmu_idx); if (ret) { - do_raise_exception_err(env, env->exception_index, + do_raise_exception_err(env, cs->exception_index, env->error_code, retaddr); } } diff --git a/target-mips/translate.c b/target-mips/translate.c index 083f6ab283..d1c25d2b22 100644 --- a/target-mips/translate.c +++ b/target-mips/translate.c @@ -15929,10 +15929,8 @@ MIPSCPU *cpu_mips_init(const char *cpu_model) void cpu_state_reset(CPUMIPSState *env) { -#ifndef CONFIG_USER_ONLY MIPSCPU *cpu = mips_env_get_cpu(env); CPUState *cs = CPU(cpu); -#endif /* Reset registers to their default values */ env->CP0_PRid = env->cpu_model->CP0_PRid; @@ -16063,7 +16061,7 @@ void cpu_state_reset(CPUMIPSState *env) } #endif compute_hflags(env); - env->exception_index = EXCP_NONE; + cs->exception_index = EXCP_NONE; } void restore_state_to_opc(CPUMIPSState *env, TranslationBlock *tb, int pc_pos) diff --git a/target-moxie/helper.c b/target-moxie/helper.c index 8160475414..3b14f3735e 100644 --- a/target-moxie/helper.c +++ b/target-moxie/helper.c @@ -63,7 +63,9 @@ void tlb_fill(CPUMoxieState *env, target_ulong addr, int is_write, int mmu_idx, void helper_raise_exception(CPUMoxieState *env, int ex) { - env->exception_index = ex; + CPUState *cs = CPU(moxie_env_get_cpu(env)); + + cs->exception_index = ex; /* Stash the exception type. */ env->sregs[2] = ex; /* Stash the address where the exception occurred. */ @@ -98,7 +100,9 @@ uint32_t helper_udiv(CPUMoxieState *env, uint32_t a, uint32_t b) void helper_debug(CPUMoxieState *env) { - env->exception_index = EXCP_DEBUG; + CPUState *cs = CPU(moxie_env_get_cpu(env)); + + cs->exception_index = EXCP_DEBUG; cpu_loop_exit(env); } @@ -106,7 +110,9 @@ void helper_debug(CPUMoxieState *env) void moxie_cpu_do_interrupt(CPUState *cs) { - env->exception_index = -1; + CPUState *cs = CPU(moxie_env_get_cpu(env)); + + cs->exception_index = -1; } int moxie_cpu_handle_mmu_fault(CPUState *cs, vaddr address, @@ -114,7 +120,7 @@ int moxie_cpu_handle_mmu_fault(CPUState *cs, vaddr address, { MoxieCPU *cpu = MOXIE_CPU(cs); - cpu->env.exception_index = 0xaa; + cs->exception_index = 0xaa; cpu->env.debug1 = address; cpu_dump_state(cs, stderr, fprintf, 0); return 1; @@ -138,7 +144,7 @@ int moxie_cpu_handle_mmu_fault(CPUState *cs, vaddr address, if (miss) { /* handle the miss. */ phy = 0; - env->exception_index = MOXIE_EX_MMU_MISS; + cs->exception_index = MOXIE_EX_MMU_MISS; } else { phy = res.phy; r = 0; @@ -150,10 +156,7 @@ int moxie_cpu_handle_mmu_fault(CPUState *cs, vaddr address, void moxie_cpu_do_interrupt(CPUState *cs) { - MoxieCPU *cpu = MOXIE_CPU(cs); - CPUMoxieState *env = &cpu->env; - - switch (env->exception_index) { + switch (cs->exception_index) { case MOXIE_EX_BREAK: break; default: diff --git a/target-openrisc/cpu.c b/target-openrisc/cpu.c index 99e4aa7c67..b601de009c 100644 --- a/target-openrisc/cpu.c +++ b/target-openrisc/cpu.c @@ -48,7 +48,7 @@ static void openrisc_cpu_reset(CPUState *s) cpu->env.pc = 0x100; cpu->env.sr = SR_FO | SR_SM; - cpu->env.exception_index = -1; + s->exception_index = -1; cpu->env.upr = UPR_UP | UPR_DMP | UPR_IMP | UPR_PICP | UPR_TTP; cpu->env.cpucfgr = CPUCFGR_OB32S | CPUCFGR_OF32S; diff --git a/target-openrisc/exception.c b/target-openrisc/exception.c index 58e53c6c98..b96f3f8963 100644 --- a/target-openrisc/exception.c +++ b/target-openrisc/exception.c @@ -22,6 +22,8 @@ void QEMU_NORETURN raise_exception(OpenRISCCPU *cpu, uint32_t excp) { - cpu->env.exception_index = excp; + CPUState *cs = CPU(cpu); + + cs->exception_index = excp; cpu_loop_exit(&cpu->env); } diff --git a/target-openrisc/interrupt.c b/target-openrisc/interrupt.c index 2153e7ea7e..087e2f1351 100644 --- a/target-openrisc/interrupt.c +++ b/target-openrisc/interrupt.c @@ -27,9 +27,9 @@ void openrisc_cpu_do_interrupt(CPUState *cs) { +#ifndef CONFIG_USER_ONLY OpenRISCCPU *cpu = OPENRISC_CPU(cs); CPUOpenRISCState *env = &cpu->env; -#ifndef CONFIG_USER_ONLY env->epcr = env->pc; if (env->flags & D_FLAG) { @@ -37,7 +37,7 @@ void openrisc_cpu_do_interrupt(CPUState *cs) env->sr |= SR_DSX; env->epcr -= 4; } - if (env->exception_index == EXCP_SYSCALL) { + if (cs->exception_index == EXCP_SYSCALL) { env->epcr += 4; } @@ -54,12 +54,12 @@ void openrisc_cpu_do_interrupt(CPUState *cs) env->tlb->cpu_openrisc_map_address_data = &cpu_openrisc_get_phys_nommu; env->tlb->cpu_openrisc_map_address_code = &cpu_openrisc_get_phys_nommu; - if (env->exception_index > 0 && env->exception_index < EXCP_NR) { - env->pc = (env->exception_index << 8); + if (cs->exception_index > 0 && cs->exception_index < EXCP_NR) { + env->pc = (cs->exception_index << 8); } else { - cpu_abort(env, "Unhandled exception 0x%x\n", env->exception_index); + cpu_abort(env, "Unhandled exception 0x%x\n", cs->exception_index); } #endif - env->exception_index = -1; + cs->exception_index = -1; } diff --git a/target-openrisc/mmu.c b/target-openrisc/mmu.c index 1fd0a0a3fa..4222219acd 100644 --- a/target-openrisc/mmu.c +++ b/target-openrisc/mmu.c @@ -139,6 +139,7 @@ static void cpu_openrisc_raise_mmu_exception(OpenRISCCPU *cpu, target_ulong address, int rw, int tlb_error) { + CPUState *cs = CPU(cpu); int exception = 0; switch (tlb_error) { @@ -169,7 +170,7 @@ static void cpu_openrisc_raise_mmu_exception(OpenRISCCPU *cpu, #endif } - cpu->env.exception_index = exception; + cs->exception_index = exception; cpu->env.eear = address; } diff --git a/target-ppc/excp_helper.c b/target-ppc/excp_helper.c index d541929743..a58655b5c7 100644 --- a/target-ppc/excp_helper.c +++ b/target-ppc/excp_helper.c @@ -43,13 +43,15 @@ void ppc_cpu_do_interrupt(CPUState *cs) PowerPCCPU *cpu = POWERPC_CPU(cs); CPUPPCState *env = &cpu->env; - env->exception_index = POWERPC_EXCP_NONE; + cs->exception_index = POWERPC_EXCP_NONE; env->error_code = 0; } void ppc_hw_interrupt(CPUPPCState *env) { - env->exception_index = POWERPC_EXCP_NONE; + CPUState *cs = CPU(ppc_env_get_cpu(env)); + + cs->exception_index = POWERPC_EXCP_NONE; env->error_code = 0; } #else /* defined(CONFIG_USER_ONLY) */ @@ -68,8 +70,8 @@ static inline void dump_syscall(CPUPPCState *env) */ static inline void powerpc_excp(PowerPCCPU *cpu, int excp_model, int excp) { + CPUState *cs = CPU(cpu); CPUPPCState *env = &cpu->env; - CPUState *cs; target_ulong msr, new_msr, vector; int srr0, srr1, asrr0, asrr1; int lpes0, lpes1, lev; @@ -135,7 +137,6 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int excp_model, int excp) fprintf(stderr, "Machine check while not allowed. " "Entering checkstop state\n"); } - cs = CPU(cpu); cs->halted = 1; cs->interrupt_request |= CPU_INTERRUPT_EXITTB; } @@ -204,7 +205,7 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int excp_model, int excp) case POWERPC_EXCP_FP: if ((msr_fe0 == 0 && msr_fe1 == 0) || msr_fp == 0) { LOG_EXCP("Ignore floating point exception\n"); - env->exception_index = POWERPC_EXCP_NONE; + cs->exception_index = POWERPC_EXCP_NONE; env->error_code = 0; return; } @@ -662,7 +663,7 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int excp_model, int excp) hreg_compute_hflags(env); env->nip = vector; /* Reset exception state */ - env->exception_index = POWERPC_EXCP_NONE; + cs->exception_index = POWERPC_EXCP_NONE; env->error_code = 0; if ((env->mmu_model == POWERPC_MMU_BOOKE) || @@ -679,7 +680,7 @@ void ppc_cpu_do_interrupt(CPUState *cs) PowerPCCPU *cpu = POWERPC_CPU(cs); CPUPPCState *env = &cpu->env; - powerpc_excp(cpu, env->excp_model, env->exception_index); + powerpc_excp(cpu, env->excp_model, cs->exception_index); } void ppc_hw_interrupt(CPUPPCState *env) @@ -815,10 +816,12 @@ static void cpu_dump_rfi(target_ulong RA, target_ulong msr) void helper_raise_exception_err(CPUPPCState *env, uint32_t exception, uint32_t error_code) { + CPUState *cs = CPU(ppc_env_get_cpu(env)); + #if 0 printf("Raise exception %3x code : %d\n", exception, error_code); #endif - env->exception_index = exception; + cs->exception_index = exception; env->error_code = error_code; cpu_loop_exit(env); } diff --git a/target-ppc/fpu_helper.c b/target-ppc/fpu_helper.c index e7f329566d..fd91239d37 100644 --- a/target-ppc/fpu_helper.c +++ b/target-ppc/fpu_helper.c @@ -119,6 +119,7 @@ uint32_t helper_compute_fprf(CPUPPCState *env, uint64_t arg, uint32_t set_fprf) static inline uint64_t fload_invalid_op_excp(CPUPPCState *env, int op, int set_fpcc) { + CPUState *cs = CPU(ppc_env_get_cpu(env)); uint64_t ret = 0; int ve; @@ -155,7 +156,7 @@ static inline uint64_t fload_invalid_op_excp(CPUPPCState *env, int op, } /* We must update the target FPR before raising the exception */ if (ve != 0) { - env->exception_index = POWERPC_EXCP_PROGRAM; + cs->exception_index = POWERPC_EXCP_PROGRAM; env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_VXVC; /* Update the floating-point enabled exception summary */ env->fpscr |= 1 << FPSCR_FEX; @@ -224,6 +225,8 @@ static inline void float_zero_divide_excp(CPUPPCState *env) static inline void float_overflow_excp(CPUPPCState *env) { + CPUState *cs = CPU(ppc_env_get_cpu(env)); + env->fpscr |= 1 << FPSCR_OX; /* Update the floating-point exception summary */ env->fpscr |= 1 << FPSCR_FX; @@ -232,7 +235,7 @@ static inline void float_overflow_excp(CPUPPCState *env) /* Update the floating-point enabled exception summary */ env->fpscr |= 1 << FPSCR_FEX; /* We must update the target FPR before raising the exception */ - env->exception_index = POWERPC_EXCP_PROGRAM; + cs->exception_index = POWERPC_EXCP_PROGRAM; env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_OX; } else { env->fpscr |= 1 << FPSCR_XX; @@ -242,6 +245,8 @@ static inline void float_overflow_excp(CPUPPCState *env) static inline void float_underflow_excp(CPUPPCState *env) { + CPUState *cs = CPU(ppc_env_get_cpu(env)); + env->fpscr |= 1 << FPSCR_UX; /* Update the floating-point exception summary */ env->fpscr |= 1 << FPSCR_FX; @@ -250,13 +255,15 @@ static inline void float_underflow_excp(CPUPPCState *env) /* Update the floating-point enabled exception summary */ env->fpscr |= 1 << FPSCR_FEX; /* We must update the target FPR before raising the exception */ - env->exception_index = POWERPC_EXCP_PROGRAM; + cs->exception_index = POWERPC_EXCP_PROGRAM; env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_UX; } } static inline void float_inexact_excp(CPUPPCState *env) { + CPUState *cs = CPU(ppc_env_get_cpu(env)); + env->fpscr |= 1 << FPSCR_XX; /* Update the floating-point exception summary */ env->fpscr |= 1 << FPSCR_FX; @@ -264,7 +271,7 @@ static inline void float_inexact_excp(CPUPPCState *env) /* Update the floating-point enabled exception summary */ env->fpscr |= 1 << FPSCR_FEX; /* We must update the target FPR before raising the exception */ - env->exception_index = POWERPC_EXCP_PROGRAM; + cs->exception_index = POWERPC_EXCP_PROGRAM; env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_XX; } } @@ -316,6 +323,7 @@ void helper_fpscr_clrbit(CPUPPCState *env, uint32_t bit) void helper_fpscr_setbit(CPUPPCState *env, uint32_t bit) { + CPUState *cs = CPU(ppc_env_get_cpu(env)); int prev; prev = (env->fpscr >> bit) & 1; @@ -439,7 +447,7 @@ void helper_fpscr_setbit(CPUPPCState *env, uint32_t bit) /* Update the floating-point enabled exception summary */ env->fpscr |= 1 << FPSCR_FEX; /* We have to update Rc1 before raising the exception */ - env->exception_index = POWERPC_EXCP_PROGRAM; + cs->exception_index = POWERPC_EXCP_PROGRAM; break; } } @@ -447,6 +455,7 @@ void helper_fpscr_setbit(CPUPPCState *env, uint32_t bit) void helper_store_fpscr(CPUPPCState *env, uint64_t arg, uint32_t mask) { + CPUState *cs = CPU(ppc_env_get_cpu(env)); target_ulong prev, new; int i; @@ -468,7 +477,7 @@ void helper_store_fpscr(CPUPPCState *env, uint64_t arg, uint32_t mask) } if ((fpscr_ex & fpscr_eex) != 0) { env->fpscr |= 1 << FPSCR_FEX; - env->exception_index = POWERPC_EXCP_PROGRAM; + cs->exception_index = POWERPC_EXCP_PROGRAM; /* XXX: we should compute it properly */ env->error_code = POWERPC_EXCP_FP; } else { @@ -484,6 +493,7 @@ void store_fpscr(CPUPPCState *env, uint64_t arg, uint32_t mask) void helper_float_check_status(CPUPPCState *env) { + CPUState *cs = CPU(ppc_env_get_cpu(env)); int status = get_float_exception_flags(&env->fp_status); if (status & float_flag_divbyzero) { @@ -496,11 +506,11 @@ void helper_float_check_status(CPUPPCState *env) float_inexact_excp(env); } - if (env->exception_index == POWERPC_EXCP_PROGRAM && + if (cs->exception_index == POWERPC_EXCP_PROGRAM && (env->error_code & POWERPC_EXCP_FP)) { /* Differred floating-point exception after target FPR update */ if (msr_fe0 != 0 || msr_fe1 != 0) { - helper_raise_exception_err(env, env->exception_index, + helper_raise_exception_err(env, cs->exception_index, env->error_code); } } diff --git a/target-ppc/kvm.c b/target-ppc/kvm.c index 32e7a8c0a7..81ec959b23 100644 --- a/target-ppc/kvm.c +++ b/target-ppc/kvm.c @@ -1178,7 +1178,7 @@ static int kvmppc_handle_halt(PowerPCCPU *cpu) if (!(cs->interrupt_request & CPU_INTERRUPT_HARD) && (msr_ee)) { cs->halted = 1; - env->exception_index = EXCP_HLT; + cs->exception_index = EXCP_HLT; } return 0; diff --git a/target-ppc/mmu-hash32.c b/target-ppc/mmu-hash32.c index 6a77dc4f97..aa87084238 100644 --- a/target-ppc/mmu-hash32.c +++ b/target-ppc/mmu-hash32.c @@ -222,6 +222,7 @@ static int ppc_hash32_direct_store(CPUPPCState *env, target_ulong sr, target_ulong eaddr, int rwx, hwaddr *raddr, int *prot) { + CPUState *cs = CPU(ppc_env_get_cpu(env)); int key = !!(msr_pr ? (sr & SR32_KP) : (sr & SR32_KS)); LOG_MMU("direct store...\n"); @@ -238,7 +239,7 @@ static int ppc_hash32_direct_store(CPUPPCState *env, target_ulong sr, if (rwx == 2) { /* No code fetch is allowed in direct-store areas */ - env->exception_index = POWERPC_EXCP_ISI; + cs->exception_index = POWERPC_EXCP_ISI; env->error_code = 0x10000000; return 1; } @@ -249,7 +250,7 @@ static int ppc_hash32_direct_store(CPUPPCState *env, target_ulong sr, break; case ACCESS_FLOAT: /* Floating point load/store */ - env->exception_index = POWERPC_EXCP_ALIGN; + cs->exception_index = POWERPC_EXCP_ALIGN; env->error_code = POWERPC_EXCP_ALIGN_FP; env->spr[SPR_DAR] = eaddr; return 1; @@ -272,7 +273,7 @@ static int ppc_hash32_direct_store(CPUPPCState *env, target_ulong sr, return 0; case ACCESS_EXT: /* eciwx or ecowx */ - env->exception_index = POWERPC_EXCP_DSI; + cs->exception_index = POWERPC_EXCP_DSI; env->error_code = 0; env->spr[SPR_DAR] = eaddr; if (rwx == 1) { @@ -290,7 +291,7 @@ static int ppc_hash32_direct_store(CPUPPCState *env, target_ulong sr, *raddr = eaddr; return 0; } else { - env->exception_index = POWERPC_EXCP_DSI; + cs->exception_index = POWERPC_EXCP_DSI; env->error_code = 0; env->spr[SPR_DAR] = eaddr; if (rwx == 1) { @@ -383,6 +384,7 @@ static hwaddr ppc_hash32_pte_raddr(target_ulong sr, ppc_hash_pte32_t pte, int ppc_hash32_handle_mmu_fault(CPUPPCState *env, target_ulong eaddr, int rwx, int mmu_idx) { + CPUState *cs = CPU(ppc_env_get_cpu(env)); target_ulong sr; hwaddr pte_offset; ppc_hash_pte32_t pte; @@ -409,10 +411,10 @@ int ppc_hash32_handle_mmu_fault(CPUPPCState *env, target_ulong eaddr, int rwx, if (raddr != -1) { if (need_prot[rwx] & ~prot) { if (rwx == 2) { - env->exception_index = POWERPC_EXCP_ISI; + cs->exception_index = POWERPC_EXCP_ISI; env->error_code = 0x08000000; } else { - env->exception_index = POWERPC_EXCP_DSI; + cs->exception_index = POWERPC_EXCP_DSI; env->error_code = 0; env->spr[SPR_DAR] = eaddr; if (rwx == 1) { @@ -449,7 +451,7 @@ int ppc_hash32_handle_mmu_fault(CPUPPCState *env, target_ulong eaddr, int rwx, /* 5. Check for segment level no-execute violation */ if ((rwx == 2) && (sr & SR32_NX)) { - env->exception_index = POWERPC_EXCP_ISI; + cs->exception_index = POWERPC_EXCP_ISI; env->error_code = 0x10000000; return 1; } @@ -458,10 +460,10 @@ int ppc_hash32_handle_mmu_fault(CPUPPCState *env, target_ulong eaddr, int rwx, pte_offset = ppc_hash32_htab_lookup(env, sr, eaddr, &pte); if (pte_offset == -1) { if (rwx == 2) { - env->exception_index = POWERPC_EXCP_ISI; + cs->exception_index = POWERPC_EXCP_ISI; env->error_code = 0x40000000; } else { - env->exception_index = POWERPC_EXCP_DSI; + cs->exception_index = POWERPC_EXCP_DSI; env->error_code = 0; env->spr[SPR_DAR] = eaddr; if (rwx == 1) { @@ -483,10 +485,10 @@ int ppc_hash32_handle_mmu_fault(CPUPPCState *env, target_ulong eaddr, int rwx, /* Access right violation */ LOG_MMU("PTE access rejected\n"); if (rwx == 2) { - env->exception_index = POWERPC_EXCP_ISI; + cs->exception_index = POWERPC_EXCP_ISI; env->error_code = 0x08000000; } else { - env->exception_index = POWERPC_EXCP_DSI; + cs->exception_index = POWERPC_EXCP_DSI; env->error_code = 0; env->spr[SPR_DAR] = eaddr; if (rwx == 1) { diff --git a/target-ppc/mmu-hash64.c b/target-ppc/mmu-hash64.c index 438d0b732f..7186c0dbb4 100644 --- a/target-ppc/mmu-hash64.c +++ b/target-ppc/mmu-hash64.c @@ -457,6 +457,7 @@ static hwaddr ppc_hash64_pte_raddr(ppc_slb_t *slb, ppc_hash_pte64_t pte, int ppc_hash64_handle_mmu_fault(CPUPPCState *env, target_ulong eaddr, int rwx, int mmu_idx) { + CPUState *cs = CPU(ppc_env_get_cpu(env)); ppc_slb_t *slb; hwaddr pte_offset; ppc_hash_pte64_t pte; @@ -483,10 +484,10 @@ int ppc_hash64_handle_mmu_fault(CPUPPCState *env, target_ulong eaddr, if (!slb) { if (rwx == 2) { - env->exception_index = POWERPC_EXCP_ISEG; + cs->exception_index = POWERPC_EXCP_ISEG; env->error_code = 0; } else { - env->exception_index = POWERPC_EXCP_DSEG; + cs->exception_index = POWERPC_EXCP_DSEG; env->error_code = 0; env->spr[SPR_DAR] = eaddr; } @@ -495,7 +496,7 @@ int ppc_hash64_handle_mmu_fault(CPUPPCState *env, target_ulong eaddr, /* 3. Check for segment level no-execute violation */ if ((rwx == 2) && (slb->vsid & SLB_VSID_N)) { - env->exception_index = POWERPC_EXCP_ISI; + cs->exception_index = POWERPC_EXCP_ISI; env->error_code = 0x10000000; return 1; } @@ -504,10 +505,10 @@ int ppc_hash64_handle_mmu_fault(CPUPPCState *env, target_ulong eaddr, pte_offset = ppc_hash64_htab_lookup(env, slb, eaddr, &pte); if (pte_offset == -1) { if (rwx == 2) { - env->exception_index = POWERPC_EXCP_ISI; + cs->exception_index = POWERPC_EXCP_ISI; env->error_code = 0x40000000; } else { - env->exception_index = POWERPC_EXCP_DSI; + cs->exception_index = POWERPC_EXCP_DSI; env->error_code = 0; env->spr[SPR_DAR] = eaddr; if (rwx == 1) { @@ -530,12 +531,12 @@ int ppc_hash64_handle_mmu_fault(CPUPPCState *env, target_ulong eaddr, /* Access right violation */ LOG_MMU("PTE access rejected\n"); if (rwx == 2) { - env->exception_index = POWERPC_EXCP_ISI; + cs->exception_index = POWERPC_EXCP_ISI; env->error_code = 0x08000000; } else { target_ulong dsisr = 0; - env->exception_index = POWERPC_EXCP_DSI; + cs->exception_index = POWERPC_EXCP_DSI; env->error_code = 0; env->spr[SPR_DAR] = eaddr; if (need_prot[rwx] & ~pp_prot) { diff --git a/target-ppc/mmu_helper.c b/target-ppc/mmu_helper.c index 8e2f8e736a..b6abd974e3 100644 --- a/target-ppc/mmu_helper.c +++ b/target-ppc/mmu_helper.c @@ -1491,6 +1491,7 @@ static void booke206_update_mas_tlb_miss(CPUPPCState *env, target_ulong address, static int cpu_ppc_handle_mmu_fault(CPUPPCState *env, target_ulong address, int rw, int mmu_idx) { + CPUState *cs = CPU(ppc_env_get_cpu(env)); mmu_ctx_t ctx; int access_type; int ret = 0; @@ -1510,24 +1511,24 @@ static int cpu_ppc_handle_mmu_fault(CPUPPCState *env, target_ulong address, mmu_idx, TARGET_PAGE_SIZE); ret = 0; } else if (ret < 0) { - LOG_MMU_STATE(CPU(ppc_env_get_cpu(env))); + LOG_MMU_STATE(cs); if (access_type == ACCESS_CODE) { switch (ret) { case -1: /* No matches in page tables or TLB */ switch (env->mmu_model) { case POWERPC_MMU_SOFT_6xx: - env->exception_index = POWERPC_EXCP_IFTLB; + cs->exception_index = POWERPC_EXCP_IFTLB; env->error_code = 1 << 18; env->spr[SPR_IMISS] = address; env->spr[SPR_ICMP] = 0x80000000 | ctx.ptem; goto tlb_miss; case POWERPC_MMU_SOFT_74xx: - env->exception_index = POWERPC_EXCP_IFTLB; + cs->exception_index = POWERPC_EXCP_IFTLB; goto tlb_miss_74xx; case POWERPC_MMU_SOFT_4xx: case POWERPC_MMU_SOFT_4xx_Z: - env->exception_index = POWERPC_EXCP_ITLB; + cs->exception_index = POWERPC_EXCP_ITLB; env->error_code = 0; env->spr[SPR_40x_DEAR] = address; env->spr[SPR_40x_ESR] = 0x00000000; @@ -1536,7 +1537,7 @@ static int cpu_ppc_handle_mmu_fault(CPUPPCState *env, target_ulong address, booke206_update_mas_tlb_miss(env, address, rw); /* fall through */ case POWERPC_MMU_BOOKE: - env->exception_index = POWERPC_EXCP_ITLB; + cs->exception_index = POWERPC_EXCP_ITLB; env->error_code = 0; env->spr[SPR_BOOKE_DEAR] = address; return -1; @@ -1555,7 +1556,7 @@ static int cpu_ppc_handle_mmu_fault(CPUPPCState *env, target_ulong address, break; case -2: /* Access rights violation */ - env->exception_index = POWERPC_EXCP_ISI; + cs->exception_index = POWERPC_EXCP_ISI; env->error_code = 0x08000000; break; case -3: @@ -1564,13 +1565,13 @@ static int cpu_ppc_handle_mmu_fault(CPUPPCState *env, target_ulong address, (env->mmu_model == POWERPC_MMU_BOOKE206)) { env->spr[SPR_BOOKE_ESR] = 0x00000000; } - env->exception_index = POWERPC_EXCP_ISI; + cs->exception_index = POWERPC_EXCP_ISI; env->error_code = 0x10000000; break; case -4: /* Direct store exception */ /* No code fetch is allowed in direct-store areas */ - env->exception_index = POWERPC_EXCP_ISI; + cs->exception_index = POWERPC_EXCP_ISI; env->error_code = 0x10000000; break; } @@ -1581,10 +1582,10 @@ static int cpu_ppc_handle_mmu_fault(CPUPPCState *env, target_ulong address, switch (env->mmu_model) { case POWERPC_MMU_SOFT_6xx: if (rw == 1) { - env->exception_index = POWERPC_EXCP_DSTLB; + cs->exception_index = POWERPC_EXCP_DSTLB; env->error_code = 1 << 16; } else { - env->exception_index = POWERPC_EXCP_DLTLB; + cs->exception_index = POWERPC_EXCP_DLTLB; env->error_code = 0; } env->spr[SPR_DMISS] = address; @@ -1598,9 +1599,9 @@ static int cpu_ppc_handle_mmu_fault(CPUPPCState *env, target_ulong address, break; case POWERPC_MMU_SOFT_74xx: if (rw == 1) { - env->exception_index = POWERPC_EXCP_DSTLB; + cs->exception_index = POWERPC_EXCP_DSTLB; } else { - env->exception_index = POWERPC_EXCP_DLTLB; + cs->exception_index = POWERPC_EXCP_DLTLB; } tlb_miss_74xx: /* Implement LRU algorithm */ @@ -1611,7 +1612,7 @@ static int cpu_ppc_handle_mmu_fault(CPUPPCState *env, target_ulong address, break; case POWERPC_MMU_SOFT_4xx: case POWERPC_MMU_SOFT_4xx_Z: - env->exception_index = POWERPC_EXCP_DTLB; + cs->exception_index = POWERPC_EXCP_DTLB; env->error_code = 0; env->spr[SPR_40x_DEAR] = address; if (rw) { @@ -1628,7 +1629,7 @@ static int cpu_ppc_handle_mmu_fault(CPUPPCState *env, target_ulong address, booke206_update_mas_tlb_miss(env, address, rw); /* fall through */ case POWERPC_MMU_BOOKE: - env->exception_index = POWERPC_EXCP_DTLB; + cs->exception_index = POWERPC_EXCP_DTLB; env->error_code = 0; env->spr[SPR_BOOKE_DEAR] = address; env->spr[SPR_BOOKE_ESR] = rw ? ESR_ST : 0; @@ -1644,7 +1645,7 @@ static int cpu_ppc_handle_mmu_fault(CPUPPCState *env, target_ulong address, break; case -2: /* Access rights violation */ - env->exception_index = POWERPC_EXCP_DSI; + cs->exception_index = POWERPC_EXCP_DSI; env->error_code = 0; if (env->mmu_model == POWERPC_MMU_SOFT_4xx || env->mmu_model == POWERPC_MMU_SOFT_4xx_Z) { @@ -1670,13 +1671,13 @@ static int cpu_ppc_handle_mmu_fault(CPUPPCState *env, target_ulong address, switch (access_type) { case ACCESS_FLOAT: /* Floating point load/store */ - env->exception_index = POWERPC_EXCP_ALIGN; + cs->exception_index = POWERPC_EXCP_ALIGN; env->error_code = POWERPC_EXCP_ALIGN_FP; env->spr[SPR_DAR] = address; break; case ACCESS_RES: /* lwarx, ldarx or stwcx. */ - env->exception_index = POWERPC_EXCP_DSI; + cs->exception_index = POWERPC_EXCP_DSI; env->error_code = 0; env->spr[SPR_DAR] = address; if (rw == 1) { @@ -1687,7 +1688,7 @@ static int cpu_ppc_handle_mmu_fault(CPUPPCState *env, target_ulong address, break; case ACCESS_EXT: /* eciwx or ecowx */ - env->exception_index = POWERPC_EXCP_DSI; + cs->exception_index = POWERPC_EXCP_DSI; env->error_code = 0; env->spr[SPR_DAR] = address; if (rw == 1) { @@ -1698,7 +1699,7 @@ static int cpu_ppc_handle_mmu_fault(CPUPPCState *env, target_ulong address, break; default: printf("DSI: invalid exception (%d)\n", ret); - env->exception_index = POWERPC_EXCP_PROGRAM; + cs->exception_index = POWERPC_EXCP_PROGRAM; env->error_code = POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_INVAL; env->spr[SPR_DAR] = address; @@ -1709,7 +1710,7 @@ static int cpu_ppc_handle_mmu_fault(CPUPPCState *env, target_ulong address, } #if 0 printf("%s: set exception to %d %02x\n", __func__, - env->exception, env->error_code); + cs->exception, env->error_code); #endif ret = 1; } @@ -2909,6 +2910,6 @@ void tlb_fill(CPUPPCState *env, target_ulong addr, int is_write, int mmu_idx, /* now we have a real cpu fault */ cpu_restore_state(env, retaddr); } - helper_raise_exception_err(env, env->exception_index, env->error_code); + helper_raise_exception_err(env, cpu->exception_index, env->error_code); } } diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c index 703b3d8797..e22d82f604 100644 --- a/target-ppc/translate_init.c +++ b/target-ppc/translate_init.c @@ -8422,7 +8422,7 @@ static void ppc_cpu_reset(CPUState *s) env->reserve_addr = (target_ulong)-1ULL; /* Be sure no exception or interrupt is pending */ env->pending_interrupts = 0; - env->exception_index = POWERPC_EXCP_NONE; + s->exception_index = POWERPC_EXCP_NONE; env->error_code = 0; #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) diff --git a/target-ppc/user_only_helper.c b/target-ppc/user_only_helper.c index a7c99e032b..829f66f504 100644 --- a/target-ppc/user_only_helper.c +++ b/target-ppc/user_only_helper.c @@ -39,7 +39,7 @@ int ppc_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw, env->spr[SPR_DAR] = address; env->spr[SPR_DSISR] = error_code; } - env->exception_index = exception; + cs->exception_index = exception; env->error_code = error_code; return 1; diff --git a/target-s390x/helper.c b/target-s390x/helper.c index e71e5fd563..6262f42762 100644 --- a/target-s390x/helper.c +++ b/target-s390x/helper.c @@ -85,10 +85,7 @@ S390CPU *cpu_s390x_init(const char *cpu_model) void s390_cpu_do_interrupt(CPUState *cs) { - S390CPU *cpu = S390_CPU(cs); - CPUS390XState *env = &cpu->env; - - env->exception_index = -1; + cs->exception_index = -1; } int s390_cpu_handle_mmu_fault(CPUState *cs, vaddr address, @@ -96,7 +93,7 @@ int s390_cpu_handle_mmu_fault(CPUState *cs, vaddr address, { S390CPU *cpu = S390_CPU(cs); - cpu->env.exception_index = EXCP_PGM; + cs->exception_index = EXCP_PGM; cpu->env.int_pgm_code = PGM_ADDRESSING; /* On real machines this value is dropped into LowMem. Since this is userland, simply put this someplace that cpu_loop can find it. */ @@ -110,7 +107,9 @@ int s390_cpu_handle_mmu_fault(CPUState *cs, vaddr address, static void trigger_pgm_exception(CPUS390XState *env, uint32_t code, uint32_t ilen) { - env->exception_index = EXCP_PGM; + CPUState *cs = CPU(s390_env_get_cpu(env)); + + cs->exception_index = EXCP_PGM; env->int_pgm_code = code; env->int_pgm_ilen = ilen; } @@ -429,7 +428,7 @@ hwaddr s390_cpu_get_phys_page_debug(CPUState *cs, vaddr vaddr) CPUS390XState *env = &cpu->env; target_ulong raddr; int prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; - int old_exc = env->exception_index; + int old_exc = cs->exception_index; uint64_t asc = env->psw.mask & PSW_MASK_ASC; /* 31-Bit mode */ @@ -438,7 +437,7 @@ hwaddr s390_cpu_get_phys_page_debug(CPUState *cs, vaddr vaddr) } mmu_translate(env, vaddr, 2, asc, &raddr, &prot); - env->exception_index = old_exc; + cs->exception_index = old_exc; return raddr; } @@ -456,7 +455,7 @@ void load_psw(CPUS390XState *env, uint64_t mask, uint64_t addr) } } cs->halted = 1; - env->exception_index = EXCP_HLT; + cs->exception_index = EXCP_HLT; } env->psw.addr = addr; @@ -753,43 +752,43 @@ void s390_cpu_do_interrupt(CPUState *cs) CPUS390XState *env = &cpu->env; qemu_log_mask(CPU_LOG_INT, "%s: %d at pc=%" PRIx64 "\n", - __func__, env->exception_index, env->psw.addr); + __func__, cs->exception_index, env->psw.addr); s390_add_running_cpu(cpu); /* handle machine checks */ if ((env->psw.mask & PSW_MASK_MCHECK) && - (env->exception_index == -1)) { + (cs->exception_index == -1)) { if (env->pending_int & INTERRUPT_MCHK) { - env->exception_index = EXCP_MCHK; + cs->exception_index = EXCP_MCHK; } } /* handle external interrupts */ if ((env->psw.mask & PSW_MASK_EXT) && - env->exception_index == -1) { + cs->exception_index == -1) { if (env->pending_int & INTERRUPT_EXT) { /* code is already in env */ - env->exception_index = EXCP_EXT; + cs->exception_index = EXCP_EXT; } else if (env->pending_int & INTERRUPT_TOD) { cpu_inject_ext(cpu, 0x1004, 0, 0); - env->exception_index = EXCP_EXT; + cs->exception_index = EXCP_EXT; env->pending_int &= ~INTERRUPT_EXT; env->pending_int &= ~INTERRUPT_TOD; } else if (env->pending_int & INTERRUPT_CPUTIMER) { cpu_inject_ext(cpu, 0x1005, 0, 0); - env->exception_index = EXCP_EXT; + cs->exception_index = EXCP_EXT; env->pending_int &= ~INTERRUPT_EXT; env->pending_int &= ~INTERRUPT_TOD; } } /* handle I/O interrupts */ if ((env->psw.mask & PSW_MASK_IO) && - (env->exception_index == -1)) { + (cs->exception_index == -1)) { if (env->pending_int & INTERRUPT_IO) { - env->exception_index = EXCP_IO; + cs->exception_index = EXCP_IO; } } - switch (env->exception_index) { + switch (cs->exception_index) { case EXCP_PGM: do_program_interrupt(env); break; @@ -806,7 +805,7 @@ void s390_cpu_do_interrupt(CPUState *cs) do_mchk_interrupt(env); break; } - env->exception_index = -1; + cs->exception_index = -1; if (!env->pending_int) { cs->interrupt_request &= ~CPU_INTERRUPT_HARD; diff --git a/target-s390x/mem_helper.c b/target-s390x/mem_helper.c index d9dc8ae3df..411c32692a 100644 --- a/target-s390x/mem_helper.c +++ b/target-s390x/mem_helper.c @@ -1052,8 +1052,9 @@ void HELPER(stura)(CPUS390XState *env, uint64_t addr, uint64_t v1) /* load real address */ uint64_t HELPER(lra)(CPUS390XState *env, uint64_t addr) { + CPUState *cs = CPU(s390_env_get_cpu(env)); uint32_t cc = 0; - int old_exc = env->exception_index; + int old_exc = cs->exception_index; uint64_t asc = env->psw.mask & PSW_MASK_ASC; uint64_t ret; int flags; @@ -1063,16 +1064,16 @@ uint64_t HELPER(lra)(CPUS390XState *env, uint64_t addr) program_interrupt(env, PGM_SPECIAL_OP, 2); } - env->exception_index = old_exc; + cs->exception_index = old_exc; if (mmu_translate(env, addr, 0, asc, &ret, &flags)) { cc = 3; } - if (env->exception_index == EXCP_PGM) { + if (cs->exception_index == EXCP_PGM) { ret = env->int_pgm_code | 0x80000000; } else { ret |= addr & ~TARGET_PAGE_MASK; } - env->exception_index = old_exc; + cs->exception_index = old_exc; env->cc_op = cc; return ret; diff --git a/target-s390x/misc_helper.c b/target-s390x/misc_helper.c index 728456f295..69da9e56a9 100644 --- a/target-s390x/misc_helper.c +++ b/target-s390x/misc_helper.c @@ -47,9 +47,10 @@ void QEMU_NORETURN runtime_exception(CPUS390XState *env, int excp, uintptr_t retaddr) { + CPUState *cs = CPU(s390_env_get_cpu(env)); int t; - env->exception_index = EXCP_PGM; + cs->exception_index = EXCP_PGM; env->int_pgm_code = excp; /* Use the (ultimate) callers address to find the insn that trapped. */ @@ -66,8 +67,10 @@ void QEMU_NORETURN runtime_exception(CPUS390XState *env, int excp, /* Raise an exception statically from a TB. */ void HELPER(exception)(CPUS390XState *env, uint32_t excp) { + CPUState *cs = CPU(s390_env_get_cpu(env)); + HELPER_LOG("%s: exception %d\n", __func__, excp); - env->exception_index = excp; + cs->exception_index = excp; cpu_loop_exit(env); } @@ -75,17 +78,21 @@ void HELPER(exception)(CPUS390XState *env, uint32_t excp) void program_interrupt(CPUS390XState *env, uint32_t code, int ilen) { + S390CPU *cpu = s390_env_get_cpu(env); + qemu_log_mask(CPU_LOG_INT, "program interrupt at %#" PRIx64 "\n", env->psw.addr); if (kvm_enabled()) { #ifdef CONFIG_KVM - kvm_s390_interrupt(s390_env_get_cpu(env), KVM_S390_PROGRAM_INT, code); + kvm_s390_interrupt(cpu, KVM_S390_PROGRAM_INT, code); #endif } else { + CPUState *cs = CPU(cpu); + env->int_pgm_code = code; env->int_pgm_ilen = ilen; - env->exception_index = EXCP_PGM; + cs->exception_index = EXCP_PGM; cpu_loop_exit(env); } } diff --git a/target-sh4/helper.c b/target-sh4/helper.c index 3f8f1fa296..0357cebb81 100644 --- a/target-sh4/helper.c +++ b/target-sh4/helper.c @@ -33,10 +33,7 @@ void superh_cpu_do_interrupt(CPUState *cs) { - SuperHCPU *cpu = SUPERH_CPU(cs); - CPUSH4State *env = &cpu->env; - - env->exception_index = -1; + cs->exception_index = -1; } int superh_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw, @@ -46,16 +43,16 @@ int superh_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw, CPUSH4State *env = &cpu->env; env->tea = address; - env->exception_index = -1; + cs->exception_index = -1; switch (rw) { case 0: - env->exception_index = 0x0a0; + cs->exception_index = 0x0a0; break; case 1: - env->exception_index = 0x0c0; + cs->exception_index = 0x0c0; break; case 2: - env->exception_index = 0x0a0; + cs->exception_index = 0x0a0; break; } return 1; @@ -89,16 +86,16 @@ void superh_cpu_do_interrupt(CPUState *cs) SuperHCPU *cpu = SUPERH_CPU(cs); CPUSH4State *env = &cpu->env; int do_irq = cs->interrupt_request & CPU_INTERRUPT_HARD; - int do_exp, irq_vector = env->exception_index; + int do_exp, irq_vector = cs->exception_index; /* prioritize exceptions over interrupts */ - do_exp = env->exception_index != -1; - do_irq = do_irq && (env->exception_index == -1); + do_exp = cs->exception_index != -1; + do_irq = do_irq && (cs->exception_index == -1); if (env->sr & SR_BL) { - if (do_exp && env->exception_index != 0x1e0) { - env->exception_index = 0x000; /* masked exception -> reset */ + if (do_exp && cs->exception_index != 0x1e0) { + cs->exception_index = 0x000; /* masked exception -> reset */ } if (do_irq && !env->in_sleep) { return; /* masked */ @@ -116,7 +113,7 @@ void superh_cpu_do_interrupt(CPUState *cs) if (qemu_loglevel_mask(CPU_LOG_INT)) { const char *expname; - switch (env->exception_index) { + switch (cs->exception_index) { case 0x0e0: expname = "addr_error"; break; @@ -180,8 +177,8 @@ void superh_cpu_do_interrupt(CPUState *cs) env->flags = 0; if (do_exp) { - env->expevt = env->exception_index; - switch (env->exception_index) { + env->expevt = cs->exception_index; + switch (cs->exception_index) { case 0x000: case 0x020: case 0x140: @@ -472,33 +469,33 @@ int superh_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw, switch (ret) { case MMU_ITLB_MISS: case MMU_DTLB_MISS_READ: - env->exception_index = 0x040; + cs->exception_index = 0x040; break; case MMU_DTLB_MULTIPLE: case MMU_ITLB_MULTIPLE: - env->exception_index = 0x140; + cs->exception_index = 0x140; break; case MMU_ITLB_VIOLATION: - env->exception_index = 0x0a0; + cs->exception_index = 0x0a0; break; case MMU_DTLB_MISS_WRITE: - env->exception_index = 0x060; + cs->exception_index = 0x060; break; case MMU_DTLB_INITIAL_WRITE: - env->exception_index = 0x080; + cs->exception_index = 0x080; break; case MMU_DTLB_VIOLATION_READ: - env->exception_index = 0x0a0; + cs->exception_index = 0x0a0; break; case MMU_DTLB_VIOLATION_WRITE: - env->exception_index = 0x0c0; + cs->exception_index = 0x0c0; break; case MMU_IADDR_ERROR: case MMU_DADDR_ERROR_READ: - env->exception_index = 0x0e0; + cs->exception_index = 0x0e0; break; case MMU_DADDR_ERROR_WRITE: - env->exception_index = 0x100; + cs->exception_index = 0x100; break; default: cpu_abort(env, "Unhandled MMU fault"); @@ -702,8 +699,10 @@ void cpu_sh4_write_mmaped_utlb_addr(CPUSH4State *s, hwaddr addr, if (entry->vpn == vpn && (!use_asid || entry->asid == asid || entry->sh)) { if (utlb_match_entry) { + CPUState *cs = CPU(sh_env_get_cpu(s)); + /* Multiple TLB Exception */ - s->exception_index = 0x140; + cs->exception_index = 0x140; s->tea = addr; break; } diff --git a/target-sh4/op_helper.c b/target-sh4/op_helper.c index 35f906788a..03633f0ee8 100644 --- a/target-sh4/op_helper.c +++ b/target-sh4/op_helper.c @@ -69,7 +69,9 @@ void helper_ldtlb(CPUSH4State *env) static inline void QEMU_NORETURN raise_exception(CPUSH4State *env, int index, uintptr_t retaddr) { - env->exception_index = index; + CPUState *cs = CPU(sh_env_get_cpu(env)); + + cs->exception_index = index; if (retaddr) { cpu_restore_state(env, retaddr); } diff --git a/target-sparc/helper.c b/target-sparc/helper.c index 57c20af478..a393ef0a48 100644 --- a/target-sparc/helper.c +++ b/target-sparc/helper.c @@ -24,13 +24,17 @@ void helper_raise_exception(CPUSPARCState *env, int tt) { - env->exception_index = tt; + CPUState *cs = CPU(sparc_env_get_cpu(env)); + + cs->exception_index = tt; cpu_loop_exit(env); } void helper_debug(CPUSPARCState *env) { - env->exception_index = EXCP_DEBUG; + CPUState *cs = CPU(sparc_env_get_cpu(env)); + + cs->exception_index = EXCP_DEBUG; cpu_loop_exit(env); } @@ -232,7 +236,7 @@ void helper_power_down(CPUSPARCState *env) CPUState *cs = CPU(sparc_env_get_cpu(env)); cs->halted = 1; - env->exception_index = EXCP_HLT; + cs->exception_index = EXCP_HLT; env->pc = env->npc; env->npc = env->pc + 4; cpu_loop_exit(env); diff --git a/target-sparc/int32_helper.c b/target-sparc/int32_helper.c index d5322380cd..f350a903e0 100644 --- a/target-sparc/int32_helper.c +++ b/target-sparc/int32_helper.c @@ -62,7 +62,7 @@ void sparc_cpu_do_interrupt(CPUState *cs) { SPARCCPU *cpu = SPARC_CPU(cs); CPUSPARCState *env = &cpu->env; - int cwp, intno = env->exception_index; + int cwp, intno = cs->exception_index; /* Compute PSR before exposing state. */ if (env->cc_op != CC_OP_FLAGS) { @@ -105,12 +105,12 @@ void sparc_cpu_do_interrupt(CPUState *cs) #endif #if !defined(CONFIG_USER_ONLY) if (env->psret == 0) { - if (env->exception_index == 0x80 && + if (cs->exception_index == 0x80 && env->def->features & CPU_FEATURE_TA0_SHUTDOWN) { qemu_system_shutdown_request(); } else { cpu_abort(env, "Trap 0x%02x while interrupts disabled, Error state", - env->exception_index); + cs->exception_index); } return; } @@ -125,7 +125,7 @@ void sparc_cpu_do_interrupt(CPUState *cs) env->tbr = (env->tbr & TBR_BASE_MASK) | (intno << 4); env->pc = env->tbr; env->npc = env->pc + 4; - env->exception_index = -1; + cs->exception_index = -1; #if !defined(CONFIG_USER_ONLY) /* IRQ acknowledgment */ diff --git a/target-sparc/int64_helper.c b/target-sparc/int64_helper.c index bf7dd86ab8..1744245f70 100644 --- a/target-sparc/int64_helper.c +++ b/target-sparc/int64_helper.c @@ -63,7 +63,7 @@ void sparc_cpu_do_interrupt(CPUState *cs) { SPARCCPU *cpu = SPARC_CPU(cs); CPUSPARCState *env = &cpu->env; - int intno = env->exception_index; + int intno = cs->exception_index; trap_state *tsptr; /* Compute PSR before exposing state. */ @@ -112,7 +112,7 @@ void sparc_cpu_do_interrupt(CPUState *cs) #if !defined(CONFIG_USER_ONLY) if (env->tl >= env->maxtl) { cpu_abort(env, "Trap 0x%04x while trap level (%d) >= MAXTL (%d)," - " Error state", env->exception_index, env->tl, env->maxtl); + " Error state", cs->exception_index, env->tl, env->maxtl); return; } #endif @@ -160,7 +160,7 @@ void sparc_cpu_do_interrupt(CPUState *cs) env->tbr |= ((env->tl > 1) ? 1 << 14 : 0) | (intno << 5); env->pc = env->tbr; env->npc = env->pc + 4; - env->exception_index = -1; + cs->exception_index = -1; } trap_state *cpu_tsptr(CPUSPARCState* env) diff --git a/target-sparc/ldst_helper.c b/target-sparc/ldst_helper.c index c2482454ac..e1475d0b0f 100644 --- a/target-sparc/ldst_helper.c +++ b/target-sparc/ldst_helper.c @@ -1325,7 +1325,7 @@ uint64_t helper_ld_asi(CPUSPARCState *env, target_ulong addr, int asi, int size, dump_asi("read ", last_addr, asi, size, ret); #endif /* env->exception_index is set in get_physical_address_data(). */ - helper_raise_exception(env, env->exception_index); + helper_raise_exception(env, cs->exception_index); } /* convert nonfaulting load ASIs to normal load ASIs */ diff --git a/target-sparc/mmu_helper.c b/target-sparc/mmu_helper.c index 5a9748e347..1571c6a026 100644 --- a/target-sparc/mmu_helper.c +++ b/target-sparc/mmu_helper.c @@ -28,12 +28,10 @@ int sparc_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw, int mmu_idx) { - SPARCCPU *cpu = SPARC_CPU(cs); - if (rw & 2) { - cpu->env.exception_index = TT_TFAULT; + cs->exception_index = TT_TFAULT; } else { - cpu->env.exception_index = TT_DFAULT; + cs->exception_index = TT_DFAULT; } return 1; } @@ -239,9 +237,9 @@ int sparc_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw, return 0; } else { if (rw & 2) { - env->exception_index = TT_TFAULT; + cs->exception_index = TT_TFAULT; } else { - env->exception_index = TT_DFAULT; + cs->exception_index = TT_DFAULT; } return 1; } @@ -491,6 +489,7 @@ static int get_physical_address_data(CPUSPARCState *env, hwaddr *physical, int *prot, target_ulong address, int rw, int mmu_idx) { + CPUState *cs = CPU(sparc_env_get_cpu(env)); unsigned int i; uint64_t context; uint64_t sfsr = 0; @@ -555,10 +554,10 @@ static int get_physical_address_data(CPUSPARCState *env, if (do_fault) { /* faults above are reported with TT_DFAULT. */ - env->exception_index = TT_DFAULT; + cs->exception_index = TT_DFAULT; } else if (!TTE_IS_W_OK(env->dtlb[i].tte) && (rw == 1)) { do_fault = 1; - env->exception_index = TT_DPROT; + cs->exception_index = TT_DPROT; trace_mmu_helper_dprot(address, context, mmu_idx, env->tl); } @@ -602,7 +601,7 @@ static int get_physical_address_data(CPUSPARCState *env, * - JPS1: SFAR updated and some fields of SFSR updated */ env->dmmu.tag_access = (address & ~0x1fffULL) | context; - env->exception_index = TT_DMISS; + cs->exception_index = TT_DMISS; return 1; } @@ -610,6 +609,7 @@ static int get_physical_address_code(CPUSPARCState *env, hwaddr *physical, int *prot, target_ulong address, int mmu_idx) { + CPUState *cs = CPU(sparc_env_get_cpu(env)); unsigned int i; uint64_t context; @@ -653,7 +653,7 @@ static int get_physical_address_code(CPUSPARCState *env, /* FIXME: ASI field in SFSR must be set */ env->immu.sfsr |= SFSR_FT_PRIV_BIT | SFSR_VALID_BIT; - env->exception_index = TT_TFAULT; + cs->exception_index = TT_TFAULT; env->immu.tag_access = (address & ~0x1fffULL) | context; @@ -671,7 +671,7 @@ static int get_physical_address_code(CPUSPARCState *env, /* Context is stored in DMMU (dmmuregs[1]) also for IMMU */ env->immu.tag_access = (address & ~0x1fffULL) | context; - env->exception_index = TT_TMISS; + cs->exception_index = TT_TMISS; return 1; } diff --git a/target-unicore32/op_helper.c b/target-unicore32/op_helper.c index 5cd2378c6d..cd2cbef34f 100644 --- a/target-unicore32/op_helper.c +++ b/target-unicore32/op_helper.c @@ -16,7 +16,9 @@ void HELPER(exception)(CPUUniCore32State *env, uint32_t excp) { - env->exception_index = excp; + CPUState *cs = CPU(uc32_env_get_cpu(env)); + + cs->exception_index = excp; cpu_loop_exit(env); } diff --git a/target-unicore32/softmmu.c b/target-unicore32/softmmu.c index 75f73865f1..a55355ebe8 100644 --- a/target-unicore32/softmmu.c +++ b/target-unicore32/softmmu.c @@ -79,7 +79,7 @@ void uc32_cpu_do_interrupt(CPUState *cs) uint32_t addr; int new_mode; - switch (env->exception_index) { + switch (cs->exception_index) { case UC32_EXCP_PRIV: new_mode = ASR_MODE_PRIV; addr = 0x08; @@ -99,7 +99,7 @@ void uc32_cpu_do_interrupt(CPUState *cs) addr = 0x18; break; default: - cpu_abort(env, "Unhandled exception 0x%x\n", env->exception_index); + cpu_abort(env, "Unhandled exception 0x%x\n", cs->exception_index); return; } /* High vectors. */ @@ -257,9 +257,9 @@ int uc32_cpu_handle_mmu_fault(CPUState *cs, vaddr address, env->cp0.c3_faultstatus = ret; env->cp0.c4_faultaddr = address; if (access_type == 2) { - env->exception_index = UC32_EXCP_ITRAP; + cs->exception_index = UC32_EXCP_ITRAP; } else { - env->exception_index = UC32_EXCP_DTRAP; + cs->exception_index = UC32_EXCP_DTRAP; } return ret; } diff --git a/target-xtensa/helper.c b/target-xtensa/helper.c index 3cb0bbd972..259878837f 100644 --- a/target-xtensa/helper.c +++ b/target-xtensa/helper.c @@ -169,6 +169,8 @@ static void handle_interrupt(CPUXtensaState *env) (env->config->level_mask[level] & env->sregs[INTSET] & env->sregs[INTENABLE])) { + CPUState *cs = CPU(xtensa_env_get_cpu(env)); + if (level > 1) { env->sregs[EPC1 + level - 1] = env->pc; env->sregs[EPS2 + level - 2] = env->sregs[PS]; @@ -185,10 +187,10 @@ static void handle_interrupt(CPUXtensaState *env) } else { env->sregs[EPC1] = env->pc; } - env->exception_index = EXC_DOUBLE; + cs->exception_index = EXC_DOUBLE; } else { env->sregs[EPC1] = env->pc; - env->exception_index = + cs->exception_index = (env->sregs[PS] & PS_UM) ? EXC_USER : EXC_KERNEL; } env->sregs[PS] |= PS_EXCM; @@ -202,7 +204,7 @@ void xtensa_cpu_do_interrupt(CPUState *cs) XtensaCPU *cpu = XTENSA_CPU(cs); CPUXtensaState *env = &cpu->env; - if (env->exception_index == EXC_IRQ) { + if (cs->exception_index == EXC_IRQ) { qemu_log_mask(CPU_LOG_INT, "%s(EXC_IRQ) level = %d, cintlevel = %d, " "pc = %08x, a0 = %08x, ps = %08x, " @@ -215,7 +217,7 @@ void xtensa_cpu_do_interrupt(CPUState *cs) handle_interrupt(env); } - switch (env->exception_index) { + switch (cs->exception_index) { case EXC_WINDOW_OVERFLOW4: case EXC_WINDOW_UNDERFLOW4: case EXC_WINDOW_OVERFLOW8: @@ -228,15 +230,15 @@ void xtensa_cpu_do_interrupt(CPUState *cs) case EXC_DEBUG: qemu_log_mask(CPU_LOG_INT, "%s(%d) " "pc = %08x, a0 = %08x, ps = %08x, ccount = %08x\n", - __func__, env->exception_index, + __func__, cs->exception_index, env->pc, env->regs[0], env->sregs[PS], env->sregs[CCOUNT]); - if (env->config->exception_vector[env->exception_index]) { + if (env->config->exception_vector[cs->exception_index]) { env->pc = relocated_vector(env, - env->config->exception_vector[env->exception_index]); + env->config->exception_vector[cs->exception_index]); env->exception_taken = 1; } else { qemu_log("%s(pc = %08x) bad exception_index: %d\n", - __func__, env->pc, env->exception_index); + __func__, env->pc, cs->exception_index); } break; @@ -245,7 +247,7 @@ void xtensa_cpu_do_interrupt(CPUState *cs) default: qemu_log("%s(pc = %08x) unknown exception_index: %d\n", - __func__, env->pc, env->exception_index); + __func__, env->pc, cs->exception_index); break; } check_interrupts(env); diff --git a/target-xtensa/op_helper.c b/target-xtensa/op_helper.c index 509ba49d60..a314ed0b9d 100644 --- a/target-xtensa/op_helper.c +++ b/target-xtensa/op_helper.c @@ -97,7 +97,9 @@ static void tb_invalidate_virtual_addr(CPUXtensaState *env, uint32_t vaddr) void HELPER(exception)(CPUXtensaState *env, uint32_t excp) { - env->exception_index = excp; + CPUState *cs = CPU(xtensa_env_get_cpu(env)); + + cs->exception_index = excp; if (excp == EXCP_DEBUG) { env->exception_taken = 0; } diff --git a/user-exec.c b/user-exec.c index dec636eb1e..dbb9c8d0a7 100644 --- a/user-exec.c +++ b/user-exec.c @@ -41,7 +41,9 @@ static void exception_action(CPUArchState *env1) { #if defined(TARGET_I386) - raise_exception_err(env1, env1->exception_index, env1->error_code); + CPUState *cpu = ENV_GET_CPU(env1); + + raise_exception_err(env1, cpu->exception_index, env1->error_code); #else cpu_loop_exit(env1); #endif @@ -71,7 +73,7 @@ void cpu_resume_from_signal(CPUArchState *env1, void *puc) sigprocmask(SIG_SETMASK, &uc->sc_mask, NULL); #endif } - env1->exception_index = -1; + cpu->exception_index = -1; siglongjmp(cpu->jmp_env, 1); } -- cgit 1.4.1 From 0429a9719551a4aa794051aeb8c7b42658902c27 Mon Sep 17 00:00:00 2001 From: Andreas Färber Date: Mon, 26 Aug 2013 18:14:44 +0200 Subject: cpu: Move opaque field from CPU_COMMON to CPUState MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Andreas Färber --- bsd-user/main.c | 2 +- gdbstub.c | 3 +-- include/exec/cpu-defs.h | 3 --- include/qom/cpu.h | 3 +++ linux-user/elfload.c | 10 ++++++---- linux-user/linuxload.c | 3 +-- linux-user/m68k/target_cpu.h | 4 +++- linux-user/main.c | 6 +++--- linux-user/signal.c | 17 +++++++++++------ linux-user/syscall.c | 30 ++++++++++++++++++------------ linux-user/vm86.c | 27 ++++++++++++++++++--------- target-arm/arm-semi.c | 9 +++++---- target-m68k/m68k-semi.c | 3 ++- 13 files changed, 72 insertions(+), 48 deletions(-) (limited to 'include/exec') diff --git a/bsd-user/main.c b/bsd-user/main.c index f9246aa102..f81ba55af8 100644 --- a/bsd-user/main.c +++ b/bsd-user/main.c @@ -1000,7 +1000,7 @@ int main(int argc, char **argv) memset(ts, 0, sizeof(TaskState)); init_task_state(ts); ts->info = info; - env->opaque = ts; + cpu->opaque = ts; #if defined(TARGET_I386) cpu_x86_set_cpl(env, 3); diff --git a/gdbstub.c b/gdbstub.c index e8ab0b2992..c5ab73fb1d 100644 --- a/gdbstub.c +++ b/gdbstub.c @@ -1086,8 +1086,7 @@ static int gdb_handle_packet(GDBState *s, const char *line_buf) } #ifdef CONFIG_USER_ONLY else if (strncmp(p, "Offsets", 7) == 0) { - CPUArchState *env = s->c_cpu->env_ptr; - TaskState *ts = env->opaque; + TaskState *ts = s->c_cpu->opaque; snprintf(buf, sizeof(buf), "Text=" TARGET_ABI_FMT_lx ";Data=" TARGET_ABI_FMT_lx diff --git a/include/exec/cpu-defs.h b/include/exec/cpu-defs.h index bec06e8f99..8af85476fc 100644 --- a/include/exec/cpu-defs.h +++ b/include/exec/cpu-defs.h @@ -138,8 +138,5 @@ typedef struct CPUWatchpoint { \ QTAILQ_HEAD(watchpoints_head, CPUWatchpoint) watchpoints; \ CPUWatchpoint *watchpoint_hit; \ - \ - /* user data */ \ - void *opaque; \ #endif diff --git a/include/qom/cpu.h b/include/qom/cpu.h index a385b9f71d..4d1ea35ca4 100644 --- a/include/qom/cpu.h +++ b/include/qom/cpu.h @@ -184,6 +184,7 @@ struct kvm_run; * @gdb_num_regs: Number of total registers accessible to GDB. * @gdb_num_g_regs: Number of registers in GDB 'g' packets. * @next_cpu: Next CPU sharing TB cache. + * @opaque: User data. * @mem_io_pc: Host Program Counter at which the memory was accessed. * @mem_io_vaddr: Target virtual address at which the memory was accessed. * @kvm_fd: vCPU file descriptor for KVM. @@ -230,6 +231,8 @@ struct CPUState { int gdb_num_g_regs; QTAILQ_ENTRY(CPUState) node; + void *opaque; + /* In order to avoid passing too many arguments to the MMIO helpers, * we store some rarely used information in the CPU context. */ diff --git a/linux-user/elfload.c b/linux-user/elfload.c index c0687e3b38..6bc799957b 100644 --- a/linux-user/elfload.c +++ b/linux-user/elfload.c @@ -2621,7 +2621,8 @@ static int write_note(struct memelfnote *men, int fd) static void fill_thread_info(struct elf_note_info *info, const CPUArchState *env) { - TaskState *ts = (TaskState *)env->opaque; + CPUState *cpu = ENV_GET_CPU((CPUArchState *)env); + TaskState *ts = (TaskState *)cpu->opaque; struct elf_thread_status *ets; ets = g_malloc0(sizeof (*ets)); @@ -2650,8 +2651,8 @@ static int fill_note_info(struct elf_note_info *info, long signr, const CPUArchState *env) { #define NUMNOTES 3 - CPUState *cpu = NULL; - TaskState *ts = (TaskState *)env->opaque; + CPUState *cpu = ENV_GET_CPU((CPUArchState *)env); + TaskState *ts = (TaskState *)cpu->opaque; int i; info->notes = g_malloc0(NUMNOTES * sizeof (struct memelfnote)); @@ -2775,7 +2776,8 @@ static int write_note_info(struct elf_note_info *info, int fd) */ static int elf_core_dump(int signr, const CPUArchState *env) { - const TaskState *ts = (const TaskState *)env->opaque; + const CPUState *cpu = ENV_GET_CPU((CPUArchState *)env); + const TaskState *ts = (const TaskState *)cpu->opaque; struct vm_area_struct *vma = NULL; char corefile[PATH_MAX]; struct elf_note_info info; diff --git a/linux-user/linuxload.c b/linux-user/linuxload.c index f2997c2f4b..506e837ae1 100644 --- a/linux-user/linuxload.c +++ b/linux-user/linuxload.c @@ -89,8 +89,7 @@ static int prepare_binprm(struct linux_binprm *bprm) abi_ulong loader_build_argptr(int envc, int argc, abi_ulong sp, abi_ulong stringp, int push_ptr) { - CPUArchState *env = thread_cpu->env_ptr; - TaskState *ts = (TaskState *)env->opaque; + TaskState *ts = (TaskState *)thread_cpu->opaque; int n = sizeof(abi_ulong); abi_ulong envp; abi_ulong argv; diff --git a/linux-user/m68k/target_cpu.h b/linux-user/m68k/target_cpu.h index cad9c90dd0..bb4d3fabe1 100644 --- a/linux-user/m68k/target_cpu.h +++ b/linux-user/m68k/target_cpu.h @@ -31,7 +31,9 @@ static inline void cpu_clone_regs(CPUM68KState *env, target_ulong newsp) static inline void cpu_set_tls(CPUM68KState *env, target_ulong newtls) { - TaskState *ts = env->opaque; + CPUState *cs = CPU(m68k_env_get_cpu(env)); + TaskState *ts = cs->opaque; + ts->tp_value = newtls; } diff --git a/linux-user/main.c b/linux-user/main.c index dee10841c3..6e62b8babd 100644 --- a/linux-user/main.c +++ b/linux-user/main.c @@ -685,7 +685,7 @@ void cpu_loop(CPUARMState *env) switch(trapnr) { case EXCP_UDEF: { - TaskState *ts = env->opaque; + TaskState *ts = cs->opaque; uint32_t opcode; int rc; @@ -2965,7 +2965,7 @@ void cpu_loop(CPUM68KState *env) int trapnr; unsigned int n; target_siginfo_t info; - TaskState *ts = env->opaque; + TaskState *ts = cs->opaque; for(;;) { trapnr = cpu_m68k_exec(env); @@ -4001,7 +4001,7 @@ int main(int argc, char **argv, char **envp) /* build Task State */ ts->info = info; ts->bprm = &bprm; - env->opaque = ts; + cpu->opaque = ts; task_settid(ts); execfd = qemu_getauxval(AT_EXECFD); diff --git a/linux-user/signal.c b/linux-user/signal.c index acf10328ee..24c91f37d9 100644 --- a/linux-user/signal.c +++ b/linux-user/signal.c @@ -370,7 +370,8 @@ void signal_init(void) static inline struct sigqueue *alloc_sigqueue(CPUArchState *env) { - TaskState *ts = env->opaque; + CPUState *cpu = ENV_GET_CPU(env); + TaskState *ts = cpu->opaque; struct sigqueue *q = ts->first_free; if (!q) return NULL; @@ -380,7 +381,9 @@ static inline struct sigqueue *alloc_sigqueue(CPUArchState *env) static inline void free_sigqueue(CPUArchState *env, struct sigqueue *q) { - TaskState *ts = env->opaque; + CPUState *cpu = ENV_GET_CPU(env); + TaskState *ts = cpu->opaque; + q->next = ts->first_free; ts->first_free = q; } @@ -388,8 +391,9 @@ static inline void free_sigqueue(CPUArchState *env, struct sigqueue *q) /* abort execution with signal */ static void QEMU_NORETURN force_sig(int target_sig) { - CPUArchState *env = thread_cpu->env_ptr; - TaskState *ts = (TaskState *)env->opaque; + CPUState *cpu = thread_cpu; + CPUArchState *env = cpu->env_ptr; + TaskState *ts = (TaskState *)cpu->opaque; int host_sig, core_dumped = 0; struct sigaction act; host_sig = target_to_host_signal(target_sig); @@ -440,7 +444,8 @@ static void QEMU_NORETURN force_sig(int target_sig) as possible */ int queue_signal(CPUArchState *env, int sig, target_siginfo_t *info) { - TaskState *ts = env->opaque; + CPUState *cpu = ENV_GET_CPU(env); + TaskState *ts = cpu->opaque; struct emulated_sigtable *k; struct sigqueue *q, **pq; abi_ulong handler; @@ -5676,7 +5681,7 @@ void process_pending_signals(CPUArchState *cpu_env) struct emulated_sigtable *k; struct target_sigaction *sa; struct sigqueue *q; - TaskState *ts = cpu_env->opaque; + TaskState *ts = cpu->opaque; if (!ts->signal_pending) return; diff --git a/linux-user/syscall.c b/linux-user/syscall.c index e2c10cc0bd..ffc11de4b7 100644 --- a/linux-user/syscall.c +++ b/linux-user/syscall.c @@ -4243,7 +4243,7 @@ static void *clone_func(void *arg) env = info->env; cpu = ENV_GET_CPU(env); thread_cpu = cpu; - ts = (TaskState *)env->opaque; + ts = (TaskState *)cpu->opaque; info->tid = gettid(); cpu->host_tid = info->tid; task_settid(ts); @@ -4271,8 +4271,10 @@ static int do_fork(CPUArchState *env, unsigned int flags, abi_ulong newsp, abi_ulong parent_tidptr, target_ulong newtls, abi_ulong child_tidptr) { + CPUState *cpu = ENV_GET_CPU(env); int ret; TaskState *ts; + CPUState *new_cpu; CPUArchState *new_env; unsigned int nptl_flags; sigset_t sigmask; @@ -4282,7 +4284,7 @@ static int do_fork(CPUArchState *env, unsigned int flags, abi_ulong newsp, flags &= ~(CLONE_VFORK | CLONE_VM); if (flags & CLONE_VM) { - TaskState *parent_ts = (TaskState *)env->opaque; + TaskState *parent_ts = (TaskState *)cpu->opaque; new_thread_info info; pthread_attr_t attr; @@ -4292,7 +4294,8 @@ static int do_fork(CPUArchState *env, unsigned int flags, abi_ulong newsp, new_env = cpu_copy(env); /* Init regs that differ from the parent. */ cpu_clone_regs(new_env, newsp); - new_env->opaque = ts; + new_cpu = ENV_GET_CPU(new_env); + new_cpu->opaque = ts; ts->bprm = parent_ts->bprm; ts->info = parent_ts->info; nptl_flags = flags; @@ -4364,7 +4367,7 @@ static int do_fork(CPUArchState *env, unsigned int flags, abi_ulong newsp, put_user_u32(gettid(), child_tidptr); if (flags & CLONE_PARENT_SETTID) put_user_u32(gettid(), parent_tidptr); - ts = (TaskState *)env->opaque; + ts = (TaskState *)cpu->opaque; if (flags & CLONE_SETTLS) cpu_set_tls (env, newtls); if (flags & CLONE_CHILD_CLEARTID) @@ -4974,7 +4977,8 @@ void init_qemu_uname_release(void) static int open_self_maps(void *cpu_env, int fd) { #if defined(TARGET_ARM) || defined(TARGET_M68K) || defined(TARGET_UNICORE32) - TaskState *ts = ((CPUArchState *)cpu_env)->opaque; + CPUState *cpu = ENV_GET_CPU((CPUArchState *)cpu_env); + TaskState *ts = cpu->opaque; #endif FILE *fp; char *line = NULL; @@ -5026,7 +5030,8 @@ static int open_self_maps(void *cpu_env, int fd) static int open_self_stat(void *cpu_env, int fd) { - TaskState *ts = ((CPUArchState *)cpu_env)->opaque; + CPUState *cpu = ENV_GET_CPU((CPUArchState *)cpu_env); + TaskState *ts = cpu->opaque; abi_ulong start_stack = ts->info->start_stack; int i; @@ -5062,7 +5067,8 @@ static int open_self_stat(void *cpu_env, int fd) static int open_self_auxv(void *cpu_env, int fd) { - TaskState *ts = ((CPUArchState *)cpu_env)->opaque; + CPUState *cpu = ENV_GET_CPU((CPUArchState *)cpu_env); + TaskState *ts = cpu->opaque; abi_ulong auxv = ts->info->saved_auxv; abi_ulong len = ts->info->auxv_len; char *ptr; @@ -5244,14 +5250,14 @@ abi_long do_syscall(void *cpu_env, int num, abi_long arg1, /* Remove the CPU from the list. */ QTAILQ_REMOVE(&cpus, cpu, node); cpu_list_unlock(); - ts = ((CPUArchState *)cpu_env)->opaque; + ts = cpu->opaque; if (ts->child_tidptr) { put_user_u32(0, ts->child_tidptr); sys_futex(g2h(ts->child_tidptr), FUTEX_WAKE, INT_MAX, NULL, NULL, 0); } thread_cpu = NULL; - object_unref(OBJECT(ENV_GET_CPU(cpu_env))); + object_unref(OBJECT(cpu)); g_free(ts); pthread_exit(NULL); } @@ -6555,7 +6561,7 @@ abi_long do_syscall(void *cpu_env, int num, abi_long arg1, break; case TARGET_NR_mprotect: { - TaskState *ts = ((CPUArchState *)cpu_env)->opaque; + TaskState *ts = cpu->opaque; /* Special hack to detect libc making the stack executable. */ if ((arg3 & PROT_GROWSDOWN) && arg1 >= ts->info->stack_limit @@ -8647,7 +8653,7 @@ abi_long do_syscall(void *cpu_env, int num, abi_long arg1, break; #elif defined(TARGET_M68K) { - TaskState *ts = ((CPUArchState *)cpu_env)->opaque; + TaskState *ts = cpu->opaque; ts->tp_value = arg1; ret = 0; break; @@ -8663,7 +8669,7 @@ abi_long do_syscall(void *cpu_env, int num, abi_long arg1, break; #elif defined(TARGET_M68K) { - TaskState *ts = ((CPUArchState *)cpu_env)->opaque; + TaskState *ts = cpu->opaque; ret = ts->tp_value; break; } diff --git a/linux-user/vm86.c b/linux-user/vm86.c index 2c4ffeb551..45ef559ec6 100644 --- a/linux-user/vm86.c +++ b/linux-user/vm86.c @@ -72,7 +72,8 @@ static inline unsigned int vm_getl(uint32_t segptr, unsigned int reg16) void save_v86_state(CPUX86State *env) { - TaskState *ts = env->opaque; + CPUState *cs = CPU(x86_env_get_cpu(env)); + TaskState *ts = cs->opaque; struct target_vm86plus_struct * target_v86; if (!lock_user_struct(VERIFY_WRITE, target_v86, ts->target_v86, 0)) @@ -131,7 +132,8 @@ static inline void return_to_32bit(CPUX86State *env, int retval) static inline int set_IF(CPUX86State *env) { - TaskState *ts = env->opaque; + CPUState *cs = CPU(x86_env_get_cpu(env)); + TaskState *ts = cs->opaque; ts->v86flags |= VIF_MASK; if (ts->v86flags & VIP_MASK) { @@ -143,7 +145,8 @@ static inline int set_IF(CPUX86State *env) static inline void clear_IF(CPUX86State *env) { - TaskState *ts = env->opaque; + CPUState *cs = CPU(x86_env_get_cpu(env)); + TaskState *ts = cs->opaque; ts->v86flags &= ~VIF_MASK; } @@ -160,7 +163,8 @@ static inline void clear_AC(CPUX86State *env) static inline int set_vflags_long(unsigned long eflags, CPUX86State *env) { - TaskState *ts = env->opaque; + CPUState *cs = CPU(x86_env_get_cpu(env)); + TaskState *ts = cs->opaque; set_flags(ts->v86flags, eflags, ts->v86mask); set_flags(env->eflags, eflags, SAFE_MASK); @@ -173,7 +177,8 @@ static inline int set_vflags_long(unsigned long eflags, CPUX86State *env) static inline int set_vflags_short(unsigned short flags, CPUX86State *env) { - TaskState *ts = env->opaque; + CPUState *cs = CPU(x86_env_get_cpu(env)); + TaskState *ts = cs->opaque; set_flags(ts->v86flags, flags, ts->v86mask & 0xffff); set_flags(env->eflags, flags, SAFE_MASK); @@ -186,7 +191,8 @@ static inline int set_vflags_short(unsigned short flags, CPUX86State *env) static inline unsigned int get_vflags(CPUX86State *env) { - TaskState *ts = env->opaque; + CPUState *cs = CPU(x86_env_get_cpu(env)); + TaskState *ts = cs->opaque; unsigned int flags; flags = env->eflags & RETURN_MASK; @@ -202,7 +208,8 @@ static inline unsigned int get_vflags(CPUX86State *env) support TSS interrupt revectoring, so this code is always executed) */ static void do_int(CPUX86State *env, int intno) { - TaskState *ts = env->opaque; + CPUState *cs = CPU(x86_env_get_cpu(env)); + TaskState *ts = cs->opaque; uint32_t int_addr, segoffs, ssp; unsigned int sp; @@ -260,7 +267,8 @@ void handle_vm86_trap(CPUX86State *env, int trapno) void handle_vm86_fault(CPUX86State *env) { - TaskState *ts = env->opaque; + CPUState *cs = CPU(x86_env_get_cpu(env)); + TaskState *ts = cs->opaque; uint32_t csp, ssp; unsigned int ip, sp, newflags, newip, newcs, opcode, intno; int data32, pref_done; @@ -384,7 +392,8 @@ void handle_vm86_fault(CPUX86State *env) int do_vm86(CPUX86State *env, long subfunction, abi_ulong vm86_addr) { - TaskState *ts = env->opaque; + CPUState *cs = CPU(x86_env_get_cpu(env)); + TaskState *ts = cs->opaque; struct target_vm86plus_struct * target_v86; int ret; diff --git a/target-arm/arm-semi.c b/target-arm/arm-semi.c index ee469c49c5..ebb5235521 100644 --- a/target-arm/arm-semi.c +++ b/target-arm/arm-semi.c @@ -127,7 +127,7 @@ static void arm_semi_cb(CPUState *cs, target_ulong ret, target_ulong err) ARMCPU *cpu = ARM_CPU(cs); CPUARMState *env = &cpu->env; #ifdef CONFIG_USER_ONLY - TaskState *ts = env->opaque; + TaskState *ts = cs->opaque; #endif if (ret == (target_ulong)-1) { @@ -164,7 +164,7 @@ static void arm_semi_flen_cb(CPUState *cs, target_ulong ret, target_ulong err) cpu_memory_rw_debug(cs, env->regs[13]-64+32, (uint8_t *)&size, 4, 0); env->regs[0] = be32_to_cpu(size); #ifdef CONFIG_USER_ONLY - ((TaskState *)env->opaque)->swi_errno = err; + ((TaskState *)cs->opaque)->swi_errno = err; #else syscall_err = err; #endif @@ -183,6 +183,7 @@ static void arm_semi_flen_cb(CPUState *cs, target_ulong ret, target_ulong err) uint32_t do_arm_semihosting(CPUARMState *env) { ARMCPU *cpu = arm_env_get_cpu(env); + CPUState *cs = CPU(cpu); target_ulong args; target_ulong arg0, arg1, arg2, arg3; char * s; @@ -190,7 +191,7 @@ uint32_t do_arm_semihosting(CPUARMState *env) uint32_t ret; uint32_t len; #ifdef CONFIG_USER_ONLY - TaskState *ts = env->opaque; + TaskState *ts = cs->opaque; #else CPUARMState *ts = env; #endif @@ -554,7 +555,7 @@ uint32_t do_arm_semihosting(CPUARMState *env) exit(0); default: fprintf(stderr, "qemu: Unsupported SemiHosting SWI 0x%02x\n", nr); - cpu_dump_state(CPU(cpu), stderr, fprintf, 0); + cpu_dump_state(cs, stderr, fprintf, 0); abort(); } } diff --git a/target-m68k/m68k-semi.c b/target-m68k/m68k-semi.c index 94c4983813..2dea3cac90 100644 --- a/target-m68k/m68k-semi.c +++ b/target-m68k/m68k-semi.c @@ -428,7 +428,8 @@ void do_m68k_semihosting(CPUM68KState *env, int nr) case HOSTED_INIT_SIM: #if defined(CONFIG_USER_ONLY) { - TaskState *ts = env->opaque; + CPUState *cs = CPU(m68k_env_get_cpu(env)); + TaskState *ts = cs->opaque; /* Allocate the heap using sbrk. */ if (!ts->heap_limit) { abi_ulong ret; -- cgit 1.4.1 From ff4700b05cfb305a880762c288b88ca01c782352 Mon Sep 17 00:00:00 2001 From: Andreas Färber Date: Mon, 26 Aug 2013 18:23:18 +0200 Subject: cpu: Move watchpoint fields from CPU_COMMON to CPUState MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Andreas Färber --- cpu-exec.c | 5 +++-- exec.c | 33 ++++++++++++++++++++------------- gdbstub.c | 8 ++++---- include/exec/cpu-defs.h | 10 ---------- include/qom/cpu.h | 10 ++++++++++ linux-user/main.c | 5 +++-- target-i386/cpu.h | 2 +- target-i386/helper.c | 7 ++++--- target-i386/kvm.c | 8 ++++---- target-lm32/cpu.h | 2 +- target-lm32/helper.c | 7 ++++--- target-xtensa/cpu.h | 2 +- target-xtensa/helper.c | 8 +++++--- 13 files changed, 60 insertions(+), 47 deletions(-) (limited to 'include/exec') diff --git a/cpu-exec.c b/cpu-exec.c index 798dc084d9..d7c21d35e5 100644 --- a/cpu-exec.c +++ b/cpu-exec.c @@ -200,10 +200,11 @@ void cpu_set_debug_excp_handler(CPUDebugExcpHandler *handler) static void cpu_handle_debug_exception(CPUArchState *env) { + CPUState *cpu = ENV_GET_CPU(env); CPUWatchpoint *wp; - if (!env->watchpoint_hit) { - QTAILQ_FOREACH(wp, &env->watchpoints, entry) { + if (!cpu->watchpoint_hit) { + QTAILQ_FOREACH(wp, &cpu->watchpoints, entry) { wp->flags &= ~BP_WATCHPOINT_HIT; } } diff --git a/exec.c b/exec.c index 26ed9ccd0c..ee5eff7734 100644 --- a/exec.c +++ b/exec.c @@ -485,7 +485,7 @@ void cpu_exec_init(CPUArchState *env) cpu->cpu_index = cpu_index; cpu->numa_node = 0; QTAILQ_INIT(&env->breakpoints); - QTAILQ_INIT(&env->watchpoints); + QTAILQ_INIT(&cpu->watchpoints); #ifndef CONFIG_USER_ONLY cpu->as = &address_space_memory; cpu->thread_id = qemu_get_thread_id(); @@ -542,6 +542,7 @@ int cpu_watchpoint_insert(CPUArchState *env, target_ulong addr, target_ulong len int cpu_watchpoint_insert(CPUArchState *env, target_ulong addr, target_ulong len, int flags, CPUWatchpoint **watchpoint) { + CPUState *cpu = ENV_GET_CPU(env); target_ulong len_mask = ~(len - 1); CPUWatchpoint *wp; @@ -559,10 +560,11 @@ int cpu_watchpoint_insert(CPUArchState *env, target_ulong addr, target_ulong len wp->flags = flags; /* keep all GDB-injected watchpoints in front */ - if (flags & BP_GDB) - QTAILQ_INSERT_HEAD(&env->watchpoints, wp, entry); - else - QTAILQ_INSERT_TAIL(&env->watchpoints, wp, entry); + if (flags & BP_GDB) { + QTAILQ_INSERT_HEAD(&cpu->watchpoints, wp, entry); + } else { + QTAILQ_INSERT_TAIL(&cpu->watchpoints, wp, entry); + } tlb_flush_page(env, addr); @@ -575,10 +577,11 @@ int cpu_watchpoint_insert(CPUArchState *env, target_ulong addr, target_ulong len int cpu_watchpoint_remove(CPUArchState *env, target_ulong addr, target_ulong len, int flags) { + CPUState *cpu = ENV_GET_CPU(env); target_ulong len_mask = ~(len - 1); CPUWatchpoint *wp; - QTAILQ_FOREACH(wp, &env->watchpoints, entry) { + QTAILQ_FOREACH(wp, &cpu->watchpoints, entry) { if (addr == wp->vaddr && len_mask == wp->len_mask && flags == (wp->flags & ~BP_WATCHPOINT_HIT)) { cpu_watchpoint_remove_by_ref(env, wp); @@ -591,7 +594,9 @@ int cpu_watchpoint_remove(CPUArchState *env, target_ulong addr, target_ulong len /* Remove a specific watchpoint by reference. */ void cpu_watchpoint_remove_by_ref(CPUArchState *env, CPUWatchpoint *watchpoint) { - QTAILQ_REMOVE(&env->watchpoints, watchpoint, entry); + CPUState *cpu = ENV_GET_CPU(env); + + QTAILQ_REMOVE(&cpu->watchpoints, watchpoint, entry); tlb_flush_page(env, watchpoint->vaddr); @@ -601,9 +606,10 @@ void cpu_watchpoint_remove_by_ref(CPUArchState *env, CPUWatchpoint *watchpoint) /* Remove all matching watchpoints. */ void cpu_watchpoint_remove_all(CPUArchState *env, int mask) { + CPUState *cpu = ENV_GET_CPU(env); CPUWatchpoint *wp, *next; - QTAILQ_FOREACH_SAFE(wp, &env->watchpoints, entry, next) { + QTAILQ_FOREACH_SAFE(wp, &cpu->watchpoints, entry, next) { if (wp->flags & mask) cpu_watchpoint_remove_by_ref(env, wp); } @@ -799,6 +805,7 @@ hwaddr memory_region_section_get_iotlb(CPUArchState *env, int prot, target_ulong *address) { + CPUState *cpu = ENV_GET_CPU(env); hwaddr iotlb; CPUWatchpoint *wp; @@ -818,7 +825,7 @@ hwaddr memory_region_section_get_iotlb(CPUArchState *env, /* Make accesses to pages with watchpoints go via the watchpoint trap routines. */ - QTAILQ_FOREACH(wp, &env->watchpoints, entry) { + QTAILQ_FOREACH(wp, &cpu->watchpoints, entry) { if (vaddr == (wp->vaddr & TARGET_PAGE_MASK)) { /* Avoid trapping reads of pages with a write breakpoint. */ if ((prot & PAGE_WRITE) || (wp->flags & BP_MEM_READ)) { @@ -1579,7 +1586,7 @@ static void check_watchpoint(int offset, int len_mask, int flags) CPUWatchpoint *wp; int cpu_flags; - if (env->watchpoint_hit) { + if (cpu->watchpoint_hit) { /* We re-entered the check after replacing the TB. Now raise * the debug interrupt so that is will trigger after the * current instruction. */ @@ -1587,12 +1594,12 @@ static void check_watchpoint(int offset, int len_mask, int flags) return; } vaddr = (cpu->mem_io_vaddr & TARGET_PAGE_MASK) + offset; - QTAILQ_FOREACH(wp, &env->watchpoints, entry) { + QTAILQ_FOREACH(wp, &cpu->watchpoints, entry) { if ((vaddr == (wp->vaddr & len_mask) || (vaddr & wp->len_mask) == wp->vaddr) && (wp->flags & flags)) { wp->flags |= BP_WATCHPOINT_HIT; - if (!env->watchpoint_hit) { - env->watchpoint_hit = wp; + if (!cpu->watchpoint_hit) { + cpu->watchpoint_hit = wp; tb_check_watchpoint(env); if (wp->flags & BP_STOP_BEFORE_ACCESS) { cpu->exception_index = EXCP_DEBUG; diff --git a/gdbstub.c b/gdbstub.c index c5ab73fb1d..0176b3f80e 100644 --- a/gdbstub.c +++ b/gdbstub.c @@ -1204,8 +1204,8 @@ static void gdb_vm_state_change(void *opaque, int running, RunState state) } switch (state) { case RUN_STATE_DEBUG: - if (env->watchpoint_hit) { - switch (env->watchpoint_hit->flags & BP_MEM_ACCESS) { + if (cpu->watchpoint_hit) { + switch (cpu->watchpoint_hit->flags & BP_MEM_ACCESS) { case BP_MEM_READ: type = "r"; break; @@ -1219,8 +1219,8 @@ static void gdb_vm_state_change(void *opaque, int running, RunState state) snprintf(buf, sizeof(buf), "T%02xthread:%02x;%swatch:" TARGET_FMT_lx ";", GDB_SIGNAL_TRAP, cpu_index(cpu), type, - env->watchpoint_hit->vaddr); - env->watchpoint_hit = NULL; + (target_ulong)cpu->watchpoint_hit->vaddr); + cpu->watchpoint_hit = NULL; goto send_packet; } tb_flush(env); diff --git a/include/exec/cpu-defs.h b/include/exec/cpu-defs.h index 8af85476fc..31aac691c5 100644 --- a/include/exec/cpu-defs.h +++ b/include/exec/cpu-defs.h @@ -120,13 +120,6 @@ typedef struct CPUBreakpoint { QTAILQ_ENTRY(CPUBreakpoint) entry; } CPUBreakpoint; -typedef struct CPUWatchpoint { - target_ulong vaddr; - target_ulong len_mask; - int flags; /* BP_* */ - QTAILQ_ENTRY(CPUWatchpoint) entry; -} CPUWatchpoint; - #define CPU_TEMP_BUF_NLONGS 128 #define CPU_COMMON \ /* soft mmu support */ \ @@ -135,8 +128,5 @@ typedef struct CPUWatchpoint { /* from this point: preserved by CPU reset */ \ /* ice debug support */ \ QTAILQ_HEAD(breakpoints_head, CPUBreakpoint) breakpoints; \ - \ - QTAILQ_HEAD(watchpoints_head, CPUWatchpoint) watchpoints; \ - CPUWatchpoint *watchpoint_hit; \ #endif diff --git a/include/qom/cpu.h b/include/qom/cpu.h index 4d1ea35ca4..c7420e070b 100644 --- a/include/qom/cpu.h +++ b/include/qom/cpu.h @@ -151,6 +151,13 @@ typedef struct icount_decr_u16 { } icount_decr_u16; #endif +typedef struct CPUWatchpoint { + vaddr vaddr; + vaddr len_mask; + int flags; /* BP_* */ + QTAILQ_ENTRY(CPUWatchpoint) entry; +} CPUWatchpoint; + struct KVMState; struct kvm_run; @@ -231,6 +238,9 @@ struct CPUState { int gdb_num_g_regs; QTAILQ_ENTRY(CPUState) node; + QTAILQ_HEAD(watchpoints_head, CPUWatchpoint) watchpoints; + CPUWatchpoint *watchpoint_hit; + void *opaque; /* In order to avoid passing too many arguments to the MMIO helpers, diff --git a/linux-user/main.c b/linux-user/main.c index 6e62b8babd..5a06192ec4 100644 --- a/linux-user/main.c +++ b/linux-user/main.c @@ -3435,6 +3435,7 @@ void init_task_state(TaskState *ts) CPUArchState *cpu_copy(CPUArchState *env) { + CPUState *cpu = ENV_GET_CPU(env); CPUArchState *new_env = cpu_init(cpu_model); #if defined(TARGET_HAS_ICE) CPUBreakpoint *bp; @@ -3450,12 +3451,12 @@ CPUArchState *cpu_copy(CPUArchState *env) Note: Once we support ptrace with hw-debug register access, make sure BP_CPU break/watchpoints are handled correctly on clone. */ QTAILQ_INIT(&env->breakpoints); - QTAILQ_INIT(&env->watchpoints); + QTAILQ_INIT(&cpu->watchpoints); #if defined(TARGET_HAS_ICE) QTAILQ_FOREACH(bp, &env->breakpoints, entry) { cpu_breakpoint_insert(new_env, bp->pc, bp->flags, NULL); } - QTAILQ_FOREACH(wp, &env->watchpoints, entry) { + QTAILQ_FOREACH(wp, &cpu->watchpoints, entry) { cpu_watchpoint_insert(new_env, wp->vaddr, (~wp->len_mask) + 1, wp->flags, NULL); } diff --git a/target-i386/cpu.h b/target-i386/cpu.h index 62641af77e..906018757d 100644 --- a/target-i386/cpu.h +++ b/target-i386/cpu.h @@ -876,7 +876,7 @@ typedef struct CPUX86State { target_ulong dr[8]; /* debug registers */ union { CPUBreakpoint *cpu_breakpoint[4]; - CPUWatchpoint *cpu_watchpoint[4]; + struct CPUWatchpoint *cpu_watchpoint[4]; }; /* break/watchpoints for dr[0..3] */ uint32_t smbase; int old_exception; /* exception in flight */ diff --git a/target-i386/helper.c b/target-i386/helper.c index 6d9bd71a3a..bd8da20946 100644 --- a/target-i386/helper.c +++ b/target-i386/helper.c @@ -1088,11 +1088,12 @@ bool check_hw_breakpoints(CPUX86State *env, bool force_dr6_update) void breakpoint_handler(CPUX86State *env) { + CPUState *cs = CPU(x86_env_get_cpu(env)); CPUBreakpoint *bp; - if (env->watchpoint_hit) { - if (env->watchpoint_hit->flags & BP_CPU) { - env->watchpoint_hit = NULL; + if (cs->watchpoint_hit) { + if (cs->watchpoint_hit->flags & BP_CPU) { + cs->watchpoint_hit = NULL; if (check_hw_breakpoints(env, false)) { raise_exception(env, EXCP01_DB); } else { diff --git a/target-i386/kvm.c b/target-i386/kvm.c index e555040a97..7a295f6f20 100644 --- a/target-i386/kvm.c +++ b/target-i386/kvm.c @@ -2277,13 +2277,13 @@ static int kvm_handle_debug(X86CPU *cpu, break; case 0x1: ret = EXCP_DEBUG; - env->watchpoint_hit = &hw_watchpoint; + cs->watchpoint_hit = &hw_watchpoint; hw_watchpoint.vaddr = hw_breakpoint[n].addr; hw_watchpoint.flags = BP_MEM_WRITE; break; case 0x3: ret = EXCP_DEBUG; - env->watchpoint_hit = &hw_watchpoint; + cs->watchpoint_hit = &hw_watchpoint; hw_watchpoint.vaddr = hw_breakpoint[n].addr; hw_watchpoint.flags = BP_MEM_ACCESS; break; @@ -2291,11 +2291,11 @@ static int kvm_handle_debug(X86CPU *cpu, } } } - } else if (kvm_find_sw_breakpoint(CPU(cpu), arch_info->pc)) { + } else if (kvm_find_sw_breakpoint(cs, arch_info->pc)) { ret = EXCP_DEBUG; } if (ret == 0) { - cpu_synchronize_state(CPU(cpu)); + cpu_synchronize_state(cs); assert(env->exception_injected == -1); /* pass to guest */ diff --git a/target-lm32/cpu.h b/target-lm32/cpu.h index b94d9b007e..d50726bce7 100644 --- a/target-lm32/cpu.h +++ b/target-lm32/cpu.h @@ -167,7 +167,7 @@ struct CPULM32State { uint32_t wp[4]; /* watchpoints */ CPUBreakpoint * cpu_breakpoint[4]; - CPUWatchpoint * cpu_watchpoint[4]; + struct CPUWatchpoint *cpu_watchpoint[4]; CPU_COMMON diff --git a/target-lm32/helper.c b/target-lm32/helper.c index e5536c0ecb..67ba278e27 100644 --- a/target-lm32/helper.c +++ b/target-lm32/helper.c @@ -118,11 +118,12 @@ static bool check_watchpoints(CPULM32State *env) void lm32_debug_excp_handler(CPULM32State *env) { + CPUState *cs = CPU(lm32_env_get_cpu(env)); CPUBreakpoint *bp; - if (env->watchpoint_hit) { - if (env->watchpoint_hit->flags & BP_CPU) { - env->watchpoint_hit = NULL; + if (cs->watchpoint_hit) { + if (cs->watchpoint_hit->flags & BP_CPU) { + cs->watchpoint_hit = NULL; if (check_watchpoints(env)) { raise_exception(env, EXCP_WATCHPOINT); } else { diff --git a/target-xtensa/cpu.h b/target-xtensa/cpu.h index 4bae693c6d..e210bacdff 100644 --- a/target-xtensa/cpu.h +++ b/target-xtensa/cpu.h @@ -359,7 +359,7 @@ typedef struct CPUXtensaState { int exception_taken; /* Watchpoints for DBREAK registers */ - CPUWatchpoint *cpu_watchpoint[MAX_NDBREAK]; + struct CPUWatchpoint *cpu_watchpoint[MAX_NDBREAK]; CPU_COMMON } CPUXtensaState; diff --git a/target-xtensa/helper.c b/target-xtensa/helper.c index 259878837f..8a9cb0a825 100644 --- a/target-xtensa/helper.c +++ b/target-xtensa/helper.c @@ -81,11 +81,13 @@ static uint32_t check_hw_breakpoints(CPUXtensaState *env) void xtensa_breakpoint_handler(CPUXtensaState *env) { - if (env->watchpoint_hit) { - if (env->watchpoint_hit->flags & BP_CPU) { + CPUState *cs = CPU(xtensa_env_get_cpu(env)); + + if (cs->watchpoint_hit) { + if (cs->watchpoint_hit->flags & BP_CPU) { uint32_t cause; - env->watchpoint_hit = NULL; + cs->watchpoint_hit = NULL; cause = check_hw_breakpoints(env); if (cause) { debug_exception_env(env, cause); -- cgit 1.4.1 From f0c3c505a8ec1a948006b3a16a35864a2270a84b Mon Sep 17 00:00:00 2001 From: Andreas Färber Date: Mon, 26 Aug 2013 21:22:53 +0200 Subject: cpu: Move breakpoints field from CPU_COMMON to CPUState MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Most targets were using offsetof(CPUFooState, breakpoints) to determine how much of CPUFooState to clear on reset. Use the next field after CPU_COMMON instead, if any, or sizeof(CPUFooState) otherwise. Signed-off-by: Andreas Färber --- exec.c | 21 +++++++++++++-------- include/exec/cpu-defs.h | 10 ---------- include/qom/cpu.h | 9 +++++++++ linux-user/main.c | 4 ++-- target-alpha/translate.c | 4 ++-- target-arm/cpu.c | 2 +- target-arm/translate-a64.c | 4 ++-- target-arm/translate.c | 4 ++-- target-cris/cpu.c | 2 +- target-cris/cpu.h | 4 ++-- target-cris/translate.c | 5 +++-- target-i386/cpu.c | 2 +- target-i386/cpu.h | 3 ++- target-i386/helper.c | 3 ++- target-i386/translate.c | 4 ++-- target-lm32/cpu.c | 2 +- target-lm32/cpu.h | 3 ++- target-lm32/helper.c | 2 +- target-lm32/translate.c | 5 +++-- target-m68k/cpu.c | 2 +- target-m68k/cpu.h | 1 + target-m68k/translate.c | 4 ++-- target-microblaze/cpu.c | 2 +- target-microblaze/translate.c | 5 +++-- target-mips/cpu.c | 2 +- target-mips/cpu.h | 1 + target-mips/translate.c | 4 ++-- target-moxie/cpu.c | 2 +- target-moxie/translate.c | 4 ++-- target-openrisc/cpu.c | 6 +++++- target-openrisc/cpu.h | 1 + target-openrisc/translate.c | 5 +++-- target-ppc/translate.c | 4 ++-- target-s390x/cpu.c | 4 ++-- target-s390x/translate.c | 4 ++-- target-sh4/cpu.c | 2 +- target-sh4/cpu.h | 1 + target-sh4/translate.c | 4 ++-- target-sparc/cpu.c | 2 +- target-sparc/cpu.h | 1 + target-sparc/translate.c | 4 ++-- target-unicore32/translate.c | 4 ++-- target-xtensa/translate.c | 5 +++-- 43 files changed, 94 insertions(+), 73 deletions(-) (limited to 'include/exec') diff --git a/exec.c b/exec.c index ee5eff7734..6d9e13a0a6 100644 --- a/exec.c +++ b/exec.c @@ -484,7 +484,7 @@ void cpu_exec_init(CPUArchState *env) } cpu->cpu_index = cpu_index; cpu->numa_node = 0; - QTAILQ_INIT(&env->breakpoints); + QTAILQ_INIT(&cpu->breakpoints); QTAILQ_INIT(&cpu->watchpoints); #ifndef CONFIG_USER_ONLY cpu->as = &address_space_memory; @@ -621,6 +621,7 @@ int cpu_breakpoint_insert(CPUArchState *env, target_ulong pc, int flags, CPUBreakpoint **breakpoint) { #if defined(TARGET_HAS_ICE) + CPUState *cpu = ENV_GET_CPU(env); CPUBreakpoint *bp; bp = g_malloc(sizeof(*bp)); @@ -630,12 +631,12 @@ int cpu_breakpoint_insert(CPUArchState *env, target_ulong pc, int flags, /* keep all GDB-injected breakpoints in front */ if (flags & BP_GDB) { - QTAILQ_INSERT_HEAD(&env->breakpoints, bp, entry); + QTAILQ_INSERT_HEAD(&cpu->breakpoints, bp, entry); } else { - QTAILQ_INSERT_TAIL(&env->breakpoints, bp, entry); + QTAILQ_INSERT_TAIL(&cpu->breakpoints, bp, entry); } - breakpoint_invalidate(ENV_GET_CPU(env), pc); + breakpoint_invalidate(cpu, pc); if (breakpoint) { *breakpoint = bp; @@ -650,9 +651,10 @@ int cpu_breakpoint_insert(CPUArchState *env, target_ulong pc, int flags, int cpu_breakpoint_remove(CPUArchState *env, target_ulong pc, int flags) { #if defined(TARGET_HAS_ICE) + CPUState *cpu = ENV_GET_CPU(env); CPUBreakpoint *bp; - QTAILQ_FOREACH(bp, &env->breakpoints, entry) { + QTAILQ_FOREACH(bp, &cpu->breakpoints, entry) { if (bp->pc == pc && bp->flags == flags) { cpu_breakpoint_remove_by_ref(env, bp); return 0; @@ -668,9 +670,11 @@ int cpu_breakpoint_remove(CPUArchState *env, target_ulong pc, int flags) void cpu_breakpoint_remove_by_ref(CPUArchState *env, CPUBreakpoint *breakpoint) { #if defined(TARGET_HAS_ICE) - QTAILQ_REMOVE(&env->breakpoints, breakpoint, entry); + CPUState *cpu = ENV_GET_CPU(env); - breakpoint_invalidate(ENV_GET_CPU(env), breakpoint->pc); + QTAILQ_REMOVE(&cpu->breakpoints, breakpoint, entry); + + breakpoint_invalidate(cpu, breakpoint->pc); g_free(breakpoint); #endif @@ -680,9 +684,10 @@ void cpu_breakpoint_remove_by_ref(CPUArchState *env, CPUBreakpoint *breakpoint) void cpu_breakpoint_remove_all(CPUArchState *env, int mask) { #if defined(TARGET_HAS_ICE) + CPUState *cpu = ENV_GET_CPU(env); CPUBreakpoint *bp, *next; - QTAILQ_FOREACH_SAFE(bp, &env->breakpoints, entry, next) { + QTAILQ_FOREACH_SAFE(bp, &cpu->breakpoints, entry, next) { if (bp->flags & mask) cpu_breakpoint_remove_by_ref(env, bp); } diff --git a/include/exec/cpu-defs.h b/include/exec/cpu-defs.h index 31aac691c5..2dd6206d4a 100644 --- a/include/exec/cpu-defs.h +++ b/include/exec/cpu-defs.h @@ -114,19 +114,9 @@ QEMU_BUILD_BUG_ON(sizeof(CPUTLBEntry) != (1 << CPU_TLB_ENTRY_BITS)); #endif -typedef struct CPUBreakpoint { - target_ulong pc; - int flags; /* BP_* */ - QTAILQ_ENTRY(CPUBreakpoint) entry; -} CPUBreakpoint; - #define CPU_TEMP_BUF_NLONGS 128 #define CPU_COMMON \ /* soft mmu support */ \ CPU_COMMON_TLB \ - \ - /* from this point: preserved by CPU reset */ \ - /* ice debug support */ \ - QTAILQ_HEAD(breakpoints_head, CPUBreakpoint) breakpoints; \ #endif diff --git a/include/qom/cpu.h b/include/qom/cpu.h index c7420e070b..3bbda08eac 100644 --- a/include/qom/cpu.h +++ b/include/qom/cpu.h @@ -151,6 +151,12 @@ typedef struct icount_decr_u16 { } icount_decr_u16; #endif +typedef struct CPUBreakpoint { + vaddr pc; + int flags; /* BP_* */ + QTAILQ_ENTRY(CPUBreakpoint) entry; +} CPUBreakpoint; + typedef struct CPUWatchpoint { vaddr vaddr; vaddr len_mask; @@ -238,6 +244,9 @@ struct CPUState { int gdb_num_g_regs; QTAILQ_ENTRY(CPUState) node; + /* ice debug support */ + QTAILQ_HEAD(breakpoints_head, CPUBreakpoint) breakpoints; + QTAILQ_HEAD(watchpoints_head, CPUWatchpoint) watchpoints; CPUWatchpoint *watchpoint_hit; diff --git a/linux-user/main.c b/linux-user/main.c index 5a06192ec4..dbc04b7d0f 100644 --- a/linux-user/main.c +++ b/linux-user/main.c @@ -3450,10 +3450,10 @@ CPUArchState *cpu_copy(CPUArchState *env) /* Clone all break/watchpoints. Note: Once we support ptrace with hw-debug register access, make sure BP_CPU break/watchpoints are handled correctly on clone. */ - QTAILQ_INIT(&env->breakpoints); + QTAILQ_INIT(&cpu->breakpoints); QTAILQ_INIT(&cpu->watchpoints); #if defined(TARGET_HAS_ICE) - QTAILQ_FOREACH(bp, &env->breakpoints, entry) { + QTAILQ_FOREACH(bp, &cpu->breakpoints, entry) { cpu_breakpoint_insert(new_env, bp->pc, bp->flags, NULL); } QTAILQ_FOREACH(wp, &cpu->watchpoints, entry) { diff --git a/target-alpha/translate.c b/target-alpha/translate.c index 4c94bed704..a9ef1a7507 100644 --- a/target-alpha/translate.c +++ b/target-alpha/translate.c @@ -3463,8 +3463,8 @@ static inline void gen_intermediate_code_internal(AlphaCPU *cpu, gen_tb_start(); do { - if (unlikely(!QTAILQ_EMPTY(&env->breakpoints))) { - QTAILQ_FOREACH(bp, &env->breakpoints, entry) { + if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) { + QTAILQ_FOREACH(bp, &cs->breakpoints, entry) { if (bp->pc == ctx.pc) { gen_excp(&ctx, EXCP_DEBUG, 0); break; diff --git a/target-arm/cpu.c b/target-arm/cpu.c index be17d72537..ecd0b7ecde 100644 --- a/target-arm/cpu.c +++ b/target-arm/cpu.c @@ -82,7 +82,7 @@ static void arm_cpu_reset(CPUState *s) acc->parent_reset(s); - memset(env, 0, offsetof(CPUARMState, breakpoints)); + memset(env, 0, offsetof(CPUARMState, features)); g_hash_table_foreach(cpu->cp_regs, cp_reg_reset, cpu); env->vfp.xregs[ARM_VFP_FPSID] = cpu->reset_fpsid; env->vfp.xregs[ARM_VFP_MVFR0] = cpu->mvfr0; diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c index 37e05e81f7..2fd9113628 100644 --- a/target-arm/translate-a64.c +++ b/target-arm/translate-a64.c @@ -9061,8 +9061,8 @@ void gen_intermediate_code_internal_a64(ARMCPU *cpu, tcg_clear_temp_count(); do { - if (unlikely(!QTAILQ_EMPTY(&env->breakpoints))) { - QTAILQ_FOREACH(bp, &env->breakpoints, entry) { + if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) { + QTAILQ_FOREACH(bp, &cs->breakpoints, entry) { if (bp->pc == dc->pc) { gen_exception_insn(dc, 0, EXCP_DEBUG); /* Advance PC so that clearing the breakpoint will diff --git a/target-arm/translate.c b/target-arm/translate.c index df259debcc..2f02c183a7 100644 --- a/target-arm/translate.c +++ b/target-arm/translate.c @@ -10733,8 +10733,8 @@ static inline void gen_intermediate_code_internal(ARMCPU *cpu, } #endif - if (unlikely(!QTAILQ_EMPTY(&env->breakpoints))) { - QTAILQ_FOREACH(bp, &env->breakpoints, entry) { + if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) { + QTAILQ_FOREACH(bp, &cs->breakpoints, entry) { if (bp->pc == dc->pc) { gen_exception_insn(dc, 0, EXCP_DEBUG); /* Advance PC so that clearing the breakpoint will diff --git a/target-cris/cpu.c b/target-cris/cpu.c index ff27e7f773..95b6a8889b 100644 --- a/target-cris/cpu.c +++ b/target-cris/cpu.c @@ -49,7 +49,7 @@ static void cris_cpu_reset(CPUState *s) ccc->parent_reset(s); vr = env->pregs[PR_VR]; - memset(env, 0, offsetof(CPUCRISState, breakpoints)); + memset(env, 0, offsetof(CPUCRISState, load_info)); env->pregs[PR_VR] = vr; tlb_flush(env, 1); diff --git a/target-cris/cpu.h b/target-cris/cpu.h index 6cc0616523..b88c147518 100644 --- a/target-cris/cpu.h +++ b/target-cris/cpu.h @@ -171,8 +171,8 @@ typedef struct CPUCRISState { CPU_COMMON - /* Members after CPU_COMMON are preserved across resets. */ - void *load_info; + /* Members from load_info on are preserved across resets. */ + void *load_info; } CPUCRISState; #include "cpu-qom.h" diff --git a/target-cris/translate.c b/target-cris/translate.c index f990d591c7..7e70940c9b 100644 --- a/target-cris/translate.c +++ b/target-cris/translate.c @@ -3089,10 +3089,11 @@ static unsigned int crisv32_decoder(CPUCRISState *env, DisasContext *dc) static void check_breakpoint(CPUCRISState *env, DisasContext *dc) { + CPUState *cs = CPU(cris_env_get_cpu(env)); CPUBreakpoint *bp; - if (unlikely(!QTAILQ_EMPTY(&env->breakpoints))) { - QTAILQ_FOREACH(bp, &env->breakpoints, entry) { + if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) { + QTAILQ_FOREACH(bp, &cs->breakpoints, entry) { if (bp->pc == dc->pc) { cris_evaluate_flags(dc); tcg_gen_movi_tl(env_pc, dc->pc); diff --git a/target-i386/cpu.c b/target-i386/cpu.c index 63ba2194cb..fab0f55735 100644 --- a/target-i386/cpu.c +++ b/target-i386/cpu.c @@ -2410,7 +2410,7 @@ static void x86_cpu_reset(CPUState *s) xcc->parent_reset(s); - memset(env, 0, offsetof(CPUX86State, breakpoints)); + memset(env, 0, offsetof(CPUX86State, pat)); tlb_flush(env, 1); diff --git a/target-i386/cpu.h b/target-i386/cpu.h index 906018757d..4d1374c6cc 100644 --- a/target-i386/cpu.h +++ b/target-i386/cpu.h @@ -875,7 +875,7 @@ typedef struct CPUX86State { target_ulong exception_next_eip; target_ulong dr[8]; /* debug registers */ union { - CPUBreakpoint *cpu_breakpoint[4]; + struct CPUBreakpoint *cpu_breakpoint[4]; struct CPUWatchpoint *cpu_watchpoint[4]; }; /* break/watchpoints for dr[0..3] */ uint32_t smbase; @@ -887,6 +887,7 @@ typedef struct CPUX86State { CPU_COMMON + /* Fields from here on are preserved across CPU reset. */ uint64_t pat; /* processor features (e.g. for CPUID insn) */ diff --git a/target-i386/helper.c b/target-i386/helper.c index bd8da20946..59736d7a4f 100644 --- a/target-i386/helper.c +++ b/target-i386/helper.c @@ -1101,7 +1101,7 @@ void breakpoint_handler(CPUX86State *env) } } } else { - QTAILQ_FOREACH(bp, &env->breakpoints, entry) + QTAILQ_FOREACH(bp, &cs->breakpoints, entry) { if (bp->pc == env->eip) { if (bp->flags & BP_CPU) { check_hw_breakpoints(env, true); @@ -1109,6 +1109,7 @@ void breakpoint_handler(CPUX86State *env) } break; } + } } } diff --git a/target-i386/translate.c b/target-i386/translate.c index 707ebd5ca0..02625e31c2 100644 --- a/target-i386/translate.c +++ b/target-i386/translate.c @@ -7965,8 +7965,8 @@ static inline void gen_intermediate_code_internal(X86CPU *cpu, gen_tb_start(); for(;;) { - if (unlikely(!QTAILQ_EMPTY(&env->breakpoints))) { - QTAILQ_FOREACH(bp, &env->breakpoints, entry) { + if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) { + QTAILQ_FOREACH(bp, &cs->breakpoints, entry) { if (bp->pc == pc_ptr && !((bp->flags & BP_CPU) && (tb->flags & HF_RF_MASK))) { gen_debug(dc, pc_ptr - dc->cs_base); diff --git a/target-lm32/cpu.c b/target-lm32/cpu.c index daec499502..d0c66bc0f5 100644 --- a/target-lm32/cpu.c +++ b/target-lm32/cpu.c @@ -125,7 +125,7 @@ static void lm32_cpu_reset(CPUState *s) lcc->parent_reset(s); /* reset cpu state */ - memset(env, 0, offsetof(CPULM32State, breakpoints)); + memset(env, 0, offsetof(CPULM32State, eba)); lm32_cpu_init_cfg_reg(cpu); tlb_flush(env, 1); diff --git a/target-lm32/cpu.h b/target-lm32/cpu.h index d50726bce7..24bde78502 100644 --- a/target-lm32/cpu.h +++ b/target-lm32/cpu.h @@ -166,11 +166,12 @@ struct CPULM32State { uint32_t bp[4]; /* breakpoints */ uint32_t wp[4]; /* watchpoints */ - CPUBreakpoint * cpu_breakpoint[4]; + struct CPUBreakpoint *cpu_breakpoint[4]; struct CPUWatchpoint *cpu_watchpoint[4]; CPU_COMMON + /* Fields from here on are preserved across CPU reset. */ uint32_t eba; /* exception base address */ uint32_t deba; /* debug exception base address */ diff --git a/target-lm32/helper.c b/target-lm32/helper.c index 67ba278e27..eadc7277a7 100644 --- a/target-lm32/helper.c +++ b/target-lm32/helper.c @@ -131,7 +131,7 @@ void lm32_debug_excp_handler(CPULM32State *env) } } } else { - QTAILQ_FOREACH(bp, &env->breakpoints, entry) { + QTAILQ_FOREACH(bp, &cs->breakpoints, entry) { if (bp->pc == env->pc) { if (bp->flags & BP_CPU) { raise_exception(env, EXCP_BREAKPOINT); diff --git a/target-lm32/translate.c b/target-lm32/translate.c index 80bffc7b27..c8abd1f27e 100644 --- a/target-lm32/translate.c +++ b/target-lm32/translate.c @@ -1037,10 +1037,11 @@ static inline void decode(DisasContext *dc, uint32_t ir) static void check_breakpoint(CPULM32State *env, DisasContext *dc) { + CPUState *cs = CPU(lm32_env_get_cpu(env)); CPUBreakpoint *bp; - if (unlikely(!QTAILQ_EMPTY(&env->breakpoints))) { - QTAILQ_FOREACH(bp, &env->breakpoints, entry) { + if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) { + QTAILQ_FOREACH(bp, &cs->breakpoints, entry) { if (bp->pc == dc->pc) { tcg_gen_movi_tl(cpu_pc, dc->pc); t_gen_raise_exception(dc, EXCP_DEBUG); diff --git a/target-m68k/cpu.c b/target-m68k/cpu.c index 46601dcd5d..a88da20b46 100644 --- a/target-m68k/cpu.c +++ b/target-m68k/cpu.c @@ -49,7 +49,7 @@ static void m68k_cpu_reset(CPUState *s) mcc->parent_reset(s); - memset(env, 0, offsetof(CPUM68KState, breakpoints)); + memset(env, 0, offsetof(CPUM68KState, features)); #if !defined(CONFIG_USER_ONLY) env->sr = 0x2700; #endif diff --git a/target-m68k/cpu.h b/target-m68k/cpu.h index dd1794feac..6e4001d523 100644 --- a/target-m68k/cpu.h +++ b/target-m68k/cpu.h @@ -110,6 +110,7 @@ typedef struct CPUM68KState { CPU_COMMON + /* Fields from here on are preserved across CPU reset. */ uint32_t features; } CPUM68KState; diff --git a/target-m68k/translate.c b/target-m68k/translate.c index 4f06443532..a0e2f19e15 100644 --- a/target-m68k/translate.c +++ b/target-m68k/translate.c @@ -3003,8 +3003,8 @@ gen_intermediate_code_internal(M68kCPU *cpu, TranslationBlock *tb, do { pc_offset = dc->pc - pc_start; gen_throws_exception = NULL; - if (unlikely(!QTAILQ_EMPTY(&env->breakpoints))) { - QTAILQ_FOREACH(bp, &env->breakpoints, entry) { + if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) { + QTAILQ_FOREACH(bp, &cs->breakpoints, entry) { if (bp->pc == dc->pc) { gen_exception(dc, dc->pc, EXCP_DEBUG); dc->is_jmp = DISAS_JUMP; diff --git a/target-microblaze/cpu.c b/target-microblaze/cpu.c index 86ec25811e..3177fe6d12 100644 --- a/target-microblaze/cpu.c +++ b/target-microblaze/cpu.c @@ -63,7 +63,7 @@ static void mb_cpu_reset(CPUState *s) mcc->parent_reset(s); - memset(env, 0, offsetof(CPUMBState, breakpoints)); + memset(env, 0, sizeof(CPUMBState)); env->res_addr = RES_ADDR_NONE; tlb_flush(env, 1); diff --git a/target-microblaze/translate.c b/target-microblaze/translate.c index 270138c6d2..fbd6951d1a 100644 --- a/target-microblaze/translate.c +++ b/target-microblaze/translate.c @@ -1660,10 +1660,11 @@ static inline void decode(DisasContext *dc, uint32_t ir) static void check_breakpoint(CPUMBState *env, DisasContext *dc) { + CPUState *cs = CPU(mb_env_get_cpu(env)); CPUBreakpoint *bp; - if (unlikely(!QTAILQ_EMPTY(&env->breakpoints))) { - QTAILQ_FOREACH(bp, &env->breakpoints, entry) { + if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) { + QTAILQ_FOREACH(bp, &cs->breakpoints, entry) { if (bp->pc == dc->pc) { t_gen_raise_exception(dc, EXCP_DEBUG); dc->is_jmp = DISAS_UPDATE; diff --git a/target-mips/cpu.c b/target-mips/cpu.c index 8c304ac832..cf4d856d6b 100644 --- a/target-mips/cpu.c +++ b/target-mips/cpu.c @@ -83,7 +83,7 @@ static void mips_cpu_reset(CPUState *s) mcc->parent_reset(s); - memset(env, 0, offsetof(CPUMIPSState, breakpoints)); + memset(env, 0, offsetof(CPUMIPSState, mvp)); tlb_flush(env, 1); cpu_state_reset(env); diff --git a/target-mips/cpu.h b/target-mips/cpu.h index a1d85efea1..3ba3229e66 100644 --- a/target-mips/cpu.h +++ b/target-mips/cpu.h @@ -482,6 +482,7 @@ struct CPUMIPSState { CPU_COMMON + /* Fields from here on are preserved across CPU reset. */ CPUMIPSMVPContext *mvp; #if !defined(CONFIG_USER_ONLY) CPUMIPSTLBContext *tlb; diff --git a/target-mips/translate.c b/target-mips/translate.c index d1c25d2b22..71dccaea55 100644 --- a/target-mips/translate.c +++ b/target-mips/translate.c @@ -15613,8 +15613,8 @@ gen_intermediate_code_internal(MIPSCPU *cpu, TranslationBlock *tb, LOG_DISAS("\ntb %p idx %d hflags %04x\n", tb, ctx.mem_idx, ctx.hflags); gen_tb_start(); while (ctx.bstate == BS_NONE) { - if (unlikely(!QTAILQ_EMPTY(&env->breakpoints))) { - QTAILQ_FOREACH(bp, &env->breakpoints, entry) { + if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) { + QTAILQ_FOREACH(bp, &cs->breakpoints, entry) { if (bp->pc == ctx.pc) { save_cpu_state(&ctx, 1); ctx.bstate = BS_BRANCH; diff --git a/target-moxie/cpu.c b/target-moxie/cpu.c index 03d8eb13d7..14d1a24438 100644 --- a/target-moxie/cpu.c +++ b/target-moxie/cpu.c @@ -42,7 +42,7 @@ static void moxie_cpu_reset(CPUState *s) mcc->parent_reset(s); - memset(env, 0, offsetof(CPUMoxieState, breakpoints)); + memset(env, 0, sizeof(CPUMoxieState)); env->pc = 0x1000; tlb_flush(env, 1); diff --git a/target-moxie/translate.c b/target-moxie/translate.c index a93196f47b..63f889fd7f 100644 --- a/target-moxie/translate.c +++ b/target-moxie/translate.c @@ -845,8 +845,8 @@ gen_intermediate_code_internal(MoxieCPU *cpu, TranslationBlock *tb, gen_tb_start(); do { - if (unlikely(!QTAILQ_EMPTY(&env->breakpoints))) { - QTAILQ_FOREACH(bp, &env->breakpoints, entry) { + if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) { + QTAILQ_FOREACH(bp, &cs->breakpoints, entry) { if (ctx.pc == bp->pc) { tcg_gen_movi_i32(cpu_pc, ctx.pc); gen_helper_debug(cpu_env); diff --git a/target-openrisc/cpu.c b/target-openrisc/cpu.c index b601de009c..a00369bef5 100644 --- a/target-openrisc/cpu.c +++ b/target-openrisc/cpu.c @@ -41,7 +41,11 @@ static void openrisc_cpu_reset(CPUState *s) occ->parent_reset(s); - memset(&cpu->env, 0, offsetof(CPUOpenRISCState, breakpoints)); +#ifndef CONFIG_USER_ONLY + memset(&cpu->env, 0, offsetof(CPUOpenRISCState, tlb)); +#else + memset(&cpu->env, 0, offsetof(CPUOpenRISCState, irq)); +#endif tlb_flush(&cpu->env, 1); /*tb_flush(&cpu->env); FIXME: Do we need it? */ diff --git a/target-openrisc/cpu.h b/target-openrisc/cpu.h index 660bb4f1e7..4512f459bf 100644 --- a/target-openrisc/cpu.h +++ b/target-openrisc/cpu.h @@ -304,6 +304,7 @@ typedef struct CPUOpenRISCState { CPU_COMMON + /* Fields from here on are preserved across CPU reset. */ #ifndef CONFIG_USER_ONLY CPUOpenRISCTLBContext * tlb; diff --git a/target-openrisc/translate.c b/target-openrisc/translate.c index 776cb6eece..852b5e6107 100644 --- a/target-openrisc/translate.c +++ b/target-openrisc/translate.c @@ -1619,10 +1619,11 @@ static void disas_openrisc_insn(DisasContext *dc, OpenRISCCPU *cpu) static void check_breakpoint(OpenRISCCPU *cpu, DisasContext *dc) { + CPUState *cs = CPU(cpu); CPUBreakpoint *bp; - if (unlikely(!QTAILQ_EMPTY(&cpu->env.breakpoints))) { - QTAILQ_FOREACH(bp, &cpu->env.breakpoints, entry) { + if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) { + QTAILQ_FOREACH(bp, &cs->breakpoints, entry) { if (bp->pc == dc->pc) { tcg_gen_movi_tl(cpu_pc, dc->pc); gen_exception(dc, EXCP_DEBUG); diff --git a/target-ppc/translate.c b/target-ppc/translate.c index 91c33dcd1d..e3fcb03c26 100644 --- a/target-ppc/translate.c +++ b/target-ppc/translate.c @@ -11377,8 +11377,8 @@ static inline void gen_intermediate_code_internal(PowerPCCPU *cpu, /* Set env in case of segfault during code fetch */ while (ctx.exception == POWERPC_EXCP_NONE && tcg_ctx.gen_opc_ptr < gen_opc_end) { - if (unlikely(!QTAILQ_EMPTY(&env->breakpoints))) { - QTAILQ_FOREACH(bp, &env->breakpoints, entry) { + if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) { + QTAILQ_FOREACH(bp, &cs->breakpoints, entry) { if (bp->pc == ctx.nip) { gen_debug_exception(ctxp); break; diff --git a/target-s390x/cpu.c b/target-s390x/cpu.c index 993d924e52..ae78ebc5f7 100644 --- a/target-s390x/cpu.c +++ b/target-s390x/cpu.c @@ -109,7 +109,7 @@ static void s390_cpu_initial_reset(CPUState *s) s390_cpu_reset(s); /* initial reset does not touch regs,fregs and aregs */ - memset(&env->fpc, 0, offsetof(CPUS390XState, breakpoints) - + memset(&env->fpc, 0, offsetof(CPUS390XState, cpu_num) - offsetof(CPUS390XState, fpc)); /* architectured initial values for CR 0 and 14 */ @@ -139,7 +139,7 @@ static void s390_cpu_full_reset(CPUState *s) scc->parent_reset(s); - memset(env, 0, offsetof(CPUS390XState, breakpoints)); + memset(env, 0, offsetof(CPUS390XState, cpu_num)); /* architectured initial values for CR 0 and 14 */ env->cregs[0] = CR0_RESET; diff --git a/target-s390x/translate.c b/target-s390x/translate.c index bc99a378a7..81b7e330ab 100644 --- a/target-s390x/translate.c +++ b/target-s390x/translate.c @@ -4795,8 +4795,8 @@ static inline void gen_intermediate_code_internal(S390CPU *cpu, } status = NO_EXIT; - if (unlikely(!QTAILQ_EMPTY(&env->breakpoints))) { - QTAILQ_FOREACH(bp, &env->breakpoints, entry) { + if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) { + QTAILQ_FOREACH(bp, &cs->breakpoints, entry) { if (bp->pc == dc.pc) { status = EXIT_PC_STALE; do_debug = true; diff --git a/target-sh4/cpu.c b/target-sh4/cpu.c index 88960c8512..4e0e2179cc 100644 --- a/target-sh4/cpu.c +++ b/target-sh4/cpu.c @@ -53,7 +53,7 @@ static void superh_cpu_reset(CPUState *s) scc->parent_reset(s); - memset(env, 0, offsetof(CPUSH4State, breakpoints)); + memset(env, 0, offsetof(CPUSH4State, id)); tlb_flush(env, 1); env->pc = 0xA0000000; diff --git a/target-sh4/cpu.h b/target-sh4/cpu.h index a85571087d..a2e9e2c031 100644 --- a/target-sh4/cpu.h +++ b/target-sh4/cpu.h @@ -175,6 +175,7 @@ typedef struct CPUSH4State { CPU_COMMON + /* Fields from here on are preserved over CPU reset. */ int id; /* CPU model */ /* The features that we should emulate. See sh_features above. */ diff --git a/target-sh4/translate.c b/target-sh4/translate.c index 661fc6c887..2360609a0a 100644 --- a/target-sh4/translate.c +++ b/target-sh4/translate.c @@ -1889,8 +1889,8 @@ gen_intermediate_code_internal(SuperHCPU *cpu, TranslationBlock *tb, max_insns = CF_COUNT_MASK; gen_tb_start(); while (ctx.bstate == BS_NONE && tcg_ctx.gen_opc_ptr < gen_opc_end) { - if (unlikely(!QTAILQ_EMPTY(&env->breakpoints))) { - QTAILQ_FOREACH(bp, &env->breakpoints, entry) { + if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) { + QTAILQ_FOREACH(bp, &cs->breakpoints, entry) { if (ctx.pc == bp->pc) { /* We have hit a breakpoint - make sure PC is up-to-date */ tcg_gen_movi_i32(cpu_pc, ctx.pc); diff --git a/target-sparc/cpu.c b/target-sparc/cpu.c index 3e6e7a754e..8465a0b18a 100644 --- a/target-sparc/cpu.c +++ b/target-sparc/cpu.c @@ -33,7 +33,7 @@ static void sparc_cpu_reset(CPUState *s) scc->parent_reset(s); - memset(env, 0, offsetof(CPUSPARCState, breakpoints)); + memset(env, 0, offsetof(CPUSPARCState, version)); tlb_flush(env, 1); env->cwp = 0; #ifndef TARGET_SPARC64 diff --git a/target-sparc/cpu.h b/target-sparc/cpu.h index 893caa0576..f72451d53e 100644 --- a/target-sparc/cpu.h +++ b/target-sparc/cpu.h @@ -423,6 +423,7 @@ struct CPUSPARCState { CPU_COMMON + /* Fields from here on are preserved across CPU reset. */ target_ulong version; uint32_t nwindows; diff --git a/target-sparc/translate.c b/target-sparc/translate.c index 46d7859e97..2de1c4a58d 100644 --- a/target-sparc/translate.c +++ b/target-sparc/translate.c @@ -5270,8 +5270,8 @@ static inline void gen_intermediate_code_internal(SPARCCPU *cpu, max_insns = CF_COUNT_MASK; gen_tb_start(); do { - if (unlikely(!QTAILQ_EMPTY(&env->breakpoints))) { - QTAILQ_FOREACH(bp, &env->breakpoints, entry) { + if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) { + QTAILQ_FOREACH(bp, &cs->breakpoints, entry) { if (bp->pc == dc->pc) { if (dc->pc != pc_start) save_state(dc); diff --git a/target-unicore32/translate.c b/target-unicore32/translate.c index 4572890ffa..5032bbe2a0 100644 --- a/target-unicore32/translate.c +++ b/target-unicore32/translate.c @@ -1922,8 +1922,8 @@ static inline void gen_intermediate_code_internal(UniCore32CPU *cpu, gen_tb_start(); do { - if (unlikely(!QTAILQ_EMPTY(&env->breakpoints))) { - QTAILQ_FOREACH(bp, &env->breakpoints, entry) { + if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) { + QTAILQ_FOREACH(bp, &cs->breakpoints, entry) { if (bp->pc == dc->pc) { gen_set_pc_im(dc->pc); gen_exception(EXCP_DEBUG); diff --git a/target-xtensa/translate.c b/target-xtensa/translate.c index 9f5895e021..764cee96f3 100644 --- a/target-xtensa/translate.c +++ b/target-xtensa/translate.c @@ -2948,10 +2948,11 @@ invalid_opcode: static void check_breakpoint(CPUXtensaState *env, DisasContext *dc) { + CPUState *cs = CPU(xtensa_env_get_cpu(env)); CPUBreakpoint *bp; - if (unlikely(!QTAILQ_EMPTY(&env->breakpoints))) { - QTAILQ_FOREACH(bp, &env->breakpoints, entry) { + if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) { + QTAILQ_FOREACH(bp, &cs->breakpoints, entry) { if (bp->pc == dc->pc) { tcg_gen_movi_i32(cpu_pc, dc->pc); gen_exception(dc, EXCP_DEBUG); -- cgit 1.4.1 From d5a11fefef1eeed86a8f06021067ba9990729a5a Mon Sep 17 00:00:00 2001 From: Andreas Färber Date: Tue, 27 Aug 2013 00:28:06 +0200 Subject: exec: Change tlb_fill() argument to CPUState MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Andreas Färber --- include/exec/exec-all.h | 2 +- include/exec/softmmu_template.h | 8 ++++---- target-alpha/mem_helper.c | 8 +++++--- target-arm/op_helper.c | 12 +++++++----- target-cris/op_helper.c | 7 ++++--- target-i386/mem_helper.c | 12 +++++++----- target-lm32/op_helper.c | 13 ++++++++----- target-m68k/op_helper.c | 8 +++++--- target-microblaze/op_helper.c | 13 ++++++++----- target-mips/op_helper.c | 7 ++++--- target-moxie/helper.c | 7 ++++--- target-openrisc/mmu_helper.c | 8 +++++--- target-ppc/mmu_helper.c | 9 +++++---- target-s390x/mem_helper.c | 8 +++++--- target-sh4/op_helper.c | 8 +++++--- target-sparc/ldst_helper.c | 8 +++++--- target-unicore32/op_helper.c | 8 +++++--- target-xtensa/op_helper.c | 6 ++++-- 18 files changed, 91 insertions(+), 61 deletions(-) (limited to 'include/exec') diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index 2179329916..c8c3a1198b 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -332,7 +332,7 @@ bool io_mem_read(struct MemoryRegion *mr, hwaddr addr, bool io_mem_write(struct MemoryRegion *mr, hwaddr addr, uint64_t value, unsigned size); -void tlb_fill(CPUArchState *env1, target_ulong addr, int is_write, int mmu_idx, +void tlb_fill(CPUState *cpu, target_ulong addr, int is_write, int mmu_idx, uintptr_t retaddr); uint8_t helper_ldb_cmmu(CPUArchState *env, target_ulong addr, int mmu_idx); diff --git a/include/exec/softmmu_template.h b/include/exec/softmmu_template.h index ac825d251c..8603933dcb 100644 --- a/include/exec/softmmu_template.h +++ b/include/exec/softmmu_template.h @@ -158,7 +158,7 @@ WORD_TYPE helper_le_ld_name(CPUArchState *env, target_ulong addr, int mmu_idx, do_unaligned_access(env, addr, READ_ACCESS_TYPE, mmu_idx, retaddr); } #endif - tlb_fill(env, addr, READ_ACCESS_TYPE, mmu_idx, retaddr); + tlb_fill(ENV_GET_CPU(env), addr, READ_ACCESS_TYPE, mmu_idx, retaddr); tlb_addr = env->tlb_table[mmu_idx][index].ADDR_READ; } @@ -240,7 +240,7 @@ WORD_TYPE helper_be_ld_name(CPUArchState *env, target_ulong addr, int mmu_idx, do_unaligned_access(env, addr, READ_ACCESS_TYPE, mmu_idx, retaddr); } #endif - tlb_fill(env, addr, READ_ACCESS_TYPE, mmu_idx, retaddr); + tlb_fill(ENV_GET_CPU(env), addr, READ_ACCESS_TYPE, mmu_idx, retaddr); tlb_addr = env->tlb_table[mmu_idx][index].ADDR_READ; } @@ -360,7 +360,7 @@ void helper_le_st_name(CPUArchState *env, target_ulong addr, DATA_TYPE val, do_unaligned_access(env, addr, 1, mmu_idx, retaddr); } #endif - tlb_fill(env, addr, 1, mmu_idx, retaddr); + tlb_fill(ENV_GET_CPU(env), addr, 1, mmu_idx, retaddr); tlb_addr = env->tlb_table[mmu_idx][index].addr_write; } @@ -436,7 +436,7 @@ void helper_be_st_name(CPUArchState *env, target_ulong addr, DATA_TYPE val, do_unaligned_access(env, addr, 1, mmu_idx, retaddr); } #endif - tlb_fill(env, addr, 1, mmu_idx, retaddr); + tlb_fill(ENV_GET_CPU(env), addr, 1, mmu_idx, retaddr); tlb_addr = env->tlb_table[mmu_idx][index].addr_write; } diff --git a/target-alpha/mem_helper.c b/target-alpha/mem_helper.c index 23878bad80..3447f828ed 100644 --- a/target-alpha/mem_helper.c +++ b/target-alpha/mem_helper.c @@ -152,14 +152,16 @@ void alpha_cpu_unassigned_access(CPUState *cs, hwaddr addr, NULL, it means that the function was called in C code (i.e. not from generated code or from helper.c) */ /* XXX: fix it to restore all registers */ -void tlb_fill(CPUAlphaState *env, target_ulong addr, int is_write, +void tlb_fill(CPUState *cs, target_ulong addr, int is_write, int mmu_idx, uintptr_t retaddr) { - AlphaCPU *cpu = alpha_env_get_cpu(env); int ret; - ret = alpha_cpu_handle_mmu_fault(CPU(cpu), addr, is_write, mmu_idx); + ret = alpha_cpu_handle_mmu_fault(cs, addr, is_write, mmu_idx); if (unlikely(ret != 0)) { + AlphaCPU *cpu = ALPHA_CPU(cs); + CPUAlphaState *env = &cpu->env; + if (retaddr) { cpu_restore_state(env, retaddr); } diff --git a/target-arm/op_helper.c b/target-arm/op_helper.c index 931536ea4f..932f5e218d 100644 --- a/target-arm/op_helper.c +++ b/target-arm/op_helper.c @@ -72,17 +72,19 @@ uint32_t HELPER(neon_tbl)(CPUARMState *env, uint32_t ireg, uint32_t def, #include "exec/softmmu_template.h" /* try to fill the TLB and return an exception if error. If retaddr is - NULL, it means that the function was called in C code (i.e. not - from generated code or from helper.c) */ -void tlb_fill(CPUARMState *env, target_ulong addr, int is_write, int mmu_idx, + * NULL, it means that the function was called in C code (i.e. not + * from generated code or from helper.c) + */ +void tlb_fill(CPUState *cs, target_ulong addr, int is_write, int mmu_idx, uintptr_t retaddr) { - ARMCPU *cpu = arm_env_get_cpu(env); - CPUState *cs = CPU(cpu); int ret; ret = arm_cpu_handle_mmu_fault(cs, addr, is_write, mmu_idx); if (unlikely(ret)) { + ARMCPU *cpu = ARM_CPU(cs); + CPUARMState *env = &cpu->env; + if (retaddr) { /* now we have a real cpu fault */ cpu_restore_state(env, retaddr); diff --git a/target-cris/op_helper.c b/target-cris/op_helper.c index 9b20b94d9b..68a5caa2a7 100644 --- a/target-cris/op_helper.c +++ b/target-cris/op_helper.c @@ -54,15 +54,16 @@ /* Try to fill the TLB and return an exception if error. If retaddr is NULL, it means that the function was called in C code (i.e. not from generated code or from helper.c) */ -void tlb_fill(CPUCRISState *env, target_ulong addr, int is_write, int mmu_idx, +void tlb_fill(CPUState *cs, target_ulong addr, int is_write, int mmu_idx, uintptr_t retaddr) { - CRISCPU *cpu = cris_env_get_cpu(env); + CRISCPU *cpu = CRIS_CPU(cs); + CPUCRISState *env = &cpu->env; int ret; D_LOG("%s pc=%x tpc=%x ra=%p\n", __func__, env->pc, env->pregs[PR_EDA], (void *)retaddr); - ret = cris_cpu_handle_mmu_fault(CPU(cpu), addr, is_write, mmu_idx); + ret = cris_cpu_handle_mmu_fault(cs, addr, is_write, mmu_idx); if (unlikely(ret)) { if (retaddr) { /* now we have a real cpu fault */ diff --git a/target-i386/mem_helper.c b/target-i386/mem_helper.c index c0d3b45552..2f0691be8f 100644 --- a/target-i386/mem_helper.c +++ b/target-i386/mem_helper.c @@ -129,18 +129,20 @@ void helper_boundl(CPUX86State *env, target_ulong a0, int v) #if !defined(CONFIG_USER_ONLY) /* try to fill the TLB and return an exception if error. If retaddr is - NULL, it means that the function was called in C code (i.e. not - from generated code or from helper.c) */ + * NULL, it means that the function was called in C code (i.e. not + * from generated code or from helper.c) + */ /* XXX: fix it to restore all registers */ -void tlb_fill(CPUX86State *env, target_ulong addr, int is_write, int mmu_idx, +void tlb_fill(CPUState *cs, target_ulong addr, int is_write, int mmu_idx, uintptr_t retaddr) { - X86CPU *cpu = x86_env_get_cpu(env); - CPUState *cs = CPU(cpu); int ret; ret = x86_cpu_handle_mmu_fault(cs, addr, is_write, mmu_idx); if (ret) { + X86CPU *cpu = X86_CPU(cs); + CPUX86State *env = &cpu->env; + if (retaddr) { /* now we have a real cpu fault */ cpu_restore_state(env, retaddr); diff --git a/target-lm32/op_helper.c b/target-lm32/op_helper.c index 3b513a7edb..7fc9191e19 100644 --- a/target-lm32/op_helper.c +++ b/target-lm32/op_helper.c @@ -150,16 +150,19 @@ uint32_t HELPER(rcsr_jrx)(CPULM32State *env) } /* Try to fill the TLB and return an exception if error. If retaddr is - NULL, it means that the function was called in C code (i.e. not - from generated code or from helper.c) */ -void tlb_fill(CPULM32State *env, target_ulong addr, int is_write, int mmu_idx, + * NULL, it means that the function was called in C code (i.e. not + * from generated code or from helper.c) + */ +void tlb_fill(CPUState *cs, target_ulong addr, int is_write, int mmu_idx, uintptr_t retaddr) { - LM32CPU *cpu = lm32_env_get_cpu(env); int ret; - ret = lm32_cpu_handle_mmu_fault(CPU(cpu), addr, is_write, mmu_idx); + ret = lm32_cpu_handle_mmu_fault(cs, addr, is_write, mmu_idx); if (unlikely(ret)) { + LM32CPU *cpu = LM32_CPU(cs); + CPULM32State *env = &cpu->env; + if (retaddr) { /* now we have a real cpu fault */ cpu_restore_state(env, retaddr); diff --git a/target-m68k/op_helper.c b/target-m68k/op_helper.c index 930d7c8d04..b1745b8796 100644 --- a/target-m68k/op_helper.c +++ b/target-m68k/op_helper.c @@ -53,14 +53,16 @@ extern int semihosting_enabled; /* Try to fill the TLB and return an exception if error. If retaddr is NULL, it means that the function was called in C code (i.e. not from generated code or from helper.c) */ -void tlb_fill(CPUM68KState *env, target_ulong addr, int is_write, int mmu_idx, +void tlb_fill(CPUState *cs, target_ulong addr, int is_write, int mmu_idx, uintptr_t retaddr) { - M68kCPU *cpu = m68k_env_get_cpu(env); int ret; - ret = m68k_cpu_handle_mmu_fault(CPU(cpu), addr, is_write, mmu_idx); + ret = m68k_cpu_handle_mmu_fault(cs, addr, is_write, mmu_idx); if (unlikely(ret)) { + M68kCPU *cpu = M68K_CPU(cs); + CPUM68KState *env = &cpu->env; + if (retaddr) { /* now we have a real cpu fault */ cpu_restore_state(env, retaddr); diff --git a/target-microblaze/op_helper.c b/target-microblaze/op_helper.c index 318185a5df..9e394114c8 100644 --- a/target-microblaze/op_helper.c +++ b/target-microblaze/op_helper.c @@ -39,16 +39,19 @@ #include "exec/softmmu_template.h" /* Try to fill the TLB and return an exception if error. If retaddr is - NULL, it means that the function was called in C code (i.e. not - from generated code or from helper.c) */ -void tlb_fill(CPUMBState *env, target_ulong addr, int is_write, int mmu_idx, + * NULL, it means that the function was called in C code (i.e. not + * from generated code or from helper.c) + */ +void tlb_fill(CPUState *cs, target_ulong addr, int is_write, int mmu_idx, uintptr_t retaddr) { - MicroBlazeCPU *cpu = mb_env_get_cpu(env); int ret; - ret = mb_cpu_handle_mmu_fault(CPU(cpu), addr, is_write, mmu_idx); + ret = mb_cpu_handle_mmu_fault(cs, addr, is_write, mmu_idx); if (unlikely(ret)) { + MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs); + CPUMBState *env = &cpu->env; + if (retaddr) { /* now we have a real cpu fault */ cpu_restore_state(env, retaddr); diff --git a/target-mips/op_helper.c b/target-mips/op_helper.c index 5a4a656f3d..8c050fc247 100644 --- a/target-mips/op_helper.c +++ b/target-mips/op_helper.c @@ -2145,15 +2145,16 @@ static void do_unaligned_access(CPUMIPSState *env, target_ulong addr, do_raise_exception(env, (is_write == 1) ? EXCP_AdES : EXCP_AdEL, retaddr); } -void tlb_fill(CPUMIPSState *env, target_ulong addr, int is_write, int mmu_idx, +void tlb_fill(CPUState *cs, target_ulong addr, int is_write, int mmu_idx, uintptr_t retaddr) { - MIPSCPU *cpu = mips_env_get_cpu(env); - CPUState *cs = CPU(cpu); int ret; ret = mips_cpu_handle_mmu_fault(cs, addr, is_write, mmu_idx); if (ret) { + MIPSCPU *cpu = MIPS_CPU(cs); + CPUMIPSState *env = &cpu->env; + do_raise_exception_err(env, cs->exception_index, env->error_code, retaddr); } diff --git a/target-moxie/helper.c b/target-moxie/helper.c index 3b14f3735e..06a4c728ee 100644 --- a/target-moxie/helper.c +++ b/target-moxie/helper.c @@ -46,13 +46,14 @@ /* Try to fill the TLB and return an exception if error. If retaddr is NULL, it means that the function was called in C code (i.e. not from generated code or from helper.c) */ -void tlb_fill(CPUMoxieState *env, target_ulong addr, int is_write, int mmu_idx, +void tlb_fill(CPUState *cs, target_ulong addr, int is_write, int mmu_idx, uintptr_t retaddr) { - MoxieCPU *cpu = moxie_env_get_cpu(env); + MoxieCPU *cpu = MOXIE_CPU(cs); + CPUMoxieState *env = &cpu->env; int ret; - ret = moxie_cpu_handle_mmu_fault(CPU(cpu), addr, is_write, mmu_idx); + ret = moxie_cpu_handle_mmu_fault(cs, addr, is_write, mmu_idx); if (unlikely(ret)) { if (retaddr) { cpu_restore_state(env, retaddr); diff --git a/target-openrisc/mmu_helper.c b/target-openrisc/mmu_helper.c index b023a5fb98..e3fe6c7127 100644 --- a/target-openrisc/mmu_helper.c +++ b/target-openrisc/mmu_helper.c @@ -36,15 +36,17 @@ #define SHIFT 3 #include "exec/softmmu_template.h" -void tlb_fill(CPUOpenRISCState *env, target_ulong addr, int is_write, +void tlb_fill(CPUState *cs, target_ulong addr, int is_write, int mmu_idx, uintptr_t retaddr) { - OpenRISCCPU *cpu = openrisc_env_get_cpu(env); int ret; - ret = openrisc_cpu_handle_mmu_fault(CPU(cpu), addr, is_write, mmu_idx); + ret = openrisc_cpu_handle_mmu_fault(cs, addr, is_write, mmu_idx); if (ret) { + OpenRISCCPU *cpu = OPENRISC_CPU(cs); + CPUOpenRISCState *env = &cpu->env; + if (retaddr) { /* now we have a real cpu fault. */ cpu_restore_state(env, retaddr); diff --git a/target-ppc/mmu_helper.c b/target-ppc/mmu_helper.c index b6abd974e3..c0421848b1 100644 --- a/target-ppc/mmu_helper.c +++ b/target-ppc/mmu_helper.c @@ -2893,11 +2893,12 @@ void helper_booke206_tlbflush(CPUPPCState *env, uint32_t type) NULL, it means that the function was called in C code (i.e. not from generated code or from helper.c) */ /* XXX: fix it to restore all registers */ -void tlb_fill(CPUPPCState *env, target_ulong addr, int is_write, int mmu_idx, +void tlb_fill(CPUState *cs, target_ulong addr, int is_write, int mmu_idx, uintptr_t retaddr) { - CPUState *cpu = CPU(ppc_env_get_cpu(env)); - PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); + PowerPCCPU *cpu = POWERPC_CPU(cs); + PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs); + CPUPPCState *env = &cpu->env; int ret; if (pcc->handle_mmu_fault) { @@ -2910,6 +2911,6 @@ void tlb_fill(CPUPPCState *env, target_ulong addr, int is_write, int mmu_idx, /* now we have a real cpu fault */ cpu_restore_state(env, retaddr); } - helper_raise_exception_err(env, cpu->exception_index, env->error_code); + helper_raise_exception_err(env, cs->exception_index, env->error_code); } } diff --git a/target-s390x/mem_helper.c b/target-s390x/mem_helper.c index 411c32692a..1e74e4d7e4 100644 --- a/target-s390x/mem_helper.c +++ b/target-s390x/mem_helper.c @@ -44,14 +44,16 @@ NULL, it means that the function was called in C code (i.e. not from generated code or from helper.c) */ /* XXX: fix it to restore all registers */ -void tlb_fill(CPUS390XState *env, target_ulong addr, int is_write, int mmu_idx, +void tlb_fill(CPUState *cs, target_ulong addr, int is_write, int mmu_idx, uintptr_t retaddr) { - S390CPU *cpu = s390_env_get_cpu(env); int ret; - ret = s390_cpu_handle_mmu_fault(CPU(cpu), addr, is_write, mmu_idx); + ret = s390_cpu_handle_mmu_fault(cs, addr, is_write, mmu_idx); if (unlikely(ret != 0)) { + S390CPU *cpu = S390_CPU(cs); + CPUS390XState *env = &cpu->env; + if (likely(retaddr)) { /* now we have a real cpu fault */ cpu_restore_state(env, retaddr); diff --git a/target-sh4/op_helper.c b/target-sh4/op_helper.c index 03633f0ee8..6e527cfcf3 100644 --- a/target-sh4/op_helper.c +++ b/target-sh4/op_helper.c @@ -38,15 +38,17 @@ #define SHIFT 3 #include "exec/softmmu_template.h" -void tlb_fill(CPUSH4State *env, target_ulong addr, int is_write, int mmu_idx, +void tlb_fill(CPUState *cs, target_ulong addr, int is_write, int mmu_idx, uintptr_t retaddr) { - SuperHCPU *cpu = sh_env_get_cpu(env); int ret; - ret = superh_cpu_handle_mmu_fault(CPU(cpu), addr, is_write, mmu_idx); + ret = superh_cpu_handle_mmu_fault(cs, addr, is_write, mmu_idx); if (ret) { /* now we have a real cpu fault */ + SuperHCPU *cpu = SUPERH_CPU(cs); + CPUSH4State *env = &cpu->env; + if (retaddr) { cpu_restore_state(env, retaddr); } diff --git a/target-sparc/ldst_helper.c b/target-sparc/ldst_helper.c index e1475d0b0f..32d0bfda18 100644 --- a/target-sparc/ldst_helper.c +++ b/target-sparc/ldst_helper.c @@ -2438,14 +2438,16 @@ static void QEMU_NORETURN do_unaligned_access(CPUSPARCState *env, NULL, it means that the function was called in C code (i.e. not from generated code or from helper.c) */ /* XXX: fix it to restore all registers */ -void tlb_fill(CPUSPARCState *env, target_ulong addr, int is_write, int mmu_idx, +void tlb_fill(CPUState *cs, target_ulong addr, int is_write, int mmu_idx, uintptr_t retaddr) { - SPARCCPU *cpu = sparc_env_get_cpu(env); int ret; - ret = sparc_cpu_handle_mmu_fault(CPU(cpu), addr, is_write, mmu_idx); + ret = sparc_cpu_handle_mmu_fault(cs, addr, is_write, mmu_idx); if (ret) { + SPARCCPU *cpu = SPARC_CPU(cs); + CPUSPARCState *env = &cpu->env; + if (retaddr) { cpu_restore_state(env, retaddr); } diff --git a/target-unicore32/op_helper.c b/target-unicore32/op_helper.c index cd2cbef34f..3efc6a80a4 100644 --- a/target-unicore32/op_helper.c +++ b/target-unicore32/op_helper.c @@ -257,14 +257,16 @@ uint32_t HELPER(ror_cc)(CPUUniCore32State *env, uint32_t x, uint32_t i) #define SHIFT 3 #include "exec/softmmu_template.h" -void tlb_fill(CPUUniCore32State *env, target_ulong addr, int is_write, +void tlb_fill(CPUState *cs, target_ulong addr, int is_write, int mmu_idx, uintptr_t retaddr) { - UniCore32CPU *cpu = uc32_env_get_cpu(env); int ret; - ret = uc32_cpu_handle_mmu_fault(CPU(cpu), addr, is_write, mmu_idx); + ret = uc32_cpu_handle_mmu_fault(cs, addr, is_write, mmu_idx); if (unlikely(ret)) { + UniCore32CPU *cpu = UNICORE32_CPU(cs); + CPUUniCore32State *env = &cpu->env; + if (retaddr) { /* now we have a real cpu fault */ cpu_restore_state(env, retaddr); diff --git a/target-xtensa/op_helper.c b/target-xtensa/op_helper.c index a314ed0b9d..1c80e310ab 100644 --- a/target-xtensa/op_helper.c +++ b/target-xtensa/op_helper.c @@ -60,9 +60,11 @@ static void do_unaligned_access(CPUXtensaState *env, } } -void tlb_fill(CPUXtensaState *env, - target_ulong vaddr, int is_write, int mmu_idx, uintptr_t retaddr) +void tlb_fill(CPUState *cs, + target_ulong vaddr, int is_write, int mmu_idx, uintptr_t retaddr) { + XtensaCPU *cpu = XTENSA_CPU(cs); + CPUXtensaState *env = &cpu->env; uint32_t paddr; uint32_t page_size; unsigned access; -- cgit 1.4.1 From 5638d180d6c469fc4c56127a3c717e8b9f27d925 Mon Sep 17 00:00:00 2001 From: Andreas Färber Date: Tue, 27 Aug 2013 17:52:12 +0200 Subject: cpu-exec: Change cpu_loop_exit() argument to CPUState MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Andreas Färber --- cpu-exec.c | 14 ++++++-------- exec.c | 2 +- include/exec/exec-all.h | 2 +- target-alpha/helper.c | 4 ++-- target-alpha/mem_helper.c | 4 ++-- target-arm/op_helper.c | 8 ++++---- target-cris/op_helper.c | 4 ++-- target-i386/excp_helper.c | 2 +- target-i386/misc_helper.c | 7 +++---- target-i386/seg_helper.c | 2 +- target-i386/svm_helper.c | 8 ++++---- target-lm32/op_helper.c | 6 +++--- target-m68k/op_helper.c | 6 +++--- target-microblaze/op_helper.c | 4 ++-- target-mips/op_helper.c | 4 ++-- target-moxie/helper.c | 6 +++--- target-openrisc/exception.c | 2 +- target-openrisc/mmu_helper.c | 2 +- target-ppc/excp_helper.c | 2 +- target-s390x/cc_helper.c | 2 +- target-s390x/mem_helper.c | 6 +++--- target-s390x/misc_helper.c | 10 +++++----- target-sh4/op_helper.c | 4 ++-- target-sparc/helper.c | 6 +++--- target-sparc/ldst_helper.c | 2 +- target-unicore32/op_helper.c | 4 ++-- target-xtensa/op_helper.c | 4 ++-- user-exec.c | 4 ++-- 28 files changed, 64 insertions(+), 67 deletions(-) (limited to 'include/exec') diff --git a/cpu-exec.c b/cpu-exec.c index d7c21d35e5..192620f37b 100644 --- a/cpu-exec.c +++ b/cpu-exec.c @@ -23,10 +23,8 @@ #include "qemu/atomic.h" #include "sysemu/qtest.h" -void cpu_loop_exit(CPUArchState *env) +void cpu_loop_exit(CPUState *cpu) { - CPUState *cpu = ENV_GET_CPU(env); - cpu->current_tb = NULL; siglongjmp(cpu->jmp_env, 1); } @@ -325,7 +323,7 @@ int cpu_exec(CPUArchState *env) if (interrupt_request & CPU_INTERRUPT_DEBUG) { cpu->interrupt_request &= ~CPU_INTERRUPT_DEBUG; cpu->exception_index = EXCP_DEBUG; - cpu_loop_exit(env); + cpu_loop_exit(cpu); } #if defined(TARGET_ARM) || defined(TARGET_SPARC) || defined(TARGET_MIPS) || \ defined(TARGET_PPC) || defined(TARGET_ALPHA) || defined(TARGET_CRIS) || \ @@ -334,7 +332,7 @@ int cpu_exec(CPUArchState *env) cpu->interrupt_request &= ~CPU_INTERRUPT_HALT; cpu->halted = 1; cpu->exception_index = EXCP_HLT; - cpu_loop_exit(env); + cpu_loop_exit(cpu); } #endif #if defined(TARGET_I386) @@ -349,7 +347,7 @@ int cpu_exec(CPUArchState *env) 0); do_cpu_init(x86_cpu); cpu->exception_index = EXCP_HALTED; - cpu_loop_exit(env); + cpu_loop_exit(cpu); } else if (interrupt_request & CPU_INTERRUPT_SIPI) { do_cpu_sipi(x86_cpu); } else if (env->hflags2 & HF2_GIF_MASK) { @@ -601,7 +599,7 @@ int cpu_exec(CPUArchState *env) if (unlikely(cpu->exit_request)) { cpu->exit_request = 0; cpu->exception_index = EXCP_INTERRUPT; - cpu_loop_exit(env); + cpu_loop_exit(cpu); } spin_lock(&tcg_ctx.tb_ctx.tb_lock); tb = tb_find_fast(env); @@ -672,7 +670,7 @@ int cpu_exec(CPUArchState *env) } cpu->exception_index = EXCP_INTERRUPT; next_tb = 0; - cpu_loop_exit(env); + cpu_loop_exit(cpu); } break; } diff --git a/exec.c b/exec.c index 6d9e13a0a6..5f7c47244f 100644 --- a/exec.c +++ b/exec.c @@ -1608,7 +1608,7 @@ static void check_watchpoint(int offset, int len_mask, int flags) tb_check_watchpoint(env); if (wp->flags & BP_STOP_BEFORE_ACCESS) { cpu->exception_index = EXCP_DEBUG; - cpu_loop_exit(env); + cpu_loop_exit(cpu); } else { cpu_get_tb_cpu_state(env, &pc, &cs_base, &cpu_flags); tb_gen_code(env, pc, cs_base, cpu_flags, 1); diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index c8c3a1198b..80277eac32 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -89,7 +89,7 @@ TranslationBlock *tb_gen_code(CPUArchState *env, target_ulong pc, target_ulong cs_base, int flags, int cflags); void cpu_exec_init(CPUArchState *env); -void QEMU_NORETURN cpu_loop_exit(CPUArchState *env1); +void QEMU_NORETURN cpu_loop_exit(CPUState *cpu); int page_unprotect(target_ulong address, uintptr_t pc, void *puc); void tb_invalidate_phys_page_range(tb_page_addr_t start, tb_page_addr_t end, int is_cpu_write_access); diff --git a/target-alpha/helper.c b/target-alpha/helper.c index 14f59a27a8..45f73e0ea2 100644 --- a/target-alpha/helper.c +++ b/target-alpha/helper.c @@ -513,7 +513,7 @@ void QEMU_NORETURN helper_excp(CPUAlphaState *env, int excp, int error) cs->exception_index = excp; env->error_code = error; - cpu_loop_exit(env); + cpu_loop_exit(cs); } /* This may be called from any of the helpers to set up EXCEPTION_INDEX. */ @@ -528,7 +528,7 @@ void QEMU_NORETURN dynamic_excp(CPUAlphaState *env, uintptr_t retaddr, if (retaddr) { cpu_restore_state(env, retaddr); } - cpu_loop_exit(env); + cpu_loop_exit(cs); } void QEMU_NORETURN arith_excp(CPUAlphaState *env, uintptr_t retaddr, diff --git a/target-alpha/mem_helper.c b/target-alpha/mem_helper.c index 3447f828ed..1957c566b9 100644 --- a/target-alpha/mem_helper.c +++ b/target-alpha/mem_helper.c @@ -116,7 +116,7 @@ static void do_unaligned_access(CPUAlphaState *env, target_ulong addr, env->trap_arg2 = (insn >> 21) & 31; /* dest regno */ cs->exception_index = EXCP_UNALIGN; env->error_code = 0; - cpu_loop_exit(env); + cpu_loop_exit(cs); } void alpha_cpu_unassigned_access(CPUState *cs, hwaddr addr, @@ -166,7 +166,7 @@ void tlb_fill(CPUState *cs, target_ulong addr, int is_write, cpu_restore_state(env, retaddr); } /* Exception index and error code are already set */ - cpu_loop_exit(env); + cpu_loop_exit(cs); } } #endif /* CONFIG_USER_ONLY */ diff --git a/target-arm/op_helper.c b/target-arm/op_helper.c index 932f5e218d..f8e535e8ce 100644 --- a/target-arm/op_helper.c +++ b/target-arm/op_helper.c @@ -28,7 +28,7 @@ static void raise_exception(CPUARMState *env, int tt) CPUState *cs = CPU(cpu); cs->exception_index = tt; - cpu_loop_exit(env); + cpu_loop_exit(cs); } uint32_t HELPER(neon_tbl)(CPUARMState *env, uint32_t ireg, uint32_t def, @@ -229,7 +229,7 @@ void HELPER(wfi)(CPUARMState *env) cs->exception_index = EXCP_HLT; cs->halted = 1; - cpu_loop_exit(env); + cpu_loop_exit(cs); } void HELPER(wfe)(CPUARMState *env) @@ -240,7 +240,7 @@ void HELPER(wfe)(CPUARMState *env) * level loop */ cs->exception_index = EXCP_YIELD; - cpu_loop_exit(env); + cpu_loop_exit(cs); } void HELPER(exception)(CPUARMState *env, uint32_t excp) @@ -248,7 +248,7 @@ void HELPER(exception)(CPUARMState *env, uint32_t excp) CPUState *cs = CPU(arm_env_get_cpu(env)); cs->exception_index = excp; - cpu_loop_exit(env); + cpu_loop_exit(cs); } uint32_t HELPER(cpsr_read)(CPUARMState *env) diff --git a/target-cris/op_helper.c b/target-cris/op_helper.c index 68a5caa2a7..d80b6c966d 100644 --- a/target-cris/op_helper.c +++ b/target-cris/op_helper.c @@ -72,7 +72,7 @@ void tlb_fill(CPUState *cs, target_ulong addr, int is_write, int mmu_idx, helper_top_evaluate_flags(env); } } - cpu_loop_exit(env); + cpu_loop_exit(cs); } } @@ -83,7 +83,7 @@ void helper_raise_exception(CPUCRISState *env, uint32_t index) CPUState *cs = CPU(cris_env_get_cpu(env)); cs->exception_index = index; - cpu_loop_exit(env); + cpu_loop_exit(cs); } void helper_tlb_flush_pid(CPUCRISState *env, uint32_t pid) diff --git a/target-i386/excp_helper.c b/target-i386/excp_helper.c index ec76eba760..f337fd20fb 100644 --- a/target-i386/excp_helper.c +++ b/target-i386/excp_helper.c @@ -108,7 +108,7 @@ static void QEMU_NORETURN raise_interrupt2(CPUX86State *env, int intno, env->error_code = error_code; env->exception_is_int = is_int; env->exception_next_eip = env->eip + next_eip_addend; - cpu_loop_exit(env); + cpu_loop_exit(cs); } /* shortcuts to generate exceptions */ diff --git a/target-i386/misc_helper.c b/target-i386/misc_helper.c index 582ad34ffe..8c6b9bfce2 100644 --- a/target-i386/misc_helper.c +++ b/target-i386/misc_helper.c @@ -569,11 +569,10 @@ void helper_rdmsr(CPUX86State *env) static void do_pause(X86CPU *cpu) { CPUState *cs = CPU(cpu); - CPUX86State *env = &cpu->env; /* Just let another CPU run. */ cs->exception_index = EXCP_INTERRUPT; - cpu_loop_exit(env); + cpu_loop_exit(cs); } static void do_hlt(X86CPU *cpu) @@ -584,7 +583,7 @@ static void do_hlt(X86CPU *cpu) env->hflags &= ~HF_INHIBIT_IRQ_MASK; /* needed if sti is just before */ cs->halted = 1; cs->exception_index = EXCP_HLT; - cpu_loop_exit(env); + cpu_loop_exit(cs); } void helper_hlt(CPUX86State *env, int next_eip_addend) @@ -642,5 +641,5 @@ void helper_debug(CPUX86State *env) CPUState *cs = CPU(x86_env_get_cpu(env)); cs->exception_index = EXCP_DEBUG; - cpu_loop_exit(env); + cpu_loop_exit(cs); } diff --git a/target-i386/seg_helper.c b/target-i386/seg_helper.c index c8fd572d99..4e134e4338 100644 --- a/target-i386/seg_helper.c +++ b/target-i386/seg_helper.c @@ -939,7 +939,7 @@ void helper_syscall(CPUX86State *env, int next_eip_addend) cs->exception_index = EXCP_SYSCALL; env->exception_next_eip = env->eip + next_eip_addend; - cpu_loop_exit(env); + cpu_loop_exit(cs); } #else void helper_syscall(CPUX86State *env, int next_eip_addend) diff --git a/target-i386/svm_helper.c b/target-i386/svm_helper.c index 5e0504d7f0..de2c2eebe0 100644 --- a/target-i386/svm_helper.c +++ b/target-i386/svm_helper.c @@ -334,7 +334,7 @@ void helper_vmrun(CPUX86State *env, int aflag, int next_eip_addend) env->exception_is_int = 0; env->exception_next_eip = env->eip; qemu_log_mask(CPU_LOG_TB_IN_ASM, "NMI"); - cpu_loop_exit(env); + cpu_loop_exit(cs); break; case SVM_EVTINJ_TYPE_EXEPT: cs->exception_index = vector; @@ -342,7 +342,7 @@ void helper_vmrun(CPUX86State *env, int aflag, int next_eip_addend) env->exception_is_int = 0; env->exception_next_eip = -1; qemu_log_mask(CPU_LOG_TB_IN_ASM, "EXEPT"); - cpu_loop_exit(env); + cpu_loop_exit(cs); break; case SVM_EVTINJ_TYPE_SOFT: cs->exception_index = vector; @@ -350,7 +350,7 @@ void helper_vmrun(CPUX86State *env, int aflag, int next_eip_addend) env->exception_is_int = 1; env->exception_next_eip = env->eip; qemu_log_mask(CPU_LOG_TB_IN_ASM, "SOFT"); - cpu_loop_exit(env); + cpu_loop_exit(cs); break; } qemu_log_mask(CPU_LOG_TB_IN_ASM, " %#x %#x\n", cs->exception_index, @@ -772,7 +772,7 @@ void helper_vmexit(CPUX86State *env, uint32_t exit_code, uint64_t exit_info_1) env->error_code = 0; env->old_exception = -1; - cpu_loop_exit(env); + cpu_loop_exit(cs); } void cpu_vmexit(CPUX86State *env, uint32_t exit_code, uint64_t exit_info_1) diff --git a/target-lm32/op_helper.c b/target-lm32/op_helper.c index 7fc9191e19..f0859aab6d 100644 --- a/target-lm32/op_helper.c +++ b/target-lm32/op_helper.c @@ -28,7 +28,7 @@ void raise_exception(CPULM32State *env, int index) CPUState *cs = CPU(lm32_env_get_cpu(env)); cs->exception_index = index; - cpu_loop_exit(env); + cpu_loop_exit(cs); } void HELPER(raise_exception)(CPULM32State *env, uint32_t index) @@ -42,7 +42,7 @@ void HELPER(hlt)(CPULM32State *env) cs->halted = 1; cs->exception_index = EXCP_HLT; - cpu_loop_exit(env); + cpu_loop_exit(cs); } void HELPER(ill)(CPULM32State *env) @@ -167,7 +167,7 @@ void tlb_fill(CPUState *cs, target_ulong addr, int is_write, int mmu_idx, /* now we have a real cpu fault */ cpu_restore_state(env, retaddr); } - cpu_loop_exit(env); + cpu_loop_exit(cs); } } #endif diff --git a/target-m68k/op_helper.c b/target-m68k/op_helper.c index b1745b8796..d6268cd6b9 100644 --- a/target-m68k/op_helper.c +++ b/target-m68k/op_helper.c @@ -67,7 +67,7 @@ void tlb_fill(CPUState *cs, target_ulong addr, int is_write, int mmu_idx, /* now we have a real cpu fault */ cpu_restore_state(env, retaddr); } - cpu_loop_exit(env); + cpu_loop_exit(cs); } } @@ -114,7 +114,7 @@ static void do_interrupt_all(CPUM68KState *env, int is_hw) } cs->halted = 1; cs->exception_index = EXCP_HLT; - cpu_loop_exit(env); + cpu_loop_exit(cs); return; } if (cs->exception_index >= EXCP_TRAP0 @@ -170,7 +170,7 @@ static void raise_exception(CPUM68KState *env, int tt) CPUState *cs = CPU(m68k_env_get_cpu(env)); cs->exception_index = tt; - cpu_loop_exit(env); + cpu_loop_exit(cs); } void HELPER(raise_exception)(CPUM68KState *env, uint32_t tt) diff --git a/target-microblaze/op_helper.c b/target-microblaze/op_helper.c index 9e394114c8..f47613241d 100644 --- a/target-microblaze/op_helper.c +++ b/target-microblaze/op_helper.c @@ -56,7 +56,7 @@ void tlb_fill(CPUState *cs, target_ulong addr, int is_write, int mmu_idx, /* now we have a real cpu fault */ cpu_restore_state(env, retaddr); } - cpu_loop_exit(env); + cpu_loop_exit(cs); } } #endif @@ -101,7 +101,7 @@ void helper_raise_exception(CPUMBState *env, uint32_t index) CPUState *cs = CPU(mb_env_get_cpu(env)); cs->exception_index = index; - cpu_loop_exit(env); + cpu_loop_exit(cs); } void helper_debug(CPUMBState *env) diff --git a/target-mips/op_helper.c b/target-mips/op_helper.c index 8c050fc247..c65350187f 100644 --- a/target-mips/op_helper.c +++ b/target-mips/op_helper.c @@ -51,7 +51,7 @@ static inline void QEMU_NORETURN do_raise_exception_err(CPUMIPSState *env, cpu_restore_state(env, pc); } - cpu_loop_exit(env); + cpu_loop_exit(cs); } static inline void QEMU_NORETURN do_raise_exception(CPUMIPSState *env, @@ -280,7 +280,7 @@ static inline hwaddr do_translate_address(CPUMIPSState *env, lladdr = cpu_mips_translate_address(env, address, rw); if (lladdr == -1LL) { - cpu_loop_exit(env); + cpu_loop_exit(CPU(mips_env_get_cpu(env))); } else { return lladdr; } diff --git a/target-moxie/helper.c b/target-moxie/helper.c index 06a4c728ee..3994c0910d 100644 --- a/target-moxie/helper.c +++ b/target-moxie/helper.c @@ -59,7 +59,7 @@ void tlb_fill(CPUState *cs, target_ulong addr, int is_write, int mmu_idx, cpu_restore_state(env, retaddr); } } - cpu_loop_exit(env); + cpu_loop_exit(cs); } void helper_raise_exception(CPUMoxieState *env, int ex) @@ -74,7 +74,7 @@ void helper_raise_exception(CPUMoxieState *env, int ex) env->sregs[5] = env->pc; /* Jump the the exception handline routine. */ env->pc = env->sregs[1]; - cpu_loop_exit(env); + cpu_loop_exit(cs); } uint32_t helper_div(CPUMoxieState *env, uint32_t a, uint32_t b) @@ -104,7 +104,7 @@ void helper_debug(CPUMoxieState *env) CPUState *cs = CPU(moxie_env_get_cpu(env)); cs->exception_index = EXCP_DEBUG; - cpu_loop_exit(env); + cpu_loop_exit(cs); } #if defined(CONFIG_USER_ONLY) diff --git a/target-openrisc/exception.c b/target-openrisc/exception.c index b96f3f8963..74652a58f6 100644 --- a/target-openrisc/exception.c +++ b/target-openrisc/exception.c @@ -25,5 +25,5 @@ void QEMU_NORETURN raise_exception(OpenRISCCPU *cpu, uint32_t excp) CPUState *cs = CPU(cpu); cs->exception_index = excp; - cpu_loop_exit(&cpu->env); + cpu_loop_exit(cs); } diff --git a/target-openrisc/mmu_helper.c b/target-openrisc/mmu_helper.c index e3fe6c7127..5f7f6f5ac4 100644 --- a/target-openrisc/mmu_helper.c +++ b/target-openrisc/mmu_helper.c @@ -52,7 +52,7 @@ void tlb_fill(CPUState *cs, target_ulong addr, int is_write, cpu_restore_state(env, retaddr); } /* Raise Exception. */ - cpu_loop_exit(env); + cpu_loop_exit(cs); } } #endif diff --git a/target-ppc/excp_helper.c b/target-ppc/excp_helper.c index a58655b5c7..4a587303a8 100644 --- a/target-ppc/excp_helper.c +++ b/target-ppc/excp_helper.c @@ -823,7 +823,7 @@ void helper_raise_exception_err(CPUPPCState *env, uint32_t exception, #endif cs->exception_index = exception; env->error_code = error_code; - cpu_loop_exit(env); + cpu_loop_exit(cs); } void helper_raise_exception(CPUPPCState *env, uint32_t exception) diff --git a/target-s390x/cc_helper.c b/target-s390x/cc_helper.c index a6d60bf885..d845f20de5 100644 --- a/target-s390x/cc_helper.c +++ b/target-s390x/cc_helper.c @@ -548,7 +548,7 @@ uint32_t HELPER(calc_cc)(CPUS390XState *env, uint32_t cc_op, uint64_t src, void HELPER(load_psw)(CPUS390XState *env, uint64_t mask, uint64_t addr) { load_psw(env, mask, addr); - cpu_loop_exit(env); + cpu_loop_exit(CPU(s390_env_get_cpu(env))); } void HELPER(sacf)(CPUS390XState *env, uint64_t a1) diff --git a/target-s390x/mem_helper.c b/target-s390x/mem_helper.c index 1e74e4d7e4..e89fcac4e2 100644 --- a/target-s390x/mem_helper.c +++ b/target-s390x/mem_helper.c @@ -58,7 +58,7 @@ void tlb_fill(CPUState *cs, target_ulong addr, int is_write, int mmu_idx, /* now we have a real cpu fault */ cpu_restore_state(env, retaddr); } - cpu_loop_exit(env); + cpu_loop_exit(cs); } } @@ -971,12 +971,12 @@ static uint32_t mvc_asc(CPUS390XState *env, int64_t l, uint64_t a1, } if (mmu_translate(env, a1 & TARGET_PAGE_MASK, 1, mode1, &dest, &flags)) { - cpu_loop_exit(env); + cpu_loop_exit(CPU(s390_env_get_cpu(env))); } dest |= a1 & ~TARGET_PAGE_MASK; if (mmu_translate(env, a2 & TARGET_PAGE_MASK, 0, mode2, &src, &flags)) { - cpu_loop_exit(env); + cpu_loop_exit(CPU(s390_env_get_cpu(env))); } src |= a2 & ~TARGET_PAGE_MASK; diff --git a/target-s390x/misc_helper.c b/target-s390x/misc_helper.c index 69da9e56a9..2beec61a2b 100644 --- a/target-s390x/misc_helper.c +++ b/target-s390x/misc_helper.c @@ -61,7 +61,7 @@ void QEMU_NORETURN runtime_exception(CPUS390XState *env, int excp, env->int_pgm_ilen = t = get_ilen(t); env->psw.addr += 2 * t; - cpu_loop_exit(env); + cpu_loop_exit(cs); } /* Raise an exception statically from a TB. */ @@ -71,7 +71,7 @@ void HELPER(exception)(CPUS390XState *env, uint32_t excp) HELPER_LOG("%s: exception %d\n", __func__, excp); cs->exception_index = excp; - cpu_loop_exit(env); + cpu_loop_exit(cs); } #ifndef CONFIG_USER_ONLY @@ -93,7 +93,7 @@ void program_interrupt(CPUS390XState *env, uint32_t code, int ilen) env->int_pgm_code = code; env->int_pgm_ilen = ilen; cs->exception_index = EXCP_PGM; - cpu_loop_exit(env); + cpu_loop_exit(cs); } } @@ -456,11 +456,11 @@ uint32_t HELPER(sigp)(CPUS390XState *env, uint64_t order_code, uint32_t r1, #if !defined(CONFIG_USER_ONLY) case SIGP_RESTART: qemu_system_reset_request(); - cpu_loop_exit(env); + cpu_loop_exit(CPU(s390_env_get_cpu(env))); break; case SIGP_STOP: qemu_system_shutdown_request(); - cpu_loop_exit(env); + cpu_loop_exit(CPU(s390_env_get_cpu(env))); break; #endif default: diff --git a/target-sh4/op_helper.c b/target-sh4/op_helper.c index 6e527cfcf3..271401f699 100644 --- a/target-sh4/op_helper.c +++ b/target-sh4/op_helper.c @@ -52,7 +52,7 @@ void tlb_fill(CPUState *cs, target_ulong addr, int is_write, int mmu_idx, if (retaddr) { cpu_restore_state(env, retaddr); } - cpu_loop_exit(env); + cpu_loop_exit(cs); } } @@ -77,7 +77,7 @@ static inline void QEMU_NORETURN raise_exception(CPUSH4State *env, int index, if (retaddr) { cpu_restore_state(env, retaddr); } - cpu_loop_exit(env); + cpu_loop_exit(cs); } void helper_raise_illegal_instruction(CPUSH4State *env) diff --git a/target-sparc/helper.c b/target-sparc/helper.c index a393ef0a48..fb5f6ecd38 100644 --- a/target-sparc/helper.c +++ b/target-sparc/helper.c @@ -27,7 +27,7 @@ void helper_raise_exception(CPUSPARCState *env, int tt) CPUState *cs = CPU(sparc_env_get_cpu(env)); cs->exception_index = tt; - cpu_loop_exit(env); + cpu_loop_exit(cs); } void helper_debug(CPUSPARCState *env) @@ -35,7 +35,7 @@ void helper_debug(CPUSPARCState *env) CPUState *cs = CPU(sparc_env_get_cpu(env)); cs->exception_index = EXCP_DEBUG; - cpu_loop_exit(env); + cpu_loop_exit(cs); } #ifdef TARGET_SPARC64 @@ -239,6 +239,6 @@ void helper_power_down(CPUSPARCState *env) cs->exception_index = EXCP_HLT; env->pc = env->npc; env->npc = env->pc + 4; - cpu_loop_exit(env); + cpu_loop_exit(cs); } #endif diff --git a/target-sparc/ldst_helper.c b/target-sparc/ldst_helper.c index 32d0bfda18..8302bb14c2 100644 --- a/target-sparc/ldst_helper.c +++ b/target-sparc/ldst_helper.c @@ -2451,7 +2451,7 @@ void tlb_fill(CPUState *cs, target_ulong addr, int is_write, int mmu_idx, if (retaddr) { cpu_restore_state(env, retaddr); } - cpu_loop_exit(env); + cpu_loop_exit(cs); } } #endif diff --git a/target-unicore32/op_helper.c b/target-unicore32/op_helper.c index 3efc6a80a4..c2bf834c27 100644 --- a/target-unicore32/op_helper.c +++ b/target-unicore32/op_helper.c @@ -19,7 +19,7 @@ void HELPER(exception)(CPUUniCore32State *env, uint32_t excp) CPUState *cs = CPU(uc32_env_get_cpu(env)); cs->exception_index = excp; - cpu_loop_exit(env); + cpu_loop_exit(cs); } static target_ulong asr_read(CPUUniCore32State *env) @@ -271,7 +271,7 @@ void tlb_fill(CPUState *cs, target_ulong addr, int is_write, /* now we have a real cpu fault */ cpu_restore_state(env, retaddr); } - cpu_loop_exit(env); + cpu_loop_exit(cs); } } #endif diff --git a/target-xtensa/op_helper.c b/target-xtensa/op_helper.c index 1c80e310ab..42653784cd 100644 --- a/target-xtensa/op_helper.c +++ b/target-xtensa/op_helper.c @@ -105,7 +105,7 @@ void HELPER(exception)(CPUXtensaState *env, uint32_t excp) if (excp == EXCP_DEBUG) { env->exception_taken = 0; } - cpu_loop_exit(env); + cpu_loop_exit(cs); } void HELPER(exception_cause)(CPUXtensaState *env, uint32_t pc, uint32_t cause) @@ -391,7 +391,7 @@ void HELPER(waiti)(CPUXtensaState *env, uint32_t pc, uint32_t intlevel) (intlevel << PS_INTLEVEL_SHIFT); check_interrupts(env); if (env->pending_irq_level) { - cpu_loop_exit(env); + cpu_loop_exit(CPU(xtensa_env_get_cpu(env))); return; } diff --git a/user-exec.c b/user-exec.c index dbb9c8d0a7..e149c9732f 100644 --- a/user-exec.c +++ b/user-exec.c @@ -40,12 +40,12 @@ static void exception_action(CPUArchState *env1) { -#if defined(TARGET_I386) CPUState *cpu = ENV_GET_CPU(env1); +#if defined(TARGET_I386) raise_exception_err(env1, cpu->exception_index, env1->error_code); #else - cpu_loop_exit(env1); + cpu_loop_exit(cpu); #endif } -- cgit 1.4.1 From 3f38f309b22d9a30b5b427501eb3d522c439482e Mon Sep 17 00:00:00 2001 From: Andreas Färber Date: Sun, 1 Sep 2013 16:51:34 +0200 Subject: translate-all: Change cpu_restore_state() argument to CPUState MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This lets us drop some local variables in tlb_fill() functions. Signed-off-by: Andreas Färber --- hw/i386/kvmvapic.c | 2 +- include/exec/exec-all.h | 2 +- target-alpha/helper.c | 2 +- target-alpha/mem_helper.c | 7 ++----- target-arm/op_helper.c | 2 +- target-cris/op_helper.c | 2 +- target-i386/helper.c | 2 +- target-i386/mem_helper.c | 2 +- target-lm32/op_helper.c | 5 +---- target-m68k/op_helper.c | 5 +---- target-microblaze/op_helper.c | 5 +---- target-mips/op_helper.c | 2 +- target-moxie/helper.c | 6 ++---- target-openrisc/mmu_helper.c | 5 +---- target-ppc/mmu_helper.c | 2 +- target-s390x/mem_helper.c | 5 +---- target-s390x/misc_helper.c | 2 +- target-sh4/op_helper.c | 7 ++----- target-sparc/helper.c | 20 ++++++++++++++------ target-sparc/ldst_helper.c | 8 +++----- target-unicore32/op_helper.c | 5 +---- target-xtensa/op_helper.c | 6 ++++-- translate-all.c | 3 ++- user-exec.c | 2 +- 24 files changed, 46 insertions(+), 63 deletions(-) (limited to 'include/exec') diff --git a/hw/i386/kvmvapic.c b/hw/i386/kvmvapic.c index 6cf5d41155..39d516a46e 100644 --- a/hw/i386/kvmvapic.c +++ b/hw/i386/kvmvapic.c @@ -406,7 +406,7 @@ static void patch_instruction(VAPICROMState *s, X86CPU *cpu, target_ulong ip) } if (!kvm_enabled()) { - cpu_restore_state(env, cs->mem_io_pc); + cpu_restore_state(cs, cs->mem_io_pc); cpu_get_tb_cpu_state(env, ¤t_pc, ¤t_cs_base, ¤t_flags); } diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index 80277eac32..cf5cd7100f 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -80,7 +80,7 @@ void restore_state_to_opc(CPUArchState *env, struct TranslationBlock *tb, void cpu_gen_init(void); int cpu_gen_code(CPUArchState *env, struct TranslationBlock *tb, int *gen_code_size_ptr); -bool cpu_restore_state(CPUArchState *env, uintptr_t searched_pc); +bool cpu_restore_state(CPUState *cpu, uintptr_t searched_pc); void page_size_init(void); void QEMU_NORETURN cpu_resume_from_signal(CPUArchState *env1, void *puc); diff --git a/target-alpha/helper.c b/target-alpha/helper.c index 45f73e0ea2..305dd67b84 100644 --- a/target-alpha/helper.c +++ b/target-alpha/helper.c @@ -526,7 +526,7 @@ void QEMU_NORETURN dynamic_excp(CPUAlphaState *env, uintptr_t retaddr, cs->exception_index = excp; env->error_code = error; if (retaddr) { - cpu_restore_state(env, retaddr); + cpu_restore_state(cs, retaddr); } cpu_loop_exit(cs); } diff --git a/target-alpha/mem_helper.c b/target-alpha/mem_helper.c index 1957c566b9..5964bdcda8 100644 --- a/target-alpha/mem_helper.c +++ b/target-alpha/mem_helper.c @@ -105,7 +105,7 @@ static void do_unaligned_access(CPUAlphaState *env, target_ulong addr, uint32_t insn; if (retaddr) { - cpu_restore_state(env, retaddr); + cpu_restore_state(cs, retaddr); } pc = env->pc; @@ -159,11 +159,8 @@ void tlb_fill(CPUState *cs, target_ulong addr, int is_write, ret = alpha_cpu_handle_mmu_fault(cs, addr, is_write, mmu_idx); if (unlikely(ret != 0)) { - AlphaCPU *cpu = ALPHA_CPU(cs); - CPUAlphaState *env = &cpu->env; - if (retaddr) { - cpu_restore_state(env, retaddr); + cpu_restore_state(cs, retaddr); } /* Exception index and error code are already set */ cpu_loop_exit(cs); diff --git a/target-arm/op_helper.c b/target-arm/op_helper.c index f8e535e8ce..21ff58e754 100644 --- a/target-arm/op_helper.c +++ b/target-arm/op_helper.c @@ -87,7 +87,7 @@ void tlb_fill(CPUState *cs, target_ulong addr, int is_write, int mmu_idx, if (retaddr) { /* now we have a real cpu fault */ - cpu_restore_state(env, retaddr); + cpu_restore_state(cs, retaddr); } raise_exception(env, cs->exception_index); } diff --git a/target-cris/op_helper.c b/target-cris/op_helper.c index d80b6c966d..d28bd61778 100644 --- a/target-cris/op_helper.c +++ b/target-cris/op_helper.c @@ -67,7 +67,7 @@ void tlb_fill(CPUState *cs, target_ulong addr, int is_write, int mmu_idx, if (unlikely(ret)) { if (retaddr) { /* now we have a real cpu fault */ - if (cpu_restore_state(env, retaddr)) { + if (cpu_restore_state(cs, retaddr)) { /* Evaluate flags after retranslation. */ helper_top_evaluate_flags(env); } diff --git a/target-i386/helper.c b/target-i386/helper.c index 59736d7a4f..cb29aa4b0e 100644 --- a/target-i386/helper.c +++ b/target-i386/helper.c @@ -1263,7 +1263,7 @@ void cpu_report_tpr_access(CPUX86State *env, TPRAccess access) cpu_interrupt(cs, CPU_INTERRUPT_TPR); } else { - cpu_restore_state(env, cs->mem_io_pc); + cpu_restore_state(cs, cs->mem_io_pc); apic_handle_tpr_access_report(cpu->apic_state, env->eip, access); } diff --git a/target-i386/mem_helper.c b/target-i386/mem_helper.c index 2f0691be8f..b3b811bc8c 100644 --- a/target-i386/mem_helper.c +++ b/target-i386/mem_helper.c @@ -145,7 +145,7 @@ void tlb_fill(CPUState *cs, target_ulong addr, int is_write, int mmu_idx, if (retaddr) { /* now we have a real cpu fault */ - cpu_restore_state(env, retaddr); + cpu_restore_state(cs, retaddr); } raise_exception_err(env, cs->exception_index, env->error_code); } diff --git a/target-lm32/op_helper.c b/target-lm32/op_helper.c index f0859aab6d..2f36b7b053 100644 --- a/target-lm32/op_helper.c +++ b/target-lm32/op_helper.c @@ -160,12 +160,9 @@ void tlb_fill(CPUState *cs, target_ulong addr, int is_write, int mmu_idx, ret = lm32_cpu_handle_mmu_fault(cs, addr, is_write, mmu_idx); if (unlikely(ret)) { - LM32CPU *cpu = LM32_CPU(cs); - CPULM32State *env = &cpu->env; - if (retaddr) { /* now we have a real cpu fault */ - cpu_restore_state(env, retaddr); + cpu_restore_state(cs, retaddr); } cpu_loop_exit(cs); } diff --git a/target-m68k/op_helper.c b/target-m68k/op_helper.c index d6268cd6b9..06302b1071 100644 --- a/target-m68k/op_helper.c +++ b/target-m68k/op_helper.c @@ -60,12 +60,9 @@ void tlb_fill(CPUState *cs, target_ulong addr, int is_write, int mmu_idx, ret = m68k_cpu_handle_mmu_fault(cs, addr, is_write, mmu_idx); if (unlikely(ret)) { - M68kCPU *cpu = M68K_CPU(cs); - CPUM68KState *env = &cpu->env; - if (retaddr) { /* now we have a real cpu fault */ - cpu_restore_state(env, retaddr); + cpu_restore_state(cs, retaddr); } cpu_loop_exit(cs); } diff --git a/target-microblaze/op_helper.c b/target-microblaze/op_helper.c index f47613241d..f8fb7f9169 100644 --- a/target-microblaze/op_helper.c +++ b/target-microblaze/op_helper.c @@ -49,12 +49,9 @@ void tlb_fill(CPUState *cs, target_ulong addr, int is_write, int mmu_idx, ret = mb_cpu_handle_mmu_fault(cs, addr, is_write, mmu_idx); if (unlikely(ret)) { - MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs); - CPUMBState *env = &cpu->env; - if (retaddr) { /* now we have a real cpu fault */ - cpu_restore_state(env, retaddr); + cpu_restore_state(cs, retaddr); } cpu_loop_exit(cs); } diff --git a/target-mips/op_helper.c b/target-mips/op_helper.c index c65350187f..de5a22329a 100644 --- a/target-mips/op_helper.c +++ b/target-mips/op_helper.c @@ -48,7 +48,7 @@ static inline void QEMU_NORETURN do_raise_exception_err(CPUMIPSState *env, if (pc) { /* now we have a real cpu fault */ - cpu_restore_state(env, pc); + cpu_restore_state(cs, pc); } cpu_loop_exit(cs); diff --git a/target-moxie/helper.c b/target-moxie/helper.c index 3994c0910d..04b36b78b5 100644 --- a/target-moxie/helper.c +++ b/target-moxie/helper.c @@ -49,14 +49,12 @@ void tlb_fill(CPUState *cs, target_ulong addr, int is_write, int mmu_idx, uintptr_t retaddr) { - MoxieCPU *cpu = MOXIE_CPU(cs); - CPUMoxieState *env = &cpu->env; int ret; ret = moxie_cpu_handle_mmu_fault(cs, addr, is_write, mmu_idx); if (unlikely(ret)) { if (retaddr) { - cpu_restore_state(env, retaddr); + cpu_restore_state(cs, retaddr); } } cpu_loop_exit(cs); @@ -70,7 +68,7 @@ void helper_raise_exception(CPUMoxieState *env, int ex) /* Stash the exception type. */ env->sregs[2] = ex; /* Stash the address where the exception occurred. */ - cpu_restore_state(env, GETPC()); + cpu_restore_state(cs, GETPC()); env->sregs[5] = env->pc; /* Jump the the exception handline routine. */ env->pc = env->sregs[1]; diff --git a/target-openrisc/mmu_helper.c b/target-openrisc/mmu_helper.c index 5f7f6f5ac4..fb457c76af 100644 --- a/target-openrisc/mmu_helper.c +++ b/target-openrisc/mmu_helper.c @@ -44,12 +44,9 @@ void tlb_fill(CPUState *cs, target_ulong addr, int is_write, ret = openrisc_cpu_handle_mmu_fault(cs, addr, is_write, mmu_idx); if (ret) { - OpenRISCCPU *cpu = OPENRISC_CPU(cs); - CPUOpenRISCState *env = &cpu->env; - if (retaddr) { /* now we have a real cpu fault. */ - cpu_restore_state(env, retaddr); + cpu_restore_state(cs, retaddr); } /* Raise Exception. */ cpu_loop_exit(cs); diff --git a/target-ppc/mmu_helper.c b/target-ppc/mmu_helper.c index c0421848b1..2a94f3d67f 100644 --- a/target-ppc/mmu_helper.c +++ b/target-ppc/mmu_helper.c @@ -2909,7 +2909,7 @@ void tlb_fill(CPUState *cs, target_ulong addr, int is_write, int mmu_idx, if (unlikely(ret != 0)) { if (likely(retaddr)) { /* now we have a real cpu fault */ - cpu_restore_state(env, retaddr); + cpu_restore_state(cs, retaddr); } helper_raise_exception_err(env, cs->exception_index, env->error_code); } diff --git a/target-s390x/mem_helper.c b/target-s390x/mem_helper.c index e89fcac4e2..e1c2ac04d1 100644 --- a/target-s390x/mem_helper.c +++ b/target-s390x/mem_helper.c @@ -51,12 +51,9 @@ void tlb_fill(CPUState *cs, target_ulong addr, int is_write, int mmu_idx, ret = s390_cpu_handle_mmu_fault(cs, addr, is_write, mmu_idx); if (unlikely(ret != 0)) { - S390CPU *cpu = S390_CPU(cs); - CPUS390XState *env = &cpu->env; - if (likely(retaddr)) { /* now we have a real cpu fault */ - cpu_restore_state(env, retaddr); + cpu_restore_state(cs, retaddr); } cpu_loop_exit(cs); } diff --git a/target-s390x/misc_helper.c b/target-s390x/misc_helper.c index 2beec61a2b..942b5f7487 100644 --- a/target-s390x/misc_helper.c +++ b/target-s390x/misc_helper.c @@ -54,7 +54,7 @@ void QEMU_NORETURN runtime_exception(CPUS390XState *env, int excp, env->int_pgm_code = excp; /* Use the (ultimate) callers address to find the insn that trapped. */ - cpu_restore_state(env, retaddr); + cpu_restore_state(cs, retaddr); /* Advance past the insn. */ t = cpu_ldub_code(env, env->psw.addr); diff --git a/target-sh4/op_helper.c b/target-sh4/op_helper.c index 271401f699..b3ce7bad53 100644 --- a/target-sh4/op_helper.c +++ b/target-sh4/op_helper.c @@ -46,11 +46,8 @@ void tlb_fill(CPUState *cs, target_ulong addr, int is_write, int mmu_idx, ret = superh_cpu_handle_mmu_fault(cs, addr, is_write, mmu_idx); if (ret) { /* now we have a real cpu fault */ - SuperHCPU *cpu = SUPERH_CPU(cs); - CPUSH4State *env = &cpu->env; - if (retaddr) { - cpu_restore_state(env, retaddr); + cpu_restore_state(cs, retaddr); } cpu_loop_exit(cs); } @@ -75,7 +72,7 @@ static inline void QEMU_NORETURN raise_exception(CPUSH4State *env, int index, cs->exception_index = index; if (retaddr) { - cpu_restore_state(env, retaddr); + cpu_restore_state(cs, retaddr); } cpu_loop_exit(cs); } diff --git a/target-sparc/helper.c b/target-sparc/helper.c index fb5f6ecd38..f3c7fbf993 100644 --- a/target-sparc/helper.c +++ b/target-sparc/helper.c @@ -71,6 +71,7 @@ void helper_tick_set_limit(void *opaque, uint64_t limit) static target_ulong helper_udiv_common(CPUSPARCState *env, target_ulong a, target_ulong b, int cc) { + SPARCCPU *cpu = sparc_env_get_cpu(env); int overflow = 0; uint64_t x0; uint32_t x1; @@ -79,7 +80,7 @@ static target_ulong helper_udiv_common(CPUSPARCState *env, target_ulong a, x1 = (b & 0xffffffff); if (x1 == 0) { - cpu_restore_state(env, GETPC()); + cpu_restore_state(CPU(cpu), GETPC()); helper_raise_exception(env, TT_DIV_ZERO); } @@ -110,6 +111,7 @@ target_ulong helper_udiv_cc(CPUSPARCState *env, target_ulong a, target_ulong b) static target_ulong helper_sdiv_common(CPUSPARCState *env, target_ulong a, target_ulong b, int cc) { + SPARCCPU *cpu = sparc_env_get_cpu(env); int overflow = 0; int64_t x0; int32_t x1; @@ -118,7 +120,7 @@ static target_ulong helper_sdiv_common(CPUSPARCState *env, target_ulong a, x1 = (b & 0xffffffff); if (x1 == 0) { - cpu_restore_state(env, GETPC()); + cpu_restore_state(CPU(cpu), GETPC()); helper_raise_exception(env, TT_DIV_ZERO); } @@ -151,7 +153,9 @@ int64_t helper_sdivx(CPUSPARCState *env, int64_t a, int64_t b) { if (b == 0) { /* Raise divide by zero trap. */ - cpu_restore_state(env, GETPC()); + SPARCCPU *cpu = sparc_env_get_cpu(env); + + cpu_restore_state(CPU(cpu), GETPC()); helper_raise_exception(env, TT_DIV_ZERO); } else if (b == -1) { /* Avoid overflow trap with i386 divide insn. */ @@ -165,7 +169,9 @@ uint64_t helper_udivx(CPUSPARCState *env, uint64_t a, uint64_t b) { if (b == 0) { /* Raise divide by zero trap. */ - cpu_restore_state(env, GETPC()); + SPARCCPU *cpu = sparc_env_get_cpu(env); + + cpu_restore_state(CPU(cpu), GETPC()); helper_raise_exception(env, TT_DIV_ZERO); } return a / b; @@ -175,6 +181,7 @@ uint64_t helper_udivx(CPUSPARCState *env, uint64_t a, uint64_t b) target_ulong helper_taddcctv(CPUSPARCState *env, target_ulong src1, target_ulong src2) { + SPARCCPU *cpu = sparc_env_get_cpu(env); target_ulong dst; /* Tag overflow occurs if either input has bits 0 or 1 set. */ @@ -197,13 +204,14 @@ target_ulong helper_taddcctv(CPUSPARCState *env, target_ulong src1, return dst; tag_overflow: - cpu_restore_state(env, GETPC()); + cpu_restore_state(CPU(cpu), GETPC()); helper_raise_exception(env, TT_TOVF); } target_ulong helper_tsubcctv(CPUSPARCState *env, target_ulong src1, target_ulong src2) { + SPARCCPU *cpu = sparc_env_get_cpu(env); target_ulong dst; /* Tag overflow occurs if either input has bits 0 or 1 set. */ @@ -226,7 +234,7 @@ target_ulong helper_tsubcctv(CPUSPARCState *env, target_ulong src1, return dst; tag_overflow: - cpu_restore_state(env, GETPC()); + cpu_restore_state(CPU(cpu), GETPC()); helper_raise_exception(env, TT_TOVF); } diff --git a/target-sparc/ldst_helper.c b/target-sparc/ldst_helper.c index 8302bb14c2..1f6df49e88 100644 --- a/target-sparc/ldst_helper.c +++ b/target-sparc/ldst_helper.c @@ -2424,12 +2424,13 @@ static void QEMU_NORETURN do_unaligned_access(CPUSPARCState *env, target_ulong addr, int is_write, int is_user, uintptr_t retaddr) { + SPARCCPU *cpu = sparc_env_get_cpu(env); #ifdef DEBUG_UNALIGNED printf("Unaligned access to 0x" TARGET_FMT_lx " from 0x" TARGET_FMT_lx "\n", addr, env->pc); #endif if (retaddr) { - cpu_restore_state(env, retaddr); + cpu_restore_state(CPU(cpu), retaddr); } helper_raise_exception(env, TT_UNALIGNED); } @@ -2445,11 +2446,8 @@ void tlb_fill(CPUState *cs, target_ulong addr, int is_write, int mmu_idx, ret = sparc_cpu_handle_mmu_fault(cs, addr, is_write, mmu_idx); if (ret) { - SPARCCPU *cpu = SPARC_CPU(cs); - CPUSPARCState *env = &cpu->env; - if (retaddr) { - cpu_restore_state(env, retaddr); + cpu_restore_state(cs, retaddr); } cpu_loop_exit(cs); } diff --git a/target-unicore32/op_helper.c b/target-unicore32/op_helper.c index c2bf834c27..4c6950d506 100644 --- a/target-unicore32/op_helper.c +++ b/target-unicore32/op_helper.c @@ -264,12 +264,9 @@ void tlb_fill(CPUState *cs, target_ulong addr, int is_write, ret = uc32_cpu_handle_mmu_fault(cs, addr, is_write, mmu_idx); if (unlikely(ret)) { - UniCore32CPU *cpu = UNICORE32_CPU(cs); - CPUUniCore32State *env = &cpu->env; - if (retaddr) { /* now we have a real cpu fault */ - cpu_restore_state(env, retaddr); + cpu_restore_state(cs, retaddr); } cpu_loop_exit(cs); } diff --git a/target-xtensa/op_helper.c b/target-xtensa/op_helper.c index 42653784cd..8233443eb0 100644 --- a/target-xtensa/op_helper.c +++ b/target-xtensa/op_helper.c @@ -52,9 +52,11 @@ static void do_unaligned_access(CPUXtensaState *env, static void do_unaligned_access(CPUXtensaState *env, target_ulong addr, int is_write, int is_user, uintptr_t retaddr) { + XtensaCPU *cpu = xtensa_env_get_cpu(env); + if (xtensa_option_enabled(env->config, XTENSA_OPTION_UNALIGNED_EXCEPTION) && !xtensa_option_enabled(env->config, XTENSA_OPTION_HW_ALIGNMENT)) { - cpu_restore_state(env, retaddr); + cpu_restore_state(CPU(cpu), retaddr); HELPER(exception_cause_vaddr)(env, env->pc, LOAD_STORE_ALIGNMENT_CAUSE, addr); } @@ -80,7 +82,7 @@ void tlb_fill(CPUState *cs, paddr & TARGET_PAGE_MASK, access, mmu_idx, page_size); } else { - cpu_restore_state(env, retaddr); + cpu_restore_state(cs, retaddr); HELPER(exception_cause_vaddr)(env, env->pc, ret, vaddr); } } diff --git a/translate-all.c b/translate-all.c index c067011684..70d8229451 100644 --- a/translate-all.c +++ b/translate-all.c @@ -253,8 +253,9 @@ static int cpu_restore_state_from_tb(TranslationBlock *tb, CPUArchState *env, return 0; } -bool cpu_restore_state(CPUArchState *env, uintptr_t retaddr) +bool cpu_restore_state(CPUState *cpu, uintptr_t retaddr) { + CPUArchState *env = cpu->env_ptr; TranslationBlock *tb; tb = tb_find_pc(retaddr); diff --git a/user-exec.c b/user-exec.c index e149c9732f..75c6d5486b 100644 --- a/user-exec.c +++ b/user-exec.c @@ -117,7 +117,7 @@ static inline int handle_cpu_signal(uintptr_t pc, unsigned long address, return 1; /* the MMU fault was handled without causing real CPU fault */ } /* now we have a real cpu fault */ - cpu_restore_state(env, pc); + cpu_restore_state(cpu, pc); /* we restore the process signal mask as the sigreturn should do it (XXX: use sigsetjmp) */ -- cgit 1.4.1 From 90b40a696a6bcfac88529930d4d1e1599878dae3 Mon Sep 17 00:00:00 2001 From: Andreas Färber Date: Sun, 1 Sep 2013 17:21:47 +0200 Subject: translate-all: Change cpu_io_recompile() argument to CPUState MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Andreas Färber --- include/exec/exec-all.h | 2 +- include/exec/softmmu_template.h | 4 ++-- translate-all.c | 4 ++-- 3 files changed, 5 insertions(+), 5 deletions(-) (limited to 'include/exec') diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index cf5cd7100f..727dc3c4a4 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -84,7 +84,7 @@ bool cpu_restore_state(CPUState *cpu, uintptr_t searched_pc); void page_size_init(void); void QEMU_NORETURN cpu_resume_from_signal(CPUArchState *env1, void *puc); -void QEMU_NORETURN cpu_io_recompile(CPUArchState *env, uintptr_t retaddr); +void QEMU_NORETURN cpu_io_recompile(CPUState *cpu, uintptr_t retaddr); TranslationBlock *tb_gen_code(CPUArchState *env, target_ulong pc, target_ulong cs_base, int flags, int cflags); diff --git a/include/exec/softmmu_template.h b/include/exec/softmmu_template.h index 8603933dcb..73ed7cf921 100644 --- a/include/exec/softmmu_template.h +++ b/include/exec/softmmu_template.h @@ -128,7 +128,7 @@ static inline DATA_TYPE glue(io_read, SUFFIX)(CPUArchState *env, physaddr = (physaddr & TARGET_PAGE_MASK) + addr; cpu->mem_io_pc = retaddr; if (mr != &io_mem_rom && mr != &io_mem_notdirty && !cpu_can_do_io(cpu)) { - cpu_io_recompile(env, retaddr); + cpu_io_recompile(cpu, retaddr); } cpu->mem_io_vaddr = addr; @@ -334,7 +334,7 @@ static inline void glue(io_write, SUFFIX)(CPUArchState *env, physaddr = (physaddr & TARGET_PAGE_MASK) + addr; if (mr != &io_mem_rom && mr != &io_mem_notdirty && !cpu_can_do_io(cpu)) { - cpu_io_recompile(env, retaddr); + cpu_io_recompile(cpu, retaddr); } cpu->mem_io_vaddr = addr; diff --git a/translate-all.c b/translate-all.c index 82d5fa40b3..83c7907b8f 100644 --- a/translate-all.c +++ b/translate-all.c @@ -1419,9 +1419,9 @@ CPUInterruptHandler cpu_interrupt_handler = tcg_handle_interrupt; /* in deterministic execution mode, instructions doing device I/Os must be at the end of the TB */ -void cpu_io_recompile(CPUArchState *env, uintptr_t retaddr) +void cpu_io_recompile(CPUState *cpu, uintptr_t retaddr) { - CPUState *cpu = ENV_GET_CPU(env); + CPUArchState *env = cpu->env_ptr; TranslationBlock *tb; uint32_t n, cflags; target_ulong pc, cs_base; -- cgit 1.4.1 From 648f034c6cd81c64d93a1cfd7bb262006f560649 Mon Sep 17 00:00:00 2001 From: Andreas Färber Date: Sun, 1 Sep 2013 17:43:17 +0200 Subject: translate-all: Change tb_gen_code() argument to CPUState MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Andreas Färber --- cpu-exec.c | 4 ++-- exec.c | 2 +- hw/i386/kvmvapic.c | 2 +- include/exec/exec-all.h | 2 +- translate-all.c | 9 +++++---- 5 files changed, 10 insertions(+), 9 deletions(-) (limited to 'include/exec') diff --git a/cpu-exec.c b/cpu-exec.c index 192620f37b..c689ef9882 100644 --- a/cpu-exec.c +++ b/cpu-exec.c @@ -103,7 +103,7 @@ static void cpu_exec_nocache(CPUArchState *env, int max_cycles, if (max_cycles > CF_COUNT_MASK) max_cycles = CF_COUNT_MASK; - tb = tb_gen_code(env, orig_tb->pc, orig_tb->cs_base, orig_tb->flags, + tb = tb_gen_code(cpu, orig_tb->pc, orig_tb->cs_base, orig_tb->flags, max_cycles); cpu->current_tb = tb; /* execute the generated code */ @@ -156,7 +156,7 @@ static TranslationBlock *tb_find_slow(CPUArchState *env, } not_found: /* if no translated code available, then translate it now */ - tb = tb_gen_code(env, pc, cs_base, flags, 0); + tb = tb_gen_code(cpu, pc, cs_base, flags, 0); found: /* Move the last found TB to the head of the list */ diff --git a/exec.c b/exec.c index 7f945818f9..6f8b2ca7b8 100644 --- a/exec.c +++ b/exec.c @@ -1611,7 +1611,7 @@ static void check_watchpoint(int offset, int len_mask, int flags) cpu_loop_exit(cpu); } else { cpu_get_tb_cpu_state(env, &pc, &cs_base, &cpu_flags); - tb_gen_code(env, pc, cs_base, cpu_flags, 1); + tb_gen_code(cpu, pc, cs_base, cpu_flags, 1); cpu_resume_from_signal(env, NULL); } } diff --git a/hw/i386/kvmvapic.c b/hw/i386/kvmvapic.c index 39d516a46e..2a9d87a5d8 100644 --- a/hw/i386/kvmvapic.c +++ b/hw/i386/kvmvapic.c @@ -448,7 +448,7 @@ static void patch_instruction(VAPICROMState *s, X86CPU *cpu, target_ulong ip) if (!kvm_enabled()) { cs->current_tb = NULL; - tb_gen_code(env, current_pc, current_cs_base, current_flags, 1); + tb_gen_code(cs, current_pc, current_cs_base, current_flags, 1); cpu_resume_from_signal(env, NULL); } } diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index 727dc3c4a4..a3e7faa416 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -85,7 +85,7 @@ void page_size_init(void); void QEMU_NORETURN cpu_resume_from_signal(CPUArchState *env1, void *puc); void QEMU_NORETURN cpu_io_recompile(CPUState *cpu, uintptr_t retaddr); -TranslationBlock *tb_gen_code(CPUArchState *env, +TranslationBlock *tb_gen_code(CPUState *cpu, target_ulong pc, target_ulong cs_base, int flags, int cflags); void cpu_exec_init(CPUArchState *env); diff --git a/translate-all.c b/translate-all.c index 83c7907b8f..a7130a5a43 100644 --- a/translate-all.c +++ b/translate-all.c @@ -938,10 +938,11 @@ static void build_page_bitmap(PageDesc *p) } } -TranslationBlock *tb_gen_code(CPUArchState *env, +TranslationBlock *tb_gen_code(CPUState *cpu, target_ulong pc, target_ulong cs_base, int flags, int cflags) { + CPUArchState *env = cpu->env_ptr; TranslationBlock *tb; uint8_t *tc_ptr; tb_page_addr_t phys_pc, phys_page2; @@ -1111,7 +1112,7 @@ void tb_invalidate_phys_page_range(tb_page_addr_t start, tb_page_addr_t end, modifying the memory. It will ensure that it cannot modify itself */ cpu->current_tb = NULL; - tb_gen_code(env, current_pc, current_cs_base, current_flags, 1); + tb_gen_code(cpu, current_pc, current_cs_base, current_flags, 1); cpu_resume_from_signal(env, NULL); } #endif @@ -1208,7 +1209,7 @@ static void tb_invalidate_phys_page(tb_page_addr_t addr, modifying the memory. It will ensure that it cannot modify itself */ cpu->current_tb = NULL; - tb_gen_code(env, current_pc, current_cs_base, current_flags, 1); + tb_gen_code(cpu, current_pc, current_cs_base, current_flags, 1); if (locked) { mmap_unlock(); } @@ -1469,7 +1470,7 @@ void cpu_io_recompile(CPUState *cpu, uintptr_t retaddr) tb_phys_invalidate(tb, -1); /* FIXME: In theory this could raise an exception. In practice we have already translated the block once so it's probably ok. */ - tb_gen_code(env, pc, cs_base, flags, cflags); + tb_gen_code(cpu, pc, cs_base, flags, cflags); /* TODO: If env->pc != tb->pc (i.e. the faulting instruction was not the first in the TB) then we end up generating a whole new TB and repeating the fault, which is horribly inefficient. -- cgit 1.4.1 From 611d4f996f650294483ff4b01c3140651e2dd29c Mon Sep 17 00:00:00 2001 From: Andreas Färber Date: Sun, 1 Sep 2013 17:52:07 +0200 Subject: translate-all: Change tb_flush_jmp_cache() argument to CPUState MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Andreas Färber --- cputlb.c | 2 +- include/exec/cputlb.h | 2 +- translate-all.c | 3 +-- 3 files changed, 3 insertions(+), 4 deletions(-) (limited to 'include/exec') diff --git a/cputlb.c b/cputlb.c index 0eb1801cc2..6b2cdb201a 100644 --- a/cputlb.c +++ b/cputlb.c @@ -106,7 +106,7 @@ void tlb_flush_page(CPUArchState *env, target_ulong addr) tlb_flush_entry(&env->tlb_table[mmu_idx][i], addr); } - tb_flush_jmp_cache(env, addr); + tb_flush_jmp_cache(cpu, addr); } /* update the TLBs so that writes to code in the virtual page 'addr' diff --git a/include/exec/cputlb.h b/include/exec/cputlb.h index e21cb60442..e1eb4d92df 100644 --- a/include/exec/cputlb.h +++ b/include/exec/cputlb.h @@ -31,7 +31,7 @@ void tlb_set_dirty(CPUArchState *env, target_ulong vaddr); extern int tlb_flush_count; /* exec.c */ -void tb_flush_jmp_cache(CPUArchState *env, target_ulong addr); +void tb_flush_jmp_cache(CPUState *cpu, target_ulong addr); MemoryRegionSection * address_space_translate_for_iotlb(AddressSpace *as, hwaddr addr, hwaddr *xlat, diff --git a/translate-all.c b/translate-all.c index a7130a5a43..df85f9f8c5 100644 --- a/translate-all.c +++ b/translate-all.c @@ -1479,9 +1479,8 @@ void cpu_io_recompile(CPUState *cpu, uintptr_t retaddr) cpu_resume_from_signal(env, NULL); } -void tb_flush_jmp_cache(CPUArchState *env, target_ulong addr) +void tb_flush_jmp_cache(CPUState *cpu, target_ulong addr) { - CPUState *cpu = ENV_GET_CPU(env); unsigned int i; /* Discard jump cache entries for any tb which might potentially -- cgit 1.4.1 From 75a34036d43dc961cbef2a4705682d0666caf384 Mon Sep 17 00:00:00 2001 From: Andreas Färber Date: Mon, 2 Sep 2013 16:57:02 +0200 Subject: exec: Change cpu_watchpoint_{insert,remove{,_by_ref,_all}} argument MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Use CPUState. This lets us drop a few local env usages. Signed-off-by: Andreas Färber --- exec.c | 34 +++++++++++++++++----------------- gdbstub.c | 17 +++++++++-------- include/exec/cpu-all.h | 6 ------ include/qom/cpu.h | 7 +++++++ linux-user/main.c | 5 +++-- target-i386/cpu.c | 2 +- target-i386/helper.c | 11 ++++++++--- target-i386/machine.c | 3 ++- target-lm32/helper.c | 7 +++++-- target-xtensa/op_helper.c | 9 ++++++--- 10 files changed, 58 insertions(+), 43 deletions(-) (limited to 'include/exec') diff --git a/exec.c b/exec.c index 6f8b2ca7b8..e89653ecca 100644 --- a/exec.c +++ b/exec.c @@ -33,6 +33,7 @@ #include "hw/xen/xen.h" #include "qemu/timer.h" #include "qemu/config-file.h" +#include "qemu/error-report.h" #include "exec/memory.h" #include "sysemu/dma.h" #include "exec/address-spaces.h" @@ -527,30 +528,30 @@ static void breakpoint_invalidate(CPUState *cpu, target_ulong pc) #endif /* TARGET_HAS_ICE */ #if defined(CONFIG_USER_ONLY) -void cpu_watchpoint_remove_all(CPUArchState *env, int mask) +void cpu_watchpoint_remove_all(CPUState *cpu, int mask) { } -int cpu_watchpoint_insert(CPUArchState *env, target_ulong addr, target_ulong len, +int cpu_watchpoint_insert(CPUState *cpu, vaddr addr, vaddr len, int flags, CPUWatchpoint **watchpoint) { return -ENOSYS; } #else /* Add a watchpoint. */ -int cpu_watchpoint_insert(CPUArchState *env, target_ulong addr, target_ulong len, +int cpu_watchpoint_insert(CPUState *cpu, vaddr addr, vaddr len, int flags, CPUWatchpoint **watchpoint) { - CPUState *cpu = ENV_GET_CPU(env); - target_ulong len_mask = ~(len - 1); + CPUArchState *env = cpu->env_ptr; + vaddr len_mask = ~(len - 1); CPUWatchpoint *wp; /* sanity checks: allow power-of-2 lengths, deny unaligned watchpoints */ if ((len & (len - 1)) || (addr & ~len_mask) || len == 0 || len > TARGET_PAGE_SIZE) { - fprintf(stderr, "qemu: tried to set invalid watchpoint at " - TARGET_FMT_lx ", len=" TARGET_FMT_lu "\n", addr, len); + error_report("tried to set invalid watchpoint at %" + VADDR_PRIx ", len=%" VADDR_PRIu, addr, len); return -EINVAL; } wp = g_malloc(sizeof(*wp)); @@ -574,17 +575,16 @@ int cpu_watchpoint_insert(CPUArchState *env, target_ulong addr, target_ulong len } /* Remove a specific watchpoint. */ -int cpu_watchpoint_remove(CPUArchState *env, target_ulong addr, target_ulong len, +int cpu_watchpoint_remove(CPUState *cpu, vaddr addr, vaddr len, int flags) { - CPUState *cpu = ENV_GET_CPU(env); - target_ulong len_mask = ~(len - 1); + vaddr len_mask = ~(len - 1); CPUWatchpoint *wp; QTAILQ_FOREACH(wp, &cpu->watchpoints, entry) { if (addr == wp->vaddr && len_mask == wp->len_mask && flags == (wp->flags & ~BP_WATCHPOINT_HIT)) { - cpu_watchpoint_remove_by_ref(env, wp); + cpu_watchpoint_remove_by_ref(cpu, wp); return 0; } } @@ -592,9 +592,9 @@ int cpu_watchpoint_remove(CPUArchState *env, target_ulong addr, target_ulong len } /* Remove a specific watchpoint by reference. */ -void cpu_watchpoint_remove_by_ref(CPUArchState *env, CPUWatchpoint *watchpoint) +void cpu_watchpoint_remove_by_ref(CPUState *cpu, CPUWatchpoint *watchpoint) { - CPUState *cpu = ENV_GET_CPU(env); + CPUArchState *env = cpu->env_ptr; QTAILQ_REMOVE(&cpu->watchpoints, watchpoint, entry); @@ -604,14 +604,14 @@ void cpu_watchpoint_remove_by_ref(CPUArchState *env, CPUWatchpoint *watchpoint) } /* Remove all matching watchpoints. */ -void cpu_watchpoint_remove_all(CPUArchState *env, int mask) +void cpu_watchpoint_remove_all(CPUState *cpu, int mask) { - CPUState *cpu = ENV_GET_CPU(env); CPUWatchpoint *wp, *next; QTAILQ_FOREACH_SAFE(wp, &cpu->watchpoints, entry, next) { - if (wp->flags & mask) - cpu_watchpoint_remove_by_ref(env, wp); + if (wp->flags & mask) { + cpu_watchpoint_remove_by_ref(cpu, wp); + } } } #endif diff --git a/gdbstub.c b/gdbstub.c index 0176b3f80e..cd10781c13 100644 --- a/gdbstub.c +++ b/gdbstub.c @@ -657,8 +657,7 @@ static int gdb_breakpoint_insert(target_ulong addr, target_ulong len, int type) case GDB_WATCHPOINT_READ: case GDB_WATCHPOINT_ACCESS: CPU_FOREACH(cpu) { - env = cpu->env_ptr; - err = cpu_watchpoint_insert(env, addr, len, xlat_gdb_type[type], + err = cpu_watchpoint_insert(cpu, addr, len, xlat_gdb_type[type], NULL); if (err) break; @@ -695,8 +694,7 @@ static int gdb_breakpoint_remove(target_ulong addr, target_ulong len, int type) case GDB_WATCHPOINT_READ: case GDB_WATCHPOINT_ACCESS: CPU_FOREACH(cpu) { - env = cpu->env_ptr; - err = cpu_watchpoint_remove(env, addr, len, xlat_gdb_type[type]); + err = cpu_watchpoint_remove(cpu, addr, len, xlat_gdb_type[type]); if (err) break; } @@ -721,7 +719,7 @@ static void gdb_breakpoint_remove_all(void) env = cpu->env_ptr; cpu_breakpoint_remove_all(env, BP_GDB); #ifndef CONFIG_USER_ONLY - cpu_watchpoint_remove_all(env, BP_GDB); + cpu_watchpoint_remove_all(cpu, BP_GDB); #endif } } @@ -1593,13 +1591,16 @@ int gdbserver_start(int port) /* Disable gdb stub for child processes. */ void gdbserver_fork(CPUArchState *env) { + CPUState *cpu = ENV_GET_CPU(env); GDBState *s = gdbserver_state; - if (gdbserver_fd < 0 || s->fd < 0) - return; + + if (gdbserver_fd < 0 || s->fd < 0) { + return; + } close(s->fd); s->fd = -1; cpu_breakpoint_remove_all(env, BP_GDB); - cpu_watchpoint_remove_all(env, BP_GDB); + cpu_watchpoint_remove_all(cpu, BP_GDB); } #else static int gdb_chr_can_receive(void *opaque) diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h index 4cb4b4a53a..ea90aee7fe 100644 --- a/include/exec/cpu-all.h +++ b/include/exec/cpu-all.h @@ -427,12 +427,6 @@ int cpu_breakpoint_insert(CPUArchState *env, target_ulong pc, int flags, int cpu_breakpoint_remove(CPUArchState *env, target_ulong pc, int flags); void cpu_breakpoint_remove_by_ref(CPUArchState *env, CPUBreakpoint *breakpoint); void cpu_breakpoint_remove_all(CPUArchState *env, int mask); -int cpu_watchpoint_insert(CPUArchState *env, target_ulong addr, target_ulong len, - int flags, CPUWatchpoint **watchpoint); -int cpu_watchpoint_remove(CPUArchState *env, target_ulong addr, - target_ulong len, int flags); -void cpu_watchpoint_remove_by_ref(CPUArchState *env, CPUWatchpoint *watchpoint); -void cpu_watchpoint_remove_all(CPUArchState *env, int mask); #if !defined(CONFIG_USER_ONLY) diff --git a/include/qom/cpu.h b/include/qom/cpu.h index 3bbda08eac..4127438507 100644 --- a/include/qom/cpu.h +++ b/include/qom/cpu.h @@ -595,6 +595,13 @@ void qemu_init_vcpu(CPUState *cpu); */ void cpu_single_step(CPUState *cpu, int enabled); +int cpu_watchpoint_insert(CPUState *cpu, vaddr addr, vaddr len, + int flags, CPUWatchpoint **watchpoint); +int cpu_watchpoint_remove(CPUState *cpu, vaddr addr, + vaddr len, int flags); +void cpu_watchpoint_remove_by_ref(CPUState *cpu, CPUWatchpoint *watchpoint); +void cpu_watchpoint_remove_all(CPUState *cpu, int mask); + #ifdef CONFIG_SOFTMMU extern const struct VMStateDescription vmstate_cpu_common; #else diff --git a/linux-user/main.c b/linux-user/main.c index dbc04b7d0f..280e295de7 100644 --- a/linux-user/main.c +++ b/linux-user/main.c @@ -3437,13 +3437,14 @@ CPUArchState *cpu_copy(CPUArchState *env) { CPUState *cpu = ENV_GET_CPU(env); CPUArchState *new_env = cpu_init(cpu_model); + CPUState *new_cpu = ENV_GET_CPU(new_env); #if defined(TARGET_HAS_ICE) CPUBreakpoint *bp; CPUWatchpoint *wp; #endif /* Reset non arch specific state */ - cpu_reset(ENV_GET_CPU(new_env)); + cpu_reset(new_cpu); memcpy(new_env, env, sizeof(CPUArchState)); @@ -3457,7 +3458,7 @@ CPUArchState *cpu_copy(CPUArchState *env) cpu_breakpoint_insert(new_env, bp->pc, bp->flags, NULL); } QTAILQ_FOREACH(wp, &cpu->watchpoints, entry) { - cpu_watchpoint_insert(new_env, wp->vaddr, (~wp->len_mask) + 1, + cpu_watchpoint_insert(new_cpu, wp->vaddr, (~wp->len_mask) + 1, wp->flags, NULL); } #endif diff --git a/target-i386/cpu.c b/target-i386/cpu.c index fab0f55735..a35f7bcb22 100644 --- a/target-i386/cpu.c +++ b/target-i386/cpu.c @@ -2474,7 +2474,7 @@ static void x86_cpu_reset(CPUState *s) env->dr[6] = DR6_FIXED_1; env->dr[7] = DR7_FIXED_1; cpu_breakpoint_remove_all(env, BP_CPU); - cpu_watchpoint_remove_all(env, BP_CPU); + cpu_watchpoint_remove_all(s, BP_CPU); env->tsc_adjust = 0; env->tsc = 0; diff --git a/target-i386/helper.c b/target-i386/helper.c index cb29aa4b0e..dd6d824010 100644 --- a/target-i386/helper.c +++ b/target-i386/helper.c @@ -993,6 +993,7 @@ hwaddr x86_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) void hw_breakpoint_insert(CPUX86State *env, int index) { + CPUState *cs = CPU(x86_env_get_cpu(env)); int type = 0, err = 0; switch (hw_breakpoint_type(env->dr[7], index)) { @@ -1014,7 +1015,7 @@ void hw_breakpoint_insert(CPUX86State *env, int index) } if (type != 0) { - err = cpu_watchpoint_insert(env, env->dr[index], + err = cpu_watchpoint_insert(cs, env->dr[index], hw_breakpoint_len(env->dr[7], index), type, &env->cpu_watchpoint[index]); } @@ -1026,8 +1027,12 @@ void hw_breakpoint_insert(CPUX86State *env, int index) void hw_breakpoint_remove(CPUX86State *env, int index) { - if (!env->cpu_breakpoint[index]) + CPUState *cs; + + if (!env->cpu_breakpoint[index]) { return; + } + cs = CPU(x86_env_get_cpu(env)); switch (hw_breakpoint_type(env->dr[7], index)) { case DR7_TYPE_BP_INST: if (hw_breakpoint_enabled(env->dr[7], index)) { @@ -1036,7 +1041,7 @@ void hw_breakpoint_remove(CPUX86State *env, int index) break; case DR7_TYPE_DATA_WR: case DR7_TYPE_DATA_RW: - cpu_watchpoint_remove_by_ref(env, env->cpu_watchpoint[index]); + cpu_watchpoint_remove_by_ref(cs, env->cpu_watchpoint[index]); break; case DR7_TYPE_IO_RW: /* No support for I/O watchpoints yet */ diff --git a/target-i386/machine.c b/target-i386/machine.c index d548c055a9..d49398c2eb 100644 --- a/target-i386/machine.c +++ b/target-i386/machine.c @@ -290,6 +290,7 @@ static void cpu_pre_save(void *opaque) static int cpu_post_load(void *opaque, int version_id) { X86CPU *cpu = opaque; + CPUState *cs = CPU(cpu); CPUX86State *env = &cpu->env; int i; @@ -320,7 +321,7 @@ static int cpu_post_load(void *opaque, int version_id) } cpu_breakpoint_remove_all(env, BP_CPU); - cpu_watchpoint_remove_all(env, BP_CPU); + cpu_watchpoint_remove_all(cs, BP_CPU); for (i = 0; i < DR7_MAX_BP; i++) { hw_breakpoint_insert(env, i); } diff --git a/target-lm32/helper.c b/target-lm32/helper.c index eadc7277a7..863337588f 100644 --- a/target-lm32/helper.c +++ b/target-lm32/helper.c @@ -69,6 +69,7 @@ void lm32_breakpoint_remove(CPULM32State *env, int idx) void lm32_watchpoint_insert(CPULM32State *env, int idx, target_ulong address, lm32_wp_t wp_type) { + LM32CPU *cpu = lm32_env_get_cpu(env); int flags = 0; switch (wp_type) { @@ -87,18 +88,20 @@ void lm32_watchpoint_insert(CPULM32State *env, int idx, target_ulong address, } if (flags != 0) { - cpu_watchpoint_insert(env, address, 1, flags, + cpu_watchpoint_insert(CPU(cpu), address, 1, flags, &env->cpu_watchpoint[idx]); } } void lm32_watchpoint_remove(CPULM32State *env, int idx) { + LM32CPU *cpu = lm32_env_get_cpu(env); + if (!env->cpu_watchpoint[idx]) { return; } - cpu_watchpoint_remove_by_ref(env, env->cpu_watchpoint[idx]); + cpu_watchpoint_remove_by_ref(CPU(cpu), env->cpu_watchpoint[idx]); env->cpu_watchpoint[idx] = NULL; } diff --git a/target-xtensa/op_helper.c b/target-xtensa/op_helper.c index 8233443eb0..07b00a4335 100644 --- a/target-xtensa/op_helper.c +++ b/target-xtensa/op_helper.c @@ -790,11 +790,12 @@ void HELPER(wsr_ibreaka)(CPUXtensaState *env, uint32_t i, uint32_t v) static void set_dbreak(CPUXtensaState *env, unsigned i, uint32_t dbreaka, uint32_t dbreakc) { + CPUState *cs = CPU(xtensa_env_get_cpu(env)); int flags = BP_CPU | BP_STOP_BEFORE_ACCESS; uint32_t mask = dbreakc | ~DBREAKC_MASK; if (env->cpu_watchpoint[i]) { - cpu_watchpoint_remove_by_ref(env, env->cpu_watchpoint[i]); + cpu_watchpoint_remove_by_ref(cs, env->cpu_watchpoint[i]); } if (dbreakc & DBREAKC_SB) { flags |= BP_MEM_WRITE; @@ -808,7 +809,7 @@ static void set_dbreak(CPUXtensaState *env, unsigned i, uint32_t dbreaka, /* cut mask after the first zero bit */ mask = 0xffffffff << (32 - clo32(mask)); } - if (cpu_watchpoint_insert(env, dbreaka & mask, ~mask + 1, + if (cpu_watchpoint_insert(cs, dbreaka & mask, ~mask + 1, flags, &env->cpu_watchpoint[i])) { env->cpu_watchpoint[i] = NULL; qemu_log("Failed to set data breakpoint at 0x%08x/%d\n", @@ -834,7 +835,9 @@ void HELPER(wsr_dbreakc)(CPUXtensaState *env, uint32_t i, uint32_t v) set_dbreak(env, i, env->sregs[DBREAKA + i], v); } else { if (env->cpu_watchpoint[i]) { - cpu_watchpoint_remove_by_ref(env, env->cpu_watchpoint[i]); + CPUState *cs = CPU(xtensa_env_get_cpu(env)); + + cpu_watchpoint_remove_by_ref(cs, env->cpu_watchpoint[i]); env->cpu_watchpoint[i] = NULL; } } -- cgit 1.4.1 From b3310ab3380995af2c640a3ffd82f6e7b352c9e6 Mon Sep 17 00:00:00 2001 From: Andreas Färber Date: Mon, 2 Sep 2013 17:26:20 +0200 Subject: exec: Change cpu_breakpoint_{insert,remove{,_by_ref,_all}} argument MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Use CPUState. Allows to clean up CPUArchState in gdbstub. Signed-off-by: Andreas Färber --- exec.c | 20 ++++++++------------ gdbstub.c | 20 ++++++++------------ include/exec/cpu-all.h | 15 --------------- include/qom/cpu.h | 15 +++++++++++++++ linux-user/main.c | 2 +- target-i386/cpu.c | 2 +- target-i386/helper.c | 4 ++-- target-i386/machine.c | 2 +- target-lm32/helper.c | 9 +++++++-- 9 files changed, 43 insertions(+), 46 deletions(-) (limited to 'include/exec') diff --git a/exec.c b/exec.c index e89653ecca..03ae5fe661 100644 --- a/exec.c +++ b/exec.c @@ -617,11 +617,10 @@ void cpu_watchpoint_remove_all(CPUState *cpu, int mask) #endif /* Add a breakpoint. */ -int cpu_breakpoint_insert(CPUArchState *env, target_ulong pc, int flags, +int cpu_breakpoint_insert(CPUState *cpu, vaddr pc, int flags, CPUBreakpoint **breakpoint) { #if defined(TARGET_HAS_ICE) - CPUState *cpu = ENV_GET_CPU(env); CPUBreakpoint *bp; bp = g_malloc(sizeof(*bp)); @@ -648,15 +647,14 @@ int cpu_breakpoint_insert(CPUArchState *env, target_ulong pc, int flags, } /* Remove a specific breakpoint. */ -int cpu_breakpoint_remove(CPUArchState *env, target_ulong pc, int flags) +int cpu_breakpoint_remove(CPUState *cpu, vaddr pc, int flags) { #if defined(TARGET_HAS_ICE) - CPUState *cpu = ENV_GET_CPU(env); CPUBreakpoint *bp; QTAILQ_FOREACH(bp, &cpu->breakpoints, entry) { if (bp->pc == pc && bp->flags == flags) { - cpu_breakpoint_remove_by_ref(env, bp); + cpu_breakpoint_remove_by_ref(cpu, bp); return 0; } } @@ -667,11 +665,9 @@ int cpu_breakpoint_remove(CPUArchState *env, target_ulong pc, int flags) } /* Remove a specific breakpoint by reference. */ -void cpu_breakpoint_remove_by_ref(CPUArchState *env, CPUBreakpoint *breakpoint) +void cpu_breakpoint_remove_by_ref(CPUState *cpu, CPUBreakpoint *breakpoint) { #if defined(TARGET_HAS_ICE) - CPUState *cpu = ENV_GET_CPU(env); - QTAILQ_REMOVE(&cpu->breakpoints, breakpoint, entry); breakpoint_invalidate(cpu, breakpoint->pc); @@ -681,15 +677,15 @@ void cpu_breakpoint_remove_by_ref(CPUArchState *env, CPUBreakpoint *breakpoint) } /* Remove all matching breakpoints. */ -void cpu_breakpoint_remove_all(CPUArchState *env, int mask) +void cpu_breakpoint_remove_all(CPUState *cpu, int mask) { #if defined(TARGET_HAS_ICE) - CPUState *cpu = ENV_GET_CPU(env); CPUBreakpoint *bp, *next; QTAILQ_FOREACH_SAFE(bp, &cpu->breakpoints, entry, next) { - if (bp->flags & mask) - cpu_breakpoint_remove_by_ref(env, bp); + if (bp->flags & mask) { + cpu_breakpoint_remove_by_ref(cpu, bp); + } } #endif } diff --git a/gdbstub.c b/gdbstub.c index cd10781c13..8afe0b701c 100644 --- a/gdbstub.c +++ b/gdbstub.c @@ -635,7 +635,6 @@ static const int xlat_gdb_type[] = { static int gdb_breakpoint_insert(target_ulong addr, target_ulong len, int type) { CPUState *cpu; - CPUArchState *env; int err = 0; if (kvm_enabled()) { @@ -646,10 +645,10 @@ static int gdb_breakpoint_insert(target_ulong addr, target_ulong len, int type) case GDB_BREAKPOINT_SW: case GDB_BREAKPOINT_HW: CPU_FOREACH(cpu) { - env = cpu->env_ptr; - err = cpu_breakpoint_insert(env, addr, BP_GDB, NULL); - if (err) + err = cpu_breakpoint_insert(cpu, addr, BP_GDB, NULL); + if (err) { break; + } } return err; #ifndef CONFIG_USER_ONLY @@ -672,7 +671,6 @@ static int gdb_breakpoint_insert(target_ulong addr, target_ulong len, int type) static int gdb_breakpoint_remove(target_ulong addr, target_ulong len, int type) { CPUState *cpu; - CPUArchState *env; int err = 0; if (kvm_enabled()) { @@ -683,10 +681,10 @@ static int gdb_breakpoint_remove(target_ulong addr, target_ulong len, int type) case GDB_BREAKPOINT_SW: case GDB_BREAKPOINT_HW: CPU_FOREACH(cpu) { - env = cpu->env_ptr; - err = cpu_breakpoint_remove(env, addr, BP_GDB); - if (err) + err = cpu_breakpoint_remove(cpu, addr, BP_GDB); + if (err) { break; + } } return err; #ifndef CONFIG_USER_ONLY @@ -708,7 +706,6 @@ static int gdb_breakpoint_remove(target_ulong addr, target_ulong len, int type) static void gdb_breakpoint_remove_all(void) { CPUState *cpu; - CPUArchState *env; if (kvm_enabled()) { kvm_remove_all_breakpoints(gdbserver_state->c_cpu); @@ -716,8 +713,7 @@ static void gdb_breakpoint_remove_all(void) } CPU_FOREACH(cpu) { - env = cpu->env_ptr; - cpu_breakpoint_remove_all(env, BP_GDB); + cpu_breakpoint_remove_all(cpu, BP_GDB); #ifndef CONFIG_USER_ONLY cpu_watchpoint_remove_all(cpu, BP_GDB); #endif @@ -1599,7 +1595,7 @@ void gdbserver_fork(CPUArchState *env) } close(s->fd); s->fd = -1; - cpu_breakpoint_remove_all(env, BP_GDB); + cpu_breakpoint_remove_all(cpu, BP_GDB); cpu_watchpoint_remove_all(cpu, BP_GDB); } #else diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h index ea90aee7fe..6bcadb4e51 100644 --- a/include/exec/cpu-all.h +++ b/include/exec/cpu-all.h @@ -413,21 +413,6 @@ void QEMU_NORETURN cpu_abort(CPUArchState *env, const char *fmt, ...) | CPU_INTERRUPT_TGT_EXT_3 \ | CPU_INTERRUPT_TGT_EXT_4) -/* Breakpoint/watchpoint flags */ -#define BP_MEM_READ 0x01 -#define BP_MEM_WRITE 0x02 -#define BP_MEM_ACCESS (BP_MEM_READ | BP_MEM_WRITE) -#define BP_STOP_BEFORE_ACCESS 0x04 -#define BP_WATCHPOINT_HIT 0x08 -#define BP_GDB 0x10 -#define BP_CPU 0x20 - -int cpu_breakpoint_insert(CPUArchState *env, target_ulong pc, int flags, - CPUBreakpoint **breakpoint); -int cpu_breakpoint_remove(CPUArchState *env, target_ulong pc, int flags); -void cpu_breakpoint_remove_by_ref(CPUArchState *env, CPUBreakpoint *breakpoint); -void cpu_breakpoint_remove_all(CPUArchState *env, int mask); - #if !defined(CONFIG_USER_ONLY) /* memory API */ diff --git a/include/qom/cpu.h b/include/qom/cpu.h index 4127438507..86698dd183 100644 --- a/include/qom/cpu.h +++ b/include/qom/cpu.h @@ -595,6 +595,21 @@ void qemu_init_vcpu(CPUState *cpu); */ void cpu_single_step(CPUState *cpu, int enabled); +/* Breakpoint/watchpoint flags */ +#define BP_MEM_READ 0x01 +#define BP_MEM_WRITE 0x02 +#define BP_MEM_ACCESS (BP_MEM_READ | BP_MEM_WRITE) +#define BP_STOP_BEFORE_ACCESS 0x04 +#define BP_WATCHPOINT_HIT 0x08 +#define BP_GDB 0x10 +#define BP_CPU 0x20 + +int cpu_breakpoint_insert(CPUState *cpu, vaddr pc, int flags, + CPUBreakpoint **breakpoint); +int cpu_breakpoint_remove(CPUState *cpu, vaddr pc, int flags); +void cpu_breakpoint_remove_by_ref(CPUState *cpu, CPUBreakpoint *breakpoint); +void cpu_breakpoint_remove_all(CPUState *cpu, int mask); + int cpu_watchpoint_insert(CPUState *cpu, vaddr addr, vaddr len, int flags, CPUWatchpoint **watchpoint); int cpu_watchpoint_remove(CPUState *cpu, vaddr addr, diff --git a/linux-user/main.c b/linux-user/main.c index 280e295de7..dc96b2348b 100644 --- a/linux-user/main.c +++ b/linux-user/main.c @@ -3455,7 +3455,7 @@ CPUArchState *cpu_copy(CPUArchState *env) QTAILQ_INIT(&cpu->watchpoints); #if defined(TARGET_HAS_ICE) QTAILQ_FOREACH(bp, &cpu->breakpoints, entry) { - cpu_breakpoint_insert(new_env, bp->pc, bp->flags, NULL); + cpu_breakpoint_insert(new_cpu, bp->pc, bp->flags, NULL); } QTAILQ_FOREACH(wp, &cpu->watchpoints, entry) { cpu_watchpoint_insert(new_cpu, wp->vaddr, (~wp->len_mask) + 1, diff --git a/target-i386/cpu.c b/target-i386/cpu.c index a35f7bcb22..659ec9a11b 100644 --- a/target-i386/cpu.c +++ b/target-i386/cpu.c @@ -2473,7 +2473,7 @@ static void x86_cpu_reset(CPUState *s) memset(env->dr, 0, sizeof(env->dr)); env->dr[6] = DR6_FIXED_1; env->dr[7] = DR7_FIXED_1; - cpu_breakpoint_remove_all(env, BP_CPU); + cpu_breakpoint_remove_all(s, BP_CPU); cpu_watchpoint_remove_all(s, BP_CPU); env->tsc_adjust = 0; diff --git a/target-i386/helper.c b/target-i386/helper.c index dd6d824010..ad61062de3 100644 --- a/target-i386/helper.c +++ b/target-i386/helper.c @@ -999,7 +999,7 @@ void hw_breakpoint_insert(CPUX86State *env, int index) switch (hw_breakpoint_type(env->dr[7], index)) { case DR7_TYPE_BP_INST: if (hw_breakpoint_enabled(env->dr[7], index)) { - err = cpu_breakpoint_insert(env, env->dr[index], BP_CPU, + err = cpu_breakpoint_insert(cs, env->dr[index], BP_CPU, &env->cpu_breakpoint[index]); } break; @@ -1036,7 +1036,7 @@ void hw_breakpoint_remove(CPUX86State *env, int index) switch (hw_breakpoint_type(env->dr[7], index)) { case DR7_TYPE_BP_INST: if (hw_breakpoint_enabled(env->dr[7], index)) { - cpu_breakpoint_remove_by_ref(env, env->cpu_breakpoint[index]); + cpu_breakpoint_remove_by_ref(cs, env->cpu_breakpoint[index]); } break; case DR7_TYPE_DATA_WR: diff --git a/target-i386/machine.c b/target-i386/machine.c index d49398c2eb..ed159a8c06 100644 --- a/target-i386/machine.c +++ b/target-i386/machine.c @@ -320,7 +320,7 @@ static int cpu_post_load(void *opaque, int version_id) env->fptags[i] = (env->fptag_vmstate >> i) & 1; } - cpu_breakpoint_remove_all(env, BP_CPU); + cpu_breakpoint_remove_all(cs, BP_CPU); cpu_watchpoint_remove_all(cs, BP_CPU); for (i = 0; i < DR7_MAX_BP; i++) { hw_breakpoint_insert(env, i); diff --git a/target-lm32/helper.c b/target-lm32/helper.c index 863337588f..8be5bed2b4 100644 --- a/target-lm32/helper.c +++ b/target-lm32/helper.c @@ -53,16 +53,21 @@ hwaddr lm32_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) void lm32_breakpoint_insert(CPULM32State *env, int idx, target_ulong address) { - cpu_breakpoint_insert(env, address, BP_CPU, &env->cpu_breakpoint[idx]); + LM32CPU *cpu = lm32_env_get_cpu(env); + + cpu_breakpoint_insert(CPU(cpu), address, BP_CPU, + &env->cpu_breakpoint[idx]); } void lm32_breakpoint_remove(CPULM32State *env, int idx) { + LM32CPU *cpu = lm32_env_get_cpu(env); + if (!env->cpu_breakpoint[idx]) { return; } - cpu_breakpoint_remove_by_ref(env, env->cpu_breakpoint[idx]); + cpu_breakpoint_remove_by_ref(CPU(cpu), env->cpu_breakpoint[idx]); env->cpu_breakpoint[idx] = NULL; } -- cgit 1.4.1 From 0ea8cb8895a9f9adea89fb202984dcd9e890e504 Mon Sep 17 00:00:00 2001 From: Andreas Färber Date: Tue, 3 Sep 2013 02:12:23 +0200 Subject: cpu-exec: Change cpu_resume_from_signal() argument to CPUState MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Andreas Färber --- cpu-exec.c | 4 +--- exec.c | 2 +- hw/i386/kvmvapic.c | 2 +- include/exec/exec-all.h | 2 +- target-i386/helper.c | 2 +- target-lm32/helper.c | 2 +- target-xtensa/helper.c | 2 +- translate-all.c | 6 +++--- user-exec.c | 3 +-- 9 files changed, 11 insertions(+), 14 deletions(-) (limited to 'include/exec') diff --git a/cpu-exec.c b/cpu-exec.c index c689ef9882..0914d3c85c 100644 --- a/cpu-exec.c +++ b/cpu-exec.c @@ -33,10 +33,8 @@ void cpu_loop_exit(CPUState *cpu) restored in a state compatible with the CPU emulator */ #if defined(CONFIG_SOFTMMU) -void cpu_resume_from_signal(CPUArchState *env, void *puc) +void cpu_resume_from_signal(CPUState *cpu, void *puc) { - CPUState *cpu = ENV_GET_CPU(env); - /* XXX: restore cpu registers saved in host registers */ cpu->exception_index = -1; diff --git a/exec.c b/exec.c index 03ae5fe661..7b377cdb70 100644 --- a/exec.c +++ b/exec.c @@ -1608,7 +1608,7 @@ static void check_watchpoint(int offset, int len_mask, int flags) } else { cpu_get_tb_cpu_state(env, &pc, &cs_base, &cpu_flags); tb_gen_code(cpu, pc, cs_base, cpu_flags, 1); - cpu_resume_from_signal(env, NULL); + cpu_resume_from_signal(cpu, NULL); } } } else { diff --git a/hw/i386/kvmvapic.c b/hw/i386/kvmvapic.c index 2a9d87a5d8..a1c3d1cb85 100644 --- a/hw/i386/kvmvapic.c +++ b/hw/i386/kvmvapic.c @@ -449,7 +449,7 @@ static void patch_instruction(VAPICROMState *s, X86CPU *cpu, target_ulong ip) if (!kvm_enabled()) { cs->current_tb = NULL; tb_gen_code(cs, current_pc, current_cs_base, current_flags, 1); - cpu_resume_from_signal(env, NULL); + cpu_resume_from_signal(cs, NULL); } } diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index a3e7faa416..01b8eba9bc 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -83,7 +83,7 @@ int cpu_gen_code(CPUArchState *env, struct TranslationBlock *tb, bool cpu_restore_state(CPUState *cpu, uintptr_t searched_pc); void page_size_init(void); -void QEMU_NORETURN cpu_resume_from_signal(CPUArchState *env1, void *puc); +void QEMU_NORETURN cpu_resume_from_signal(CPUState *cpu, void *puc); void QEMU_NORETURN cpu_io_recompile(CPUState *cpu, uintptr_t retaddr); TranslationBlock *tb_gen_code(CPUState *cpu, target_ulong pc, target_ulong cs_base, int flags, diff --git a/target-i386/helper.c b/target-i386/helper.c index ad61062de3..8c70d62af5 100644 --- a/target-i386/helper.c +++ b/target-i386/helper.c @@ -1102,7 +1102,7 @@ void breakpoint_handler(CPUX86State *env) if (check_hw_breakpoints(env, false)) { raise_exception(env, EXCP01_DB); } else { - cpu_resume_from_signal(env, NULL); + cpu_resume_from_signal(cs, NULL); } } } else { diff --git a/target-lm32/helper.c b/target-lm32/helper.c index 8be5bed2b4..7de783b91d 100644 --- a/target-lm32/helper.c +++ b/target-lm32/helper.c @@ -135,7 +135,7 @@ void lm32_debug_excp_handler(CPULM32State *env) if (check_watchpoints(env)) { raise_exception(env, EXCP_WATCHPOINT); } else { - cpu_resume_from_signal(env, NULL); + cpu_resume_from_signal(cs, NULL); } } } else { diff --git a/target-xtensa/helper.c b/target-xtensa/helper.c index 8a9cb0a825..94dcd9442e 100644 --- a/target-xtensa/helper.c +++ b/target-xtensa/helper.c @@ -92,7 +92,7 @@ void xtensa_breakpoint_handler(CPUXtensaState *env) if (cause) { debug_exception_env(env, cause); } - cpu_resume_from_signal(env, NULL); + cpu_resume_from_signal(cs, NULL); } } } diff --git a/translate-all.c b/translate-all.c index df85f9f8c5..0aa4f76432 100644 --- a/translate-all.c +++ b/translate-all.c @@ -1113,7 +1113,7 @@ void tb_invalidate_phys_page_range(tb_page_addr_t start, tb_page_addr_t end, itself */ cpu->current_tb = NULL; tb_gen_code(cpu, current_pc, current_cs_base, current_flags, 1); - cpu_resume_from_signal(env, NULL); + cpu_resume_from_signal(cpu, NULL); } #endif } @@ -1213,7 +1213,7 @@ static void tb_invalidate_phys_page(tb_page_addr_t addr, if (locked) { mmap_unlock(); } - cpu_resume_from_signal(env, puc); + cpu_resume_from_signal(cpu, puc); } #endif } @@ -1476,7 +1476,7 @@ void cpu_io_recompile(CPUState *cpu, uintptr_t retaddr) repeating the fault, which is horribly inefficient. Better would be to execute just this insn uncached, or generate a second new TB. */ - cpu_resume_from_signal(env, NULL); + cpu_resume_from_signal(cpu, NULL); } void tb_flush_jmp_cache(CPUState *cpu, target_ulong addr) diff --git a/user-exec.c b/user-exec.c index 75c6d5486b..3b795c1550 100644 --- a/user-exec.c +++ b/user-exec.c @@ -52,9 +52,8 @@ static void exception_action(CPUArchState *env1) /* exit the current TB from a signal handler. The host registers are restored in a state compatible with the CPU emulator */ -void cpu_resume_from_signal(CPUArchState *env1, void *puc) +void cpu_resume_from_signal(CPUState *cpu, void *puc) { - CPUState *cpu = ENV_GET_CPU(env1); #ifdef __linux__ struct ucontext *uc = puc; #elif defined(__OpenBSD__) -- cgit 1.4.1 From baea4fae7b6d75ce0d1aeb2be0a223c7be8f4161 Mon Sep 17 00:00:00 2001 From: Andreas Färber Date: Tue, 3 Sep 2013 10:51:26 +0200 Subject: cputlb: Change tlb_unprotect_code_phys() argument to CPUState MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Note that the argument is unused. Signed-off-by: Andreas Färber --- cputlb.c | 2 +- include/exec/cputlb.h | 2 +- translate-all.c | 6 +++--- 3 files changed, 5 insertions(+), 5 deletions(-) (limited to 'include/exec') diff --git a/cputlb.c b/cputlb.c index 6b2cdb201a..343ede2bbb 100644 --- a/cputlb.c +++ b/cputlb.c @@ -119,7 +119,7 @@ void tlb_protect_code(ram_addr_t ram_addr) /* update the TLB so that writes in physical page 'phys_addr' are no longer tested for self modifying code */ -void tlb_unprotect_code_phys(CPUArchState *env, ram_addr_t ram_addr, +void tlb_unprotect_code_phys(CPUState *cpu, ram_addr_t ram_addr, target_ulong vaddr) { cpu_physical_memory_set_dirty_flag(ram_addr, DIRTY_MEMORY_CODE); diff --git a/include/exec/cputlb.h b/include/exec/cputlb.h index e1eb4d92df..31df03c525 100644 --- a/include/exec/cputlb.h +++ b/include/exec/cputlb.h @@ -22,7 +22,7 @@ #if !defined(CONFIG_USER_ONLY) /* cputlb.c */ void tlb_protect_code(ram_addr_t ram_addr); -void tlb_unprotect_code_phys(CPUArchState *env, ram_addr_t ram_addr, +void tlb_unprotect_code_phys(CPUState *cpu, ram_addr_t ram_addr, target_ulong vaddr); void tlb_reset_dirty_range(CPUTLBEntry *tlb_entry, uintptr_t start, uintptr_t length); diff --git a/translate-all.c b/translate-all.c index 0aa4f76432..e35fcbe86a 100644 --- a/translate-all.c +++ b/translate-all.c @@ -1007,7 +1007,7 @@ void tb_invalidate_phys_page_range(tb_page_addr_t start, tb_page_addr_t end, { TranslationBlock *tb, *tb_next, *saved_tb; CPUState *cpu = current_cpu; -#if defined(TARGET_HAS_PRECISE_SMC) || !defined(CONFIG_USER_ONLY) +#if defined(TARGET_HAS_PRECISE_SMC) CPUArchState *env = NULL; #endif tb_page_addr_t tb_start, tb_end; @@ -1032,7 +1032,7 @@ void tb_invalidate_phys_page_range(tb_page_addr_t start, tb_page_addr_t end, /* build code bitmap */ build_page_bitmap(p); } -#if defined(TARGET_HAS_PRECISE_SMC) || !defined(CONFIG_USER_ONLY) +#if defined(TARGET_HAS_PRECISE_SMC) if (cpu != NULL) { env = cpu->env_ptr; } @@ -1102,7 +1102,7 @@ void tb_invalidate_phys_page_range(tb_page_addr_t start, tb_page_addr_t end, if (!p->first_tb) { invalidate_page_bitmap(p); if (is_cpu_write_access) { - tlb_unprotect_code_phys(env, start, cpu->mem_io_vaddr); + tlb_unprotect_code_phys(cpu, start, cpu->mem_io_vaddr); } } #endif -- cgit 1.4.1 From bb0e627a84752707e629fde5534558ac08e7c521 Mon Sep 17 00:00:00 2001 From: Andreas Färber Date: Tue, 3 Sep 2013 13:32:01 +0200 Subject: exec: Change memory_region_section_get_iotlb() argument to CPUState MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit It no longer needs CPUArchState since moving watchpoints to CPUState. Signed-off-by: Andreas Färber --- cputlb.c | 2 +- exec.c | 3 +-- include/exec/cputlb.h | 2 +- 3 files changed, 3 insertions(+), 4 deletions(-) (limited to 'include/exec') diff --git a/cputlb.c b/cputlb.c index 343ede2bbb..8a00330db3 100644 --- a/cputlb.c +++ b/cputlb.c @@ -261,7 +261,7 @@ void tlb_set_page(CPUArchState *env, target_ulong vaddr, } code_address = address; - iotlb = memory_region_section_get_iotlb(env, section, vaddr, paddr, xlat, + iotlb = memory_region_section_get_iotlb(cpu, section, vaddr, paddr, xlat, prot, &address); index = (vaddr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1); diff --git a/exec.c b/exec.c index 7b377cdb70..82580c5e0d 100644 --- a/exec.c +++ b/exec.c @@ -799,14 +799,13 @@ static void cpu_physical_memory_set_dirty_tracking(bool enable) in_migration = enable; } -hwaddr memory_region_section_get_iotlb(CPUArchState *env, +hwaddr memory_region_section_get_iotlb(CPUState *cpu, MemoryRegionSection *section, target_ulong vaddr, hwaddr paddr, hwaddr xlat, int prot, target_ulong *address) { - CPUState *cpu = ENV_GET_CPU(env); hwaddr iotlb; CPUWatchpoint *wp; diff --git a/include/exec/cputlb.h b/include/exec/cputlb.h index 31df03c525..b8ecd6f68d 100644 --- a/include/exec/cputlb.h +++ b/include/exec/cputlb.h @@ -36,7 +36,7 @@ void tb_flush_jmp_cache(CPUState *cpu, target_ulong addr); MemoryRegionSection * address_space_translate_for_iotlb(AddressSpace *as, hwaddr addr, hwaddr *xlat, hwaddr *plen); -hwaddr memory_region_section_get_iotlb(CPUArchState *env, +hwaddr memory_region_section_get_iotlb(CPUState *cpu, MemoryRegionSection *section, target_ulong vaddr, hwaddr paddr, hwaddr xlat, -- cgit 1.4.1 From a47dddd7348d3e75ad650ef5e2ca9c3b13a600ac Mon Sep 17 00:00:00 2001 From: Andreas Färber Date: Tue, 3 Sep 2013 17:38:47 +0200 Subject: exec: Change cpu_abort() argument to CPUState MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Andreas Färber --- cputlb.c | 2 +- exec.c | 3 +- include/exec/cpu-all.h | 3 -- include/qom/cpu.h | 3 ++ linux-user/m68k-sim.c | 3 +- linux-user/main.c | 80 ++++++++++++++++++++--------------------- target-alpha/helper.c | 2 +- target-arm/helper.c | 35 ++++++++++++------ target-arm/translate.c | 2 +- target-cris/helper.c | 6 ++-- target-cris/translate.c | 4 +-- target-cris/translate_v10.c | 12 +++---- target-i386/seg_helper.c | 8 +++-- target-lm32/helper.c | 2 +- target-m68k/helper.c | 7 ++-- target-m68k/m68k-semi.c | 2 +- target-m68k/translate.c | 16 ++++++--- target-microblaze/helper.c | 4 +-- target-microblaze/translate.c | 32 ++++++++++------- target-mips/op_helper.c | 11 ++++-- target-mips/translate_init.c | 4 ++- target-openrisc/interrupt.c | 2 +- target-ppc/cpu.h | 2 +- target-ppc/excp_helper.c | 48 ++++++++++++------------- target-ppc/kvm.c | 6 ++-- target-ppc/mmu_helper.c | 54 ++++++++++++++++------------ target-ppc/translate_init.c | 5 +-- target-s390x/cc_helper.c | 3 +- target-s390x/fpu_helper.c | 4 ++- target-s390x/helper.c | 23 +++++++----- target-s390x/int_helper.c | 3 +- target-s390x/mem_helper.c | 11 +++--- target-sh4/helper.c | 21 +++++++---- target-sh4/op_helper.c | 4 ++- target-sparc/int32_helper.c | 2 +- target-sparc/int64_helper.c | 2 +- target-unicore32/helper.c | 14 +++----- target-unicore32/softmmu.c | 15 ++++---- target-unicore32/translate.c | 28 +++++++++++++-- target-unicore32/ucf64_helper.c | 3 +- translate-all.c | 16 ++++----- 41 files changed, 301 insertions(+), 206 deletions(-) (limited to 'include/exec') diff --git a/cputlb.c b/cputlb.c index 8a00330db3..22810536f5 100644 --- a/cputlb.c +++ b/cputlb.c @@ -322,7 +322,7 @@ tb_page_addr_t get_page_addr_code(CPUArchState *env1, target_ulong addr) if (cc->do_unassigned_access) { cc->do_unassigned_access(cpu, addr, false, true, 0, 4); } else { - cpu_abort(env1, "Trying to execute code outside RAM or ROM at 0x" + cpu_abort(cpu, "Trying to execute code outside RAM or ROM at 0x" TARGET_FMT_lx "\n", addr); } } diff --git a/exec.c b/exec.c index 82580c5e0d..5224b31e9f 100644 --- a/exec.c +++ b/exec.c @@ -709,9 +709,8 @@ void cpu_single_step(CPUState *cpu, int enabled) #endif } -void cpu_abort(CPUArchState *env, const char *fmt, ...) +void cpu_abort(CPUState *cpu, const char *fmt, ...) { - CPUState *cpu = ENV_GET_CPU(env); va_list ap; va_list ap2; diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h index 6bcadb4e51..fb649a4029 100644 --- a/include/exec/cpu-all.h +++ b/include/exec/cpu-all.h @@ -360,9 +360,6 @@ int page_check_range(target_ulong start, target_ulong len, int flags); CPUArchState *cpu_copy(CPUArchState *env); -void QEMU_NORETURN cpu_abort(CPUArchState *env, const char *fmt, ...) - GCC_FMT_ATTR(2, 3); - /* Flags for use in ENV->INTERRUPT_PENDING. The numbers assigned here are non-sequential in order to preserve diff --git a/include/qom/cpu.h b/include/qom/cpu.h index 86698dd183..06ee2636c3 100644 --- a/include/qom/cpu.h +++ b/include/qom/cpu.h @@ -617,6 +617,9 @@ int cpu_watchpoint_remove(CPUState *cpu, vaddr addr, void cpu_watchpoint_remove_by_ref(CPUState *cpu, CPUWatchpoint *watchpoint); void cpu_watchpoint_remove_all(CPUState *cpu, int mask); +void QEMU_NORETURN cpu_abort(CPUState *cpu, const char *fmt, ...) + GCC_FMT_ATTR(2, 3); + #ifdef CONFIG_SOFTMMU extern const struct VMStateDescription vmstate_cpu_common; #else diff --git a/linux-user/m68k-sim.c b/linux-user/m68k-sim.c index d5926eec4b..1994e40000 100644 --- a/linux-user/m68k-sim.c +++ b/linux-user/m68k-sim.c @@ -98,6 +98,7 @@ static int translate_openflags(int flags) #define ARG(x) tswap32(args[x]) void do_m68k_simcall(CPUM68KState *env, int nr) { + M68kCPU *cpu = m68k_env_get_cpu(env); uint32_t *args; args = (uint32_t *)(unsigned long)(env->aregs[7] + 4); @@ -165,6 +166,6 @@ void do_m68k_simcall(CPUM68KState *env, int nr) check_err(env, lseek(ARG(0), (int32_t)ARG(1), ARG(2))); break; default: - cpu_abort(env, "Unsupported m68k sim syscall %d\n", nr); + cpu_abort(CPU(cpu), "Unsupported m68k sim syscall %d\n", nr); } } diff --git a/linux-user/main.c b/linux-user/main.c index dc96b2348b..af924dcc9d 100644 --- a/linux-user/main.c +++ b/linux-user/main.c @@ -1577,11 +1577,11 @@ void cpu_loop(CPUPPCState *env) /* Just go on */ break; case POWERPC_EXCP_CRITICAL: /* Critical input */ - cpu_abort(env, "Critical interrupt while in user mode. " + cpu_abort(cs, "Critical interrupt while in user mode. " "Aborting\n"); break; case POWERPC_EXCP_MCHECK: /* Machine check exception */ - cpu_abort(env, "Machine check exception while in user mode. " + cpu_abort(cs, "Machine check exception while in user mode. " "Aborting\n"); break; case POWERPC_EXCP_DSI: /* Data storage exception */ @@ -1645,7 +1645,7 @@ void cpu_loop(CPUPPCState *env) queue_signal(env, info.si_signo, &info); break; case POWERPC_EXCP_EXTERNAL: /* External input */ - cpu_abort(env, "External interrupt while in user mode. " + cpu_abort(cs, "External interrupt while in user mode. " "Aborting\n"); break; case POWERPC_EXCP_ALIGN: /* Alignment exception */ @@ -1739,11 +1739,11 @@ void cpu_loop(CPUPPCState *env) } break; case POWERPC_EXCP_TRAP: - cpu_abort(env, "Tried to call a TRAP\n"); + cpu_abort(cs, "Tried to call a TRAP\n"); break; default: /* Should not happen ! */ - cpu_abort(env, "Unknown program exception (%02x)\n", + cpu_abort(cs, "Unknown program exception (%02x)\n", env->error_code); break; } @@ -1759,7 +1759,7 @@ void cpu_loop(CPUPPCState *env) queue_signal(env, info.si_signo, &info); break; case POWERPC_EXCP_SYSCALL: /* System call exception */ - cpu_abort(env, "Syscall exception while in user mode. " + cpu_abort(cs, "Syscall exception while in user mode. " "Aborting\n"); break; case POWERPC_EXCP_APU: /* Auxiliary processor unavailable */ @@ -1771,23 +1771,23 @@ void cpu_loop(CPUPPCState *env) queue_signal(env, info.si_signo, &info); break; case POWERPC_EXCP_DECR: /* Decrementer exception */ - cpu_abort(env, "Decrementer interrupt while in user mode. " + cpu_abort(cs, "Decrementer interrupt while in user mode. " "Aborting\n"); break; case POWERPC_EXCP_FIT: /* Fixed-interval timer interrupt */ - cpu_abort(env, "Fix interval timer interrupt while in user mode. " + cpu_abort(cs, "Fix interval timer interrupt while in user mode. " "Aborting\n"); break; case POWERPC_EXCP_WDT: /* Watchdog timer interrupt */ - cpu_abort(env, "Watchdog timer interrupt while in user mode. " + cpu_abort(cs, "Watchdog timer interrupt while in user mode. " "Aborting\n"); break; case POWERPC_EXCP_DTLB: /* Data TLB error */ - cpu_abort(env, "Data TLB exception while in user mode. " + cpu_abort(cs, "Data TLB exception while in user mode. " "Aborting\n"); break; case POWERPC_EXCP_ITLB: /* Instruction TLB error */ - cpu_abort(env, "Instruction TLB exception while in user mode. " + cpu_abort(cs, "Instruction TLB exception while in user mode. " "Aborting\n"); break; case POWERPC_EXCP_SPEU: /* SPE/embedded floating-point unavail. */ @@ -1799,37 +1799,37 @@ void cpu_loop(CPUPPCState *env) queue_signal(env, info.si_signo, &info); break; case POWERPC_EXCP_EFPDI: /* Embedded floating-point data IRQ */ - cpu_abort(env, "Embedded floating-point data IRQ not handled\n"); + cpu_abort(cs, "Embedded floating-point data IRQ not handled\n"); break; case POWERPC_EXCP_EFPRI: /* Embedded floating-point round IRQ */ - cpu_abort(env, "Embedded floating-point round IRQ not handled\n"); + cpu_abort(cs, "Embedded floating-point round IRQ not handled\n"); break; case POWERPC_EXCP_EPERFM: /* Embedded performance monitor IRQ */ - cpu_abort(env, "Performance monitor exception not handled\n"); + cpu_abort(cs, "Performance monitor exception not handled\n"); break; case POWERPC_EXCP_DOORI: /* Embedded doorbell interrupt */ - cpu_abort(env, "Doorbell interrupt while in user mode. " + cpu_abort(cs, "Doorbell interrupt while in user mode. " "Aborting\n"); break; case POWERPC_EXCP_DOORCI: /* Embedded doorbell critical interrupt */ - cpu_abort(env, "Doorbell critical interrupt while in user mode. " + cpu_abort(cs, "Doorbell critical interrupt while in user mode. " "Aborting\n"); break; case POWERPC_EXCP_RESET: /* System reset exception */ - cpu_abort(env, "Reset interrupt while in user mode. " + cpu_abort(cs, "Reset interrupt while in user mode. " "Aborting\n"); break; case POWERPC_EXCP_DSEG: /* Data segment exception */ - cpu_abort(env, "Data segment exception while in user mode. " + cpu_abort(cs, "Data segment exception while in user mode. " "Aborting\n"); break; case POWERPC_EXCP_ISEG: /* Instruction segment exception */ - cpu_abort(env, "Instruction segment exception " + cpu_abort(cs, "Instruction segment exception " "while in user mode. Aborting\n"); break; /* PowerPC 64 with hypervisor mode support */ case POWERPC_EXCP_HDECR: /* Hypervisor decrementer exception */ - cpu_abort(env, "Hypervisor decrementer interrupt " + cpu_abort(cs, "Hypervisor decrementer interrupt " "while in user mode. Aborting\n"); break; case POWERPC_EXCP_TRACE: /* Trace exception */ @@ -1839,19 +1839,19 @@ void cpu_loop(CPUPPCState *env) break; /* PowerPC 64 with hypervisor mode support */ case POWERPC_EXCP_HDSI: /* Hypervisor data storage exception */ - cpu_abort(env, "Hypervisor data storage exception " + cpu_abort(cs, "Hypervisor data storage exception " "while in user mode. Aborting\n"); break; case POWERPC_EXCP_HISI: /* Hypervisor instruction storage excp */ - cpu_abort(env, "Hypervisor instruction storage exception " + cpu_abort(cs, "Hypervisor instruction storage exception " "while in user mode. Aborting\n"); break; case POWERPC_EXCP_HDSEG: /* Hypervisor data segment exception */ - cpu_abort(env, "Hypervisor data segment exception " + cpu_abort(cs, "Hypervisor data segment exception " "while in user mode. Aborting\n"); break; case POWERPC_EXCP_HISEG: /* Hypervisor instruction segment excp */ - cpu_abort(env, "Hypervisor instruction segment exception " + cpu_abort(cs, "Hypervisor instruction segment exception " "while in user mode. Aborting\n"); break; case POWERPC_EXCP_VPU: /* Vector unavailable exception */ @@ -1863,58 +1863,58 @@ void cpu_loop(CPUPPCState *env) queue_signal(env, info.si_signo, &info); break; case POWERPC_EXCP_PIT: /* Programmable interval timer IRQ */ - cpu_abort(env, "Programmable interval timer interrupt " + cpu_abort(cs, "Programmable interval timer interrupt " "while in user mode. Aborting\n"); break; case POWERPC_EXCP_IO: /* IO error exception */ - cpu_abort(env, "IO error exception while in user mode. " + cpu_abort(cs, "IO error exception while in user mode. " "Aborting\n"); break; case POWERPC_EXCP_RUNM: /* Run mode exception */ - cpu_abort(env, "Run mode exception while in user mode. " + cpu_abort(cs, "Run mode exception while in user mode. " "Aborting\n"); break; case POWERPC_EXCP_EMUL: /* Emulation trap exception */ - cpu_abort(env, "Emulation trap exception not handled\n"); + cpu_abort(cs, "Emulation trap exception not handled\n"); break; case POWERPC_EXCP_IFTLB: /* Instruction fetch TLB error */ - cpu_abort(env, "Instruction fetch TLB exception " + cpu_abort(cs, "Instruction fetch TLB exception " "while in user-mode. Aborting"); break; case POWERPC_EXCP_DLTLB: /* Data load TLB miss */ - cpu_abort(env, "Data load TLB exception while in user-mode. " + cpu_abort(cs, "Data load TLB exception while in user-mode. " "Aborting"); break; case POWERPC_EXCP_DSTLB: /* Data store TLB miss */ - cpu_abort(env, "Data store TLB exception while in user-mode. " + cpu_abort(cs, "Data store TLB exception while in user-mode. " "Aborting"); break; case POWERPC_EXCP_FPA: /* Floating-point assist exception */ - cpu_abort(env, "Floating-point assist exception not handled\n"); + cpu_abort(cs, "Floating-point assist exception not handled\n"); break; case POWERPC_EXCP_IABR: /* Instruction address breakpoint */ - cpu_abort(env, "Instruction address breakpoint exception " + cpu_abort(cs, "Instruction address breakpoint exception " "not handled\n"); break; case POWERPC_EXCP_SMI: /* System management interrupt */ - cpu_abort(env, "System management interrupt while in user mode. " + cpu_abort(cs, "System management interrupt while in user mode. " "Aborting\n"); break; case POWERPC_EXCP_THERM: /* Thermal interrupt */ - cpu_abort(env, "Thermal interrupt interrupt while in user mode. " + cpu_abort(cs, "Thermal interrupt interrupt while in user mode. " "Aborting\n"); break; case POWERPC_EXCP_PERFM: /* Embedded performance monitor IRQ */ - cpu_abort(env, "Performance monitor exception not handled\n"); + cpu_abort(cs, "Performance monitor exception not handled\n"); break; case POWERPC_EXCP_VPUA: /* Vector assist exception */ - cpu_abort(env, "Vector assist exception not handled\n"); + cpu_abort(cs, "Vector assist exception not handled\n"); break; case POWERPC_EXCP_SOFTP: /* Soft patch exception */ - cpu_abort(env, "Soft patch exception not handled\n"); + cpu_abort(cs, "Soft patch exception not handled\n"); break; case POWERPC_EXCP_MAINT: /* Maintenance exception */ - cpu_abort(env, "Maintenance exception while in user mode. " + cpu_abort(cs, "Maintenance exception while in user mode. " "Aborting\n"); break; case POWERPC_EXCP_STOP: /* stop translation */ @@ -1970,7 +1970,7 @@ void cpu_loop(CPUPPCState *env) /* just indicate that signals should be handled asap */ break; default: - cpu_abort(env, "Unknown exception 0x%d. Aborting\n", trapnr); + cpu_abort(cs, "Unknown exception 0x%d. Aborting\n", trapnr); break; } process_pending_signals(env); diff --git a/target-alpha/helper.c b/target-alpha/helper.c index 305dd67b84..fdb033564c 100644 --- a/target-alpha/helper.c +++ b/target-alpha/helper.c @@ -452,7 +452,7 @@ void alpha_cpu_do_interrupt(CPUState *cs) } break; default: - cpu_abort(env, "Unhandled CPU exception"); + cpu_abort(cs, "Unhandled CPU exception"); } /* Remember where the exception happened. Emulate real hardware in diff --git a/target-arm/helper.c b/target-arm/helper.c index 0d173ebfcf..0a9c6fc5e2 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -2671,29 +2671,40 @@ int arm_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw, /* These should probably raise undefined insn exceptions. */ void HELPER(v7m_msr)(CPUARMState *env, uint32_t reg, uint32_t val) { - cpu_abort(env, "v7m_mrs %d\n", reg); + ARMCPU *cpu = arm_env_get_cpu(env); + + cpu_abort(CPU(cpu), "v7m_msr %d\n", reg); } uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg) { - cpu_abort(env, "v7m_mrs %d\n", reg); + ARMCPU *cpu = arm_env_get_cpu(env); + + cpu_abort(CPU(cpu), "v7m_mrs %d\n", reg); return 0; } void switch_mode(CPUARMState *env, int mode) { - if (mode != ARM_CPU_MODE_USR) - cpu_abort(env, "Tried to switch out of user mode\n"); + ARMCPU *cpu = arm_env_get_cpu(env); + + if (mode != ARM_CPU_MODE_USR) { + cpu_abort(CPU(cpu), "Tried to switch out of user mode\n"); + } } void HELPER(set_r13_banked)(CPUARMState *env, uint32_t mode, uint32_t val) { - cpu_abort(env, "banked r13 write\n"); + ARMCPU *cpu = arm_env_get_cpu(env); + + cpu_abort(CPU(cpu), "banked r13 write\n"); } uint32_t HELPER(get_r13_banked)(CPUARMState *env, uint32_t mode) { - cpu_abort(env, "banked r13 read\n"); + ARMCPU *cpu = arm_env_get_cpu(env); + + cpu_abort(CPU(cpu), "banked r13 read\n"); return 0; } @@ -2892,7 +2903,7 @@ void arm_v7m_cpu_do_interrupt(CPUState *cs) do_v7m_exception_exit(env); return; default: - cpu_abort(env, "Unhandled exception 0x%x\n", cs->exception_index); + cpu_abort(cs, "Unhandled exception 0x%x\n", cs->exception_index); return; /* Never happens. Keep compiler happy. */ } @@ -3017,7 +3028,7 @@ void arm_cpu_do_interrupt(CPUState *cs) offset = 4; break; default: - cpu_abort(env, "Unhandled exception 0x%x\n", cs->exception_index); + cpu_abort(cs, "Unhandled exception 0x%x\n", cs->exception_index); return; /* Never happens. Keep compiler happy. */ } /* High vectors. */ @@ -3695,6 +3706,8 @@ uint32_t HELPER(get_r13_banked)(CPUARMState *env, uint32_t mode) uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg) { + ARMCPU *cpu = arm_env_get_cpu(env); + switch (reg) { case 0: /* APSR */ return xpsr_read(env) & 0xf8000000; @@ -3725,13 +3738,15 @@ uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg) return env->v7m.control; default: /* ??? For debugging only. */ - cpu_abort(env, "Unimplemented system register read (%d)\n", reg); + cpu_abort(CPU(cpu), "Unimplemented system register read (%d)\n", reg); return 0; } } void HELPER(v7m_msr)(CPUARMState *env, uint32_t reg, uint32_t val) { + ARMCPU *cpu = arm_env_get_cpu(env); + switch (reg) { case 0: /* APSR */ xpsr_write(env, val, 0xf8000000); @@ -3794,7 +3809,7 @@ void HELPER(v7m_msr)(CPUARMState *env, uint32_t reg, uint32_t val) break; default: /* ??? For debugging only. */ - cpu_abort(env, "Unimplemented system register write (%d)\n", reg); + cpu_abort(CPU(cpu), "Unimplemented system register write (%d)\n", reg); return; } } diff --git a/target-arm/translate.c b/target-arm/translate.c index 2f02c183a7..fbe513b40d 100644 --- a/target-arm/translate.c +++ b/target-arm/translate.c @@ -10803,7 +10803,7 @@ static inline void gen_intermediate_code_internal(ARMCPU *cpu, if (dc->condjmp) { /* FIXME: This can theoretically happen with self-modifying code. */ - cpu_abort(env, "IO on conditional branch instruction"); + cpu_abort(cs, "IO on conditional branch instruction"); } gen_io_end(); } diff --git a/target-cris/helper.c b/target-cris/helper.c index d7fdc33647..ec84b57c0b 100644 --- a/target-cris/helper.c +++ b/target-cris/helper.c @@ -89,7 +89,7 @@ int cris_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw, rw, mmu_idx, 0); if (miss) { if (cs->exception_index == EXCP_BUSFAULT) { - cpu_abort(env, + cpu_abort(cs, "CRIS: Illegal recursive bus fault." "addr=%" VADDR_PRIx " rw=%d\n", address, rw); @@ -130,7 +130,7 @@ void crisv10_cpu_do_interrupt(CPUState *cs) if (env->dslot) { /* CRISv10 never takes interrupts while in a delay-slot. */ - cpu_abort(env, "CRIS: Interrupt on delay-slot\n"); + cpu_abort(cs, "CRIS: Interrupt on delay-slot\n"); } assert(!(env->pregs[PR_CCS] & PFIX_FLAG)); @@ -150,7 +150,7 @@ void crisv10_cpu_do_interrupt(CPUState *cs) break; case EXCP_BUSFAULT: - cpu_abort(env, "Unhandled busfault"); + cpu_abort(cs, "Unhandled busfault"); break; default: diff --git a/target-cris/translate.c b/target-cris/translate.c index 7e70940c9b..3e26b9b3c3 100644 --- a/target-cris/translate.c +++ b/target-cris/translate.c @@ -129,7 +129,7 @@ static void gen_BUG(DisasContext *dc, const char *file, int line) { printf("BUG: pc=%x %s %d\n", dc->pc, file, line); qemu_log("BUG: pc=%x %s %d\n", dc->pc, file, line); - cpu_abort(dc->env, "%s:%d\n", file, line); + cpu_abort(CPU(cris_env_get_cpu(dc->env)), "%s:%d\n", file, line); } static const char *regnames[] = @@ -272,7 +272,7 @@ static int cris_fetch(CPUCRISState *env, DisasContext *dc, uint32_t addr, break; } default: - cpu_abort(dc->env, "Invalid fetch size %d\n", size); + cpu_abort(CPU(cris_env_get_cpu(dc->env)), "Invalid fetch size %d\n", size); break; } return r; diff --git a/target-cris/translate_v10.c b/target-cris/translate_v10.c index d6ef084483..3f27456d19 100644 --- a/target-cris/translate_v10.c +++ b/target-cris/translate_v10.c @@ -340,7 +340,7 @@ static unsigned int dec10_quick_imm(DisasContext *dc) default: LOG_DIS("pc=%x mode=%x quickimm %d r%d r%d\n", dc->pc, dc->mode, dc->opcode, dc->src, dc->dst); - cpu_abort(dc->env, "Unhandled quickimm\n"); + cpu_abort(CPU(cris_env_get_cpu(dc->env)), "Unhandled quickimm\n"); break; } return 2; @@ -651,7 +651,7 @@ static unsigned int dec10_reg(DisasContext *dc) case 2: tmp = 1; break; case 1: tmp = 0; break; default: - cpu_abort(dc->env, "Unhandled BIAP"); + cpu_abort(CPU(cris_env_get_cpu(dc->env)), "Unhandled BIAP"); break; } @@ -669,7 +669,7 @@ static unsigned int dec10_reg(DisasContext *dc) default: LOG_DIS("pc=%x reg %d r%d r%d\n", dc->pc, dc->opcode, dc->src, dc->dst); - cpu_abort(dc->env, "Unhandled opcode"); + cpu_abort(CPU(cris_env_get_cpu(dc->env)), "Unhandled opcode"); break; } } else { @@ -745,7 +745,7 @@ static unsigned int dec10_reg(DisasContext *dc) default: LOG_DIS("pc=%x reg %d r%d r%d\n", dc->pc, dc->opcode, dc->src, dc->dst); - cpu_abort(dc->env, "Unhandled opcode"); + cpu_abort(CPU(cris_env_get_cpu(dc->env)), "Unhandled opcode"); break; } } @@ -1105,7 +1105,7 @@ static unsigned int dec10_ind(CPUCRISState *env, DisasContext *dc) default: LOG_DIS("pc=%x var-ind.%d %d r%d r%d\n", dc->pc, size, dc->opcode, dc->src, dc->dst); - cpu_abort(dc->env, "Unhandled opcode"); + cpu_abort(CPU(cris_env_get_cpu(dc->env)), "Unhandled opcode"); break; } return insn_len; @@ -1198,7 +1198,7 @@ static unsigned int dec10_ind(CPUCRISState *env, DisasContext *dc) break; default: LOG_DIS("ERROR pc=%x opcode=%d\n", dc->pc, dc->opcode); - cpu_abort(dc->env, "Unhandled opcode"); + cpu_abort(CPU(cris_env_get_cpu(dc->env)), "Unhandled opcode"); break; } diff --git a/target-i386/seg_helper.c b/target-i386/seg_helper.c index 4e134e4338..8c3f92c22b 100644 --- a/target-i386/seg_helper.c +++ b/target-i386/seg_helper.c @@ -95,6 +95,7 @@ static inline void load_seg_vm(CPUX86State *env, int seg, int selector) static inline void get_ss_esp_from_tss(CPUX86State *env, uint32_t *ss_ptr, uint32_t *esp_ptr, int dpl) { + X86CPU *cpu = x86_env_get_cpu(env); int type, index, shift; #if 0 @@ -112,11 +113,11 @@ static inline void get_ss_esp_from_tss(CPUX86State *env, uint32_t *ss_ptr, #endif if (!(env->tr.flags & DESC_P_MASK)) { - cpu_abort(env, "invalid tss"); + cpu_abort(CPU(cpu), "invalid tss"); } type = (env->tr.flags >> DESC_TYPE_SHIFT) & 0xf; if ((type & 7) != 1) { - cpu_abort(env, "invalid tss type"); + cpu_abort(CPU(cpu), "invalid tss type"); } shift = type >> 3; index = (dpl * 4 + 2) << shift; @@ -782,6 +783,7 @@ static void do_interrupt_protected(CPUX86State *env, int intno, int is_int, static inline target_ulong get_rsp_from_tss(CPUX86State *env, int level) { + X86CPU *cpu = x86_env_get_cpu(env); int index; #if 0 @@ -790,7 +792,7 @@ static inline target_ulong get_rsp_from_tss(CPUX86State *env, int level) #endif if (!(env->tr.flags & DESC_P_MASK)) { - cpu_abort(env, "invalid tss"); + cpu_abort(CPU(cpu), "invalid tss"); } index = 8 * level + 4; if ((index + 7) > env->tr.limit) { diff --git a/target-lm32/helper.c b/target-lm32/helper.c index 7de783b91d..3adfea9ef0 100644 --- a/target-lm32/helper.c +++ b/target-lm32/helper.c @@ -185,7 +185,7 @@ void lm32_cpu_do_interrupt(CPUState *cs) log_cpu_state_mask(CPU_LOG_INT, cs, 0); break; default: - cpu_abort(env, "unhandled exception type=%d\n", + cpu_abort(cs, "unhandled exception type=%d\n", cs->exception_index); break; } diff --git a/target-m68k/helper.c b/target-m68k/helper.c index fb43b81505..276fb4bcc9 100644 --- a/target-m68k/helper.c +++ b/target-m68k/helper.c @@ -132,6 +132,7 @@ void m68k_cpu_init_gdb(M68kCPU *cpu) void cpu_m68k_flush_flags(CPUM68KState *env, int cc_op) { + M68kCPU *cpu = m68k_env_get_cpu(env); int flags; uint32_t src; uint32_t dest; @@ -204,7 +205,7 @@ void cpu_m68k_flush_flags(CPUM68KState *env, int cc_op) flags |= CCF_C; break; default: - cpu_abort(env, "Bad CC_OP %d", cc_op); + cpu_abort(CPU(cpu), "Bad CC_OP %d", cc_op); } env->cc_op = CC_OP_FLAGS; env->cc_dest = flags; @@ -212,6 +213,8 @@ void cpu_m68k_flush_flags(CPUM68KState *env, int cc_op) void HELPER(movec)(CPUM68KState *env, uint32_t reg, uint32_t val) { + M68kCPU *cpu = m68k_env_get_cpu(env); + switch (reg) { case 0x02: /* CACR */ env->cacr = val; @@ -225,7 +228,7 @@ void HELPER(movec)(CPUM68KState *env, uint32_t reg, uint32_t val) break; /* TODO: Implement control registers. */ default: - cpu_abort(env, "Unimplemented control register write 0x%x = 0x%x\n", + cpu_abort(CPU(cpu), "Unimplemented control register write 0x%x = 0x%x\n", reg, val); } } diff --git a/target-m68k/m68k-semi.c b/target-m68k/m68k-semi.c index 2dea3cac90..9dffe8de60 100644 --- a/target-m68k/m68k-semi.c +++ b/target-m68k/m68k-semi.c @@ -461,7 +461,7 @@ void do_m68k_semihosting(CPUM68KState *env, int nr) #endif return; default: - cpu_abort(env, "Unsupported semihosting syscall %d\n", nr); + cpu_abort(CPU(m68k_env_get_cpu(env)), "Unsupported semihosting syscall %d\n", nr); result = 0; } failed: diff --git a/target-m68k/translate.c b/target-m68k/translate.c index a0e2f19e15..cd662891c8 100644 --- a/target-m68k/translate.c +++ b/target-m68k/translate.c @@ -881,8 +881,10 @@ DISAS_INSN(undef_fpu) DISAS_INSN(undef) { + M68kCPU *cpu = m68k_env_get_cpu(env); + gen_exception(s, s->pc - 2, EXCP_UNSUPPORTED); - cpu_abort(env, "Illegal instruction: %04x @ %08x", insn, s->pc - 2); + cpu_abort(CPU(cpu), "Illegal instruction: %04x @ %08x", insn, s->pc - 2); } DISAS_INSN(mulw) @@ -2082,12 +2084,14 @@ DISAS_INSN(wddata) DISAS_INSN(wdebug) { + M68kCPU *cpu = m68k_env_get_cpu(env); + if (IS_USER(s)) { gen_exception(s, s->pc - 2, EXCP_PRIVILEGE); return; } /* TODO: Implement wdebug. */ - cpu_abort(env, "WDEBUG not implemented"); + cpu_abort(CPU(cpu), "WDEBUG not implemented"); } DISAS_INSN(trap) @@ -2461,14 +2465,18 @@ DISAS_INSN(fbcc) DISAS_INSN(frestore) { + M68kCPU *cpu = m68k_env_get_cpu(env); + /* TODO: Implement frestore. */ - cpu_abort(env, "FRESTORE not implemented"); + cpu_abort(CPU(cpu), "FRESTORE not implemented"); } DISAS_INSN(fsave) { + M68kCPU *cpu = m68k_env_get_cpu(env); + /* TODO: Implement fsave. */ - cpu_abort(env, "FSAVE not implemented"); + cpu_abort(CPU(cpu), "FSAVE not implemented"); } static inline TCGv gen_mac_extract_word(DisasContext *s, TCGv val, int upper) diff --git a/target-microblaze/helper.c b/target-microblaze/helper.c index 48254154d3..11d8aa266d 100644 --- a/target-microblaze/helper.c +++ b/target-microblaze/helper.c @@ -98,7 +98,7 @@ int mb_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw, } if (cs->exception_index == EXCP_MMU) { - cpu_abort(env, "recursive faults\n"); + cpu_abort(cs, "recursive faults\n"); } /* TLB miss. */ @@ -259,7 +259,7 @@ void mb_cpu_do_interrupt(CPUState *cs) env->sregs[SR_PC] = env->btarget; break; default: - cpu_abort(env, "unhandled exception type=%d\n", + cpu_abort(cs, "unhandled exception type=%d\n", cs->exception_index); break; } diff --git a/target-microblaze/translate.c b/target-microblaze/translate.c index fbd6951d1a..4322f171c7 100644 --- a/target-microblaze/translate.c +++ b/target-microblaze/translate.c @@ -370,7 +370,7 @@ static void dec_pattern(DisasContext *dc) } break; default: - cpu_abort(dc->env, + cpu_abort(CPU(mb_env_get_cpu(dc->env)), "unsupported pattern insn opcode=%x\n", dc->opcode); break; } @@ -441,6 +441,8 @@ static inline void msr_write(DisasContext *dc, TCGv v) static void dec_msr(DisasContext *dc) { + MicroBlazeCPU *cpu = mb_env_get_cpu(dc->env); + CPUState *cs = CPU(cpu); TCGv t0, t1; unsigned int sr, to, rn; int mem_index = cpu_mmu_index(dc->env); @@ -537,7 +539,7 @@ static void dec_msr(DisasContext *dc) tcg_gen_st_tl(cpu_R[dc->ra], cpu_env, offsetof(CPUMBState, shr)); break; default: - cpu_abort(dc->env, "unknown mts reg %x\n", sr); + cpu_abort(CPU(mb_env_get_cpu(dc->env)), "unknown mts reg %x\n", sr); break; } } else { @@ -586,7 +588,7 @@ static void dec_msr(DisasContext *dc) cpu_env, offsetof(CPUMBState, pvr.regs[rn])); break; default: - cpu_abort(dc->env, "unknown mfs reg %x\n", sr); + cpu_abort(cs, "unknown mfs reg %x\n", sr); break; } } @@ -684,7 +686,7 @@ static void dec_mul(DisasContext *dc) t_gen_mulu(d[0], cpu_R[dc->rd], cpu_R[dc->ra], cpu_R[dc->rb]); break; default: - cpu_abort(dc->env, "unknown MUL insn %x\n", subcode); + cpu_abort(CPU(mb_env_get_cpu(dc->env)), "unknown MUL insn %x\n", subcode); break; } done: @@ -752,6 +754,8 @@ static void dec_barrel(DisasContext *dc) static void dec_bit(DisasContext *dc) { + MicroBlazeCPU *cpu = mb_env_get_cpu(dc->env); + CPUState *cs = CPU(cpu); TCGv t0; unsigned int op; int mem_index = cpu_mmu_index(dc->env); @@ -839,8 +843,8 @@ static void dec_bit(DisasContext *dc) tcg_gen_rotri_i32(cpu_R[dc->rd], cpu_R[dc->ra], 16); break; default: - cpu_abort(dc->env, "unknown bit oc=%x op=%x rd=%d ra=%d rb=%d\n", - dc->pc, op, dc->rd, dc->ra, dc->rb); + cpu_abort(cs, "unknown bit oc=%x op=%x rd=%d ra=%d rb=%d\n", + dc->pc, op, dc->rd, dc->ra, dc->rb); break; } } @@ -991,7 +995,7 @@ static void dec_load(DisasContext *dc) } break; default: - cpu_abort(dc->env, "Invalid reverse size\n"); + cpu_abort(CPU(mb_env_get_cpu(dc->env)), "Invalid reverse size\n"); break; } } @@ -1142,7 +1146,7 @@ static void dec_store(DisasContext *dc) } break; default: - cpu_abort(dc->env, "Invalid reverse size\n"); + cpu_abort(CPU(mb_env_get_cpu(dc->env)), "Invalid reverse size\n"); break; } } @@ -1193,7 +1197,7 @@ static inline void eval_cc(DisasContext *dc, unsigned int cc, tcg_gen_setcond_tl(TCG_COND_GT, d, a, b); break; default: - cpu_abort(dc->env, "Unknown condition code %x.\n", cc); + cpu_abort(CPU(mb_env_get_cpu(dc->env)), "Unknown condition code %x.\n", cc); break; } } @@ -1637,8 +1641,9 @@ static inline void decode(DisasContext *dc, uint32_t ir) LOG_DIS("nr_nops=%d\t", dc->nr_nops); dc->nr_nops++; - if (dc->nr_nops > 4) - cpu_abort(dc->env, "fetching nop sequence\n"); + if (dc->nr_nops > 4) { + cpu_abort(CPU(mb_env_get_cpu(dc->env)), "fetching nop sequence\n"); + } } /* bit 2 seems to indicate insn type. */ dc->type_b = ir & (1 << 29); @@ -1709,8 +1714,9 @@ gen_intermediate_code_internal(MicroBlazeCPU *cpu, TranslationBlock *tb, dc->abort_at_next_insn = 0; dc->nr_nops = 0; - if (pc_start & 3) - cpu_abort(env, "Microblaze: unaligned PC=%x\n", pc_start); + if (pc_start & 3) { + cpu_abort(cs, "Microblaze: unaligned PC=%x\n", pc_start); + } if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) { #if !SIM_COMPAT diff --git a/target-mips/op_helper.c b/target-mips/op_helper.c index de5a22329a..1a785c23d9 100644 --- a/target-mips/op_helper.c +++ b/target-mips/op_helper.c @@ -1344,6 +1344,7 @@ void helper_mtc0_compare(CPUMIPSState *env, target_ulong arg1) void helper_mtc0_status(CPUMIPSState *env, target_ulong arg1) { + MIPSCPU *cpu = mips_env_get_cpu(env); uint32_t val, old; uint32_t mask = env->CP0_Status_rw_bitmask; @@ -1365,7 +1366,9 @@ void helper_mtc0_status(CPUMIPSState *env, target_ulong arg1) case MIPS_HFLAG_UM: qemu_log(", UM\n"); break; case MIPS_HFLAG_SM: qemu_log(", SM\n"); break; case MIPS_HFLAG_KM: qemu_log("\n"); break; - default: cpu_abort(env, "Invalid MMU mode!\n"); break; + default: + cpu_abort(CPU(cpu), "Invalid MMU mode!\n"); + break; } } } @@ -1985,6 +1988,8 @@ static void debug_pre_eret(CPUMIPSState *env) static void debug_post_eret(CPUMIPSState *env) { + MIPSCPU *cpu = mips_env_get_cpu(env); + if (qemu_loglevel_mask(CPU_LOG_EXEC)) { qemu_log(" => PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx, env->active_tc.PC, env->CP0_EPC); @@ -1996,7 +2001,9 @@ static void debug_post_eret(CPUMIPSState *env) case MIPS_HFLAG_UM: qemu_log(", UM\n"); break; case MIPS_HFLAG_SM: qemu_log(", SM\n"); break; case MIPS_HFLAG_KM: qemu_log("\n"); break; - default: cpu_abort(env, "Invalid MMU mode!\n"); break; + default: + cpu_abort(CPU(cpu), "Invalid MMU mode!\n"); + break; } } } diff --git a/target-mips/translate_init.c b/target-mips/translate_init.c index 29d39e2a39..a64fd2b530 100644 --- a/target-mips/translate_init.c +++ b/target-mips/translate_init.c @@ -629,6 +629,8 @@ static void r4k_mmu_init (CPUMIPSState *env, const mips_def_t *def) static void mmu_init (CPUMIPSState *env, const mips_def_t *def) { + MIPSCPU *cpu = mips_env_get_cpu(env); + env->tlb = g_malloc0(sizeof(CPUMIPSTLBContext)); switch (def->mmu_type) { @@ -645,7 +647,7 @@ static void mmu_init (CPUMIPSState *env, const mips_def_t *def) case MMU_TYPE_R6000: case MMU_TYPE_R8000: default: - cpu_abort(env, "MMU type not supported\n"); + cpu_abort(CPU(cpu), "MMU type not supported\n"); } } #endif /* CONFIG_USER_ONLY */ diff --git a/target-openrisc/interrupt.c b/target-openrisc/interrupt.c index 087e2f1351..e312300853 100644 --- a/target-openrisc/interrupt.c +++ b/target-openrisc/interrupt.c @@ -57,7 +57,7 @@ void openrisc_cpu_do_interrupt(CPUState *cs) if (cs->exception_index > 0 && cs->exception_index < EXCP_NR) { env->pc = (cs->exception_index << 8); } else { - cpu_abort(env, "Unhandled exception 0x%x\n", cs->exception_index); + cpu_abort(cs, "Unhandled exception 0x%x\n", cs->exception_index); } #endif diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h index acf6909de7..91b7ae5534 100644 --- a/target-ppc/cpu.h +++ b/target-ppc/cpu.h @@ -2100,7 +2100,7 @@ static inline int booke206_tlbm_to_tlbn(CPUPPCState *env, ppcmas_tlb_t *tlbm) } } - cpu_abort(env, "Unknown TLBe: %d\n", id); + cpu_abort(CPU(ppc_env_get_cpu(env)), "Unknown TLBe: %d\n", id); return 0; } diff --git a/target-ppc/excp_helper.c b/target-ppc/excp_helper.c index 4a587303a8..a2226d1923 100644 --- a/target-ppc/excp_helper.c +++ b/target-ppc/excp_helper.c @@ -242,7 +242,7 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int excp_model, int excp) break; default: /* Should never occur */ - cpu_abort(env, "Invalid program exception %d. Aborting\n", + cpu_abort(cs, "Invalid program exception %d. Aborting\n", env->error_code); break; } @@ -302,26 +302,26 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int excp_model, int excp) break; } /* XXX: TODO */ - cpu_abort(env, "Debug exception is not implemented yet !\n"); + cpu_abort(cs, "Debug exception is not implemented yet !\n"); goto store_next; case POWERPC_EXCP_SPEU: /* SPE/embedded floating-point unavailable */ env->spr[SPR_BOOKE_ESR] = ESR_SPV; goto store_current; case POWERPC_EXCP_EFPDI: /* Embedded floating-point data interrupt */ /* XXX: TODO */ - cpu_abort(env, "Embedded floating point data exception " + cpu_abort(cs, "Embedded floating point data exception " "is not implemented yet !\n"); env->spr[SPR_BOOKE_ESR] = ESR_SPV; goto store_next; case POWERPC_EXCP_EFPRI: /* Embedded floating-point round interrupt */ /* XXX: TODO */ - cpu_abort(env, "Embedded floating point round exception " + cpu_abort(cs, "Embedded floating point round exception " "is not implemented yet !\n"); env->spr[SPR_BOOKE_ESR] = ESR_SPV; goto store_next; case POWERPC_EXCP_EPERFM: /* Embedded performance monitor interrupt */ /* XXX: TODO */ - cpu_abort(env, + cpu_abort(cs, "Performance counter exception is not implemented yet !\n"); goto store_next; case POWERPC_EXCP_DOORI: /* Embedded doorbell interrupt */ @@ -403,15 +403,15 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int excp_model, int excp) goto store_next; case POWERPC_EXCP_IO: /* IO error exception */ /* XXX: TODO */ - cpu_abort(env, "601 IO error exception is not implemented yet !\n"); + cpu_abort(cs, "601 IO error exception is not implemented yet !\n"); goto store_next; case POWERPC_EXCP_RUNM: /* Run mode exception */ /* XXX: TODO */ - cpu_abort(env, "601 run mode exception is not implemented yet !\n"); + cpu_abort(cs, "601 run mode exception is not implemented yet !\n"); goto store_next; case POWERPC_EXCP_EMUL: /* Emulation trap exception */ /* XXX: TODO */ - cpu_abort(env, "602 emulation trap exception " + cpu_abort(cs, "602 emulation trap exception " "is not implemented yet !\n"); goto store_next; case POWERPC_EXCP_IFTLB: /* Instruction fetch TLB error */ @@ -429,7 +429,7 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int excp_model, int excp) case POWERPC_EXCP_74xx: goto tlb_miss_74xx; default: - cpu_abort(env, "Invalid instruction TLB miss exception\n"); + cpu_abort(cs, "Invalid instruction TLB miss exception\n"); break; } break; @@ -448,7 +448,7 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int excp_model, int excp) case POWERPC_EXCP_74xx: goto tlb_miss_74xx; default: - cpu_abort(env, "Invalid data load TLB miss exception\n"); + cpu_abort(cs, "Invalid data load TLB miss exception\n"); break; } break; @@ -534,30 +534,30 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int excp_model, int excp) msr |= env->error_code; /* key bit */ break; default: - cpu_abort(env, "Invalid data store TLB miss exception\n"); + cpu_abort(cs, "Invalid data store TLB miss exception\n"); break; } goto store_next; case POWERPC_EXCP_FPA: /* Floating-point assist exception */ /* XXX: TODO */ - cpu_abort(env, "Floating point assist exception " + cpu_abort(cs, "Floating point assist exception " "is not implemented yet !\n"); goto store_next; case POWERPC_EXCP_DABR: /* Data address breakpoint */ /* XXX: TODO */ - cpu_abort(env, "DABR exception is not implemented yet !\n"); + cpu_abort(cs, "DABR exception is not implemented yet !\n"); goto store_next; case POWERPC_EXCP_IABR: /* Instruction address breakpoint */ /* XXX: TODO */ - cpu_abort(env, "IABR exception is not implemented yet !\n"); + cpu_abort(cs, "IABR exception is not implemented yet !\n"); goto store_next; case POWERPC_EXCP_SMI: /* System management interrupt */ /* XXX: TODO */ - cpu_abort(env, "SMI exception is not implemented yet !\n"); + cpu_abort(cs, "SMI exception is not implemented yet !\n"); goto store_next; case POWERPC_EXCP_THERM: /* Thermal interrupt */ /* XXX: TODO */ - cpu_abort(env, "Thermal management exception " + cpu_abort(cs, "Thermal management exception " "is not implemented yet !\n"); goto store_next; case POWERPC_EXCP_PERFM: /* Embedded performance monitor interrupt */ @@ -565,36 +565,36 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int excp_model, int excp) new_msr |= (target_ulong)MSR_HVB; } /* XXX: TODO */ - cpu_abort(env, + cpu_abort(cs, "Performance counter exception is not implemented yet !\n"); goto store_next; case POWERPC_EXCP_VPUA: /* Vector assist exception */ /* XXX: TODO */ - cpu_abort(env, "VPU assist exception is not implemented yet !\n"); + cpu_abort(cs, "VPU assist exception is not implemented yet !\n"); goto store_next; case POWERPC_EXCP_SOFTP: /* Soft patch exception */ /* XXX: TODO */ - cpu_abort(env, + cpu_abort(cs, "970 soft-patch exception is not implemented yet !\n"); goto store_next; case POWERPC_EXCP_MAINT: /* Maintenance exception */ /* XXX: TODO */ - cpu_abort(env, + cpu_abort(cs, "970 maintenance exception is not implemented yet !\n"); goto store_next; case POWERPC_EXCP_MEXTBR: /* Maskable external breakpoint */ /* XXX: TODO */ - cpu_abort(env, "Maskable external exception " + cpu_abort(cs, "Maskable external exception " "is not implemented yet !\n"); goto store_next; case POWERPC_EXCP_NMEXTBR: /* Non maskable external breakpoint */ /* XXX: TODO */ - cpu_abort(env, "Non maskable external exception " + cpu_abort(cs, "Non maskable external exception " "is not implemented yet !\n"); goto store_next; default: excp_invalid: - cpu_abort(env, "Invalid PowerPC exception %d. Aborting\n", excp); + cpu_abort(cs, "Invalid PowerPC exception %d. Aborting\n", excp); break; store_current: /* save current instruction location */ @@ -636,7 +636,7 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int excp_model, int excp) /* Jump to handler */ vector = env->excp_vectors[excp]; if (vector == (target_ulong)-1ULL) { - cpu_abort(env, "Raised an exception without defined vector %d\n", + cpu_abort(cs, "Raised an exception without defined vector %d\n", excp); } vector |= env->excp_prefix; diff --git a/target-ppc/kvm.c b/target-ppc/kvm.c index 81ec959b23..9974b10ccb 100644 --- a/target-ppc/kvm.c +++ b/target-ppc/kvm.c @@ -1504,7 +1504,6 @@ int kvmppc_get_hypercall(CPUPPCState *env, uint8_t *buf, int buf_len) void kvmppc_set_papr(PowerPCCPU *cpu) { - CPUPPCState *env = &cpu->env; CPUState *cs = CPU(cpu); struct kvm_enable_cap cap = {}; int ret; @@ -1513,7 +1512,7 @@ void kvmppc_set_papr(PowerPCCPU *cpu) ret = kvm_vcpu_ioctl(cs, KVM_ENABLE_CAP, &cap); if (ret) { - cpu_abort(env, "This KVM version does not support PAPR\n"); + cpu_abort(cs, "This KVM version does not support PAPR\n"); } /* Update the capability flag so we sync the right information @@ -1523,7 +1522,6 @@ void kvmppc_set_papr(PowerPCCPU *cpu) void kvmppc_set_mpic_proxy(PowerPCCPU *cpu, int mpic_proxy) { - CPUPPCState *env = &cpu->env; CPUState *cs = CPU(cpu); struct kvm_enable_cap cap = {}; int ret; @@ -1533,7 +1531,7 @@ void kvmppc_set_mpic_proxy(PowerPCCPU *cpu, int mpic_proxy) ret = kvm_vcpu_ioctl(cs, KVM_ENABLE_CAP, &cap); if (ret && mpic_proxy) { - cpu_abort(env, "This KVM version does not support EPR\n"); + cpu_abort(cs, "This KVM version does not support EPR\n"); } } diff --git a/target-ppc/mmu_helper.c b/target-ppc/mmu_helper.c index c75b4f2a71..845a7252b3 100644 --- a/target-ppc/mmu_helper.c +++ b/target-ppc/mmu_helper.c @@ -746,9 +746,11 @@ static int mmu40x_get_physical_address(CPUPPCState *env, mmu_ctx_t *ctx, void store_40x_sler(CPUPPCState *env, uint32_t val) { + PowerPCCPU *cpu = ppc_env_get_cpu(env); + /* XXX: TO BE FIXED */ if (val != 0x00000000) { - cpu_abort(env, "Little-endian regions are not supported by now\n"); + cpu_abort(CPU(cpu), "Little-endian regions are not supported by now\n"); } env->spr[SPR_405_SLER] = val; } @@ -1344,6 +1346,7 @@ static inline int check_physical(CPUPPCState *env, mmu_ctx_t *ctx, static int get_physical_address(CPUPPCState *env, mmu_ctx_t *ctx, target_ulong eaddr, int rw, int access_type) { + PowerPCCPU *cpu = ppc_env_get_cpu(env); int ret = -1; bool real_mode = (access_type == ACCESS_CODE && msr_ir == 0) || (access_type != ACCESS_CODE && msr_dr == 0); @@ -1388,17 +1391,17 @@ static int get_physical_address(CPUPPCState *env, mmu_ctx_t *ctx, break; case POWERPC_MMU_MPC8xx: /* XXX: TODO */ - cpu_abort(env, "MPC8xx MMU model is not implemented\n"); + cpu_abort(CPU(cpu), "MPC8xx MMU model is not implemented\n"); break; case POWERPC_MMU_REAL: if (real_mode) { ret = check_physical(env, ctx, eaddr, rw); } else { - cpu_abort(env, "PowerPC in real mode do not do any translation\n"); + cpu_abort(CPU(cpu), "PowerPC in real mode do not do any translation\n"); } return -1; default: - cpu_abort(env, "Unknown or invalid MMU model\n"); + cpu_abort(CPU(cpu), "Unknown or invalid MMU model\n"); return -1; } #if 0 @@ -1543,14 +1546,14 @@ static int cpu_ppc_handle_mmu_fault(CPUPPCState *env, target_ulong address, return -1; case POWERPC_MMU_MPC8xx: /* XXX: TODO */ - cpu_abort(env, "MPC8xx MMU model is not implemented\n"); + cpu_abort(cs, "MPC8xx MMU model is not implemented\n"); break; case POWERPC_MMU_REAL: - cpu_abort(env, "PowerPC in real mode should never raise " + cpu_abort(cs, "PowerPC in real mode should never raise " "any MMU exceptions\n"); return -1; default: - cpu_abort(env, "Unknown or invalid MMU model\n"); + cpu_abort(cs, "Unknown or invalid MMU model\n"); return -1; } break; @@ -1623,7 +1626,7 @@ static int cpu_ppc_handle_mmu_fault(CPUPPCState *env, target_ulong address, break; case POWERPC_MMU_MPC8xx: /* XXX: TODO */ - cpu_abort(env, "MPC8xx MMU model is not implemented\n"); + cpu_abort(cs, "MPC8xx MMU model is not implemented\n"); break; case POWERPC_MMU_BOOKE206: booke206_update_mas_tlb_miss(env, address, rw); @@ -1635,11 +1638,11 @@ static int cpu_ppc_handle_mmu_fault(CPUPPCState *env, target_ulong address, env->spr[SPR_BOOKE_ESR] = rw ? ESR_ST : 0; return -1; case POWERPC_MMU_REAL: - cpu_abort(env, "PowerPC in real mode should never raise " + cpu_abort(cs, "PowerPC in real mode should never raise " "any MMU exceptions\n"); return -1; default: - cpu_abort(env, "Unknown or invalid MMU model\n"); + cpu_abort(cs, "Unknown or invalid MMU model\n"); return -1; } break; @@ -1893,6 +1896,8 @@ void helper_store_601_batl(CPUPPCState *env, uint32_t nr, target_ulong value) /* TLB management */ void ppc_tlb_invalidate_all(CPUPPCState *env) { + PowerPCCPU *cpu = ppc_env_get_cpu(env); + switch (env->mmu_model) { case POWERPC_MMU_SOFT_6xx: case POWERPC_MMU_SOFT_74xx: @@ -1903,11 +1908,11 @@ void ppc_tlb_invalidate_all(CPUPPCState *env) ppc4xx_tlb_invalidate_all(env); break; case POWERPC_MMU_REAL: - cpu_abort(env, "No TLB for PowerPC 4xx in real mode\n"); + cpu_abort(CPU(cpu), "No TLB for PowerPC 4xx in real mode\n"); break; case POWERPC_MMU_MPC8xx: /* XXX: TODO */ - cpu_abort(env, "MPC8xx MMU model is not implemented\n"); + cpu_abort(CPU(cpu), "MPC8xx MMU model is not implemented\n"); break; case POWERPC_MMU_BOOKE: tlb_flush(env, 1); @@ -1927,7 +1932,7 @@ void ppc_tlb_invalidate_all(CPUPPCState *env) break; default: /* XXX: TODO */ - cpu_abort(env, "Unknown MMU model\n"); + cpu_abort(CPU(cpu), "Unknown MMU model\n"); break; } } @@ -1935,6 +1940,8 @@ void ppc_tlb_invalidate_all(CPUPPCState *env) void ppc_tlb_invalidate_one(CPUPPCState *env, target_ulong addr) { #if !defined(FLUSH_ALL_TLBS) + PowerPCCPU *cpu = ppc_env_get_cpu(env); + addr &= TARGET_PAGE_MASK; switch (env->mmu_model) { case POWERPC_MMU_SOFT_6xx: @@ -1949,19 +1956,19 @@ void ppc_tlb_invalidate_one(CPUPPCState *env, target_ulong addr) ppc4xx_tlb_invalidate_virt(env, addr, env->spr[SPR_40x_PID]); break; case POWERPC_MMU_REAL: - cpu_abort(env, "No TLB for PowerPC 4xx in real mode\n"); + cpu_abort(CPU(cpu), "No TLB for PowerPC 4xx in real mode\n"); break; case POWERPC_MMU_MPC8xx: /* XXX: TODO */ - cpu_abort(env, "MPC8xx MMU model is not implemented\n"); + cpu_abort(CPU(cpu), "MPC8xx MMU model is not implemented\n"); break; case POWERPC_MMU_BOOKE: /* XXX: TODO */ - cpu_abort(env, "BookE MMU model is not implemented\n"); + cpu_abort(CPU(cpu), "BookE MMU model is not implemented\n"); break; case POWERPC_MMU_BOOKE206: /* XXX: TODO */ - cpu_abort(env, "BookE 2.06 MMU model is not implemented\n"); + cpu_abort(CPU(cpu), "BookE 2.06 MMU model is not implemented\n"); break; case POWERPC_MMU_32B: case POWERPC_MMU_601: @@ -2002,7 +2009,7 @@ void ppc_tlb_invalidate_one(CPUPPCState *env, target_ulong addr) #endif /* defined(TARGET_PPC64) */ default: /* XXX: TODO */ - cpu_abort(env, "Unknown MMU model\n"); + cpu_abort(CPU(cpu), "Unknown MMU model\n"); break; } #else @@ -2317,6 +2324,7 @@ target_ulong helper_4xx_tlbre_lo(CPUPPCState *env, target_ulong entry) void helper_4xx_tlbwe_hi(CPUPPCState *env, target_ulong entry, target_ulong val) { + PowerPCCPU *cpu = ppc_env_get_cpu(env); ppcemb_tlb_t *tlb; target_ulong page, end; @@ -2340,7 +2348,7 @@ void helper_4xx_tlbwe_hi(CPUPPCState *env, target_ulong entry, * of the ppc or ppc64 one */ if ((val & PPC4XX_TLBHI_V) && tlb->size < TARGET_PAGE_SIZE) { - cpu_abort(env, "TLB size " TARGET_FMT_lu " < %u " + cpu_abort(CPU(cpu), "TLB size " TARGET_FMT_lu " < %u " "are not supported (%d)\n", tlb->size, TARGET_PAGE_SIZE, (int)((val >> 7) & 0x7)); } @@ -2349,7 +2357,7 @@ void helper_4xx_tlbwe_hi(CPUPPCState *env, target_ulong entry, tlb->prot |= PAGE_VALID; if (val & PPC4XX_TLBHI_E) { /* XXX: TO BE FIXED */ - cpu_abort(env, + cpu_abort(CPU(cpu), "Little-endian TLB entries are not supported by now\n"); } } else { @@ -2545,6 +2553,7 @@ target_ulong helper_440_tlbsx(CPUPPCState *env, target_ulong address) static ppcmas_tlb_t *booke206_cur_tlb(CPUPPCState *env) { + PowerPCCPU *cpu = ppc_env_get_cpu(env); uint32_t tlbncfg = 0; int esel = (env->spr[SPR_BOOKE_MAS0] & MAS0_ESEL_MASK) >> MAS0_ESEL_SHIFT; int ea = (env->spr[SPR_BOOKE_MAS2] & MAS2_EPN_MASK); @@ -2554,7 +2563,7 @@ static ppcmas_tlb_t *booke206_cur_tlb(CPUPPCState *env) tlbncfg = env->spr[SPR_BOOKE_TLB0CFG + tlb]; if ((tlbncfg & TLBnCFG_HES) && (env->spr[SPR_BOOKE_MAS0] & MAS0_HES)) { - cpu_abort(env, "we don't support HES yet\n"); + cpu_abort(CPU(cpu), "we don't support HES yet\n"); } return booke206_get_tlbm(env, tlb, ea, esel); @@ -2569,6 +2578,7 @@ void helper_booke_setpid(CPUPPCState *env, uint32_t pidn, target_ulong pid) void helper_booke206_tlbwe(CPUPPCState *env) { + PowerPCCPU *cpu = ppc_env_get_cpu(env); uint32_t tlbncfg, tlbn; ppcmas_tlb_t *tlb; uint32_t size_tlb, size_ps; @@ -2622,7 +2632,7 @@ void helper_booke206_tlbwe(CPUPPCState *env) } if (msr_gs) { - cpu_abort(env, "missing HV implementation\n"); + cpu_abort(CPU(cpu), "missing HV implementation\n"); } tlb->mas7_3 = ((uint64_t)env->spr[SPR_BOOKE_MAS7] << 32) | env->spr[SPR_BOOKE_MAS3]; diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c index e22d82f604..267a3765b4 100644 --- a/target-ppc/translate_init.c +++ b/target-ppc/translate_init.c @@ -4432,6 +4432,7 @@ enum fsl_e500_version { static void init_proc_e500 (CPUPPCState *env, int version) { + PowerPCCPU *cpu = ppc_env_get_cpu(env); uint32_t tlbncfg[2]; uint64_t ivor_mask; uint64_t ivpr_mask = 0xFFFF0000ULL; @@ -4490,7 +4491,7 @@ static void init_proc_e500 (CPUPPCState *env, int version) tlbncfg[1] = gen_tlbncfg(64, 1, 12, TLBnCFG_AVAIL | TLBnCFG_IPROT, 64); break; default: - cpu_abort(env, "Unknown CPU: " TARGET_FMT_lx "\n", env->spr[SPR_PVR]); + cpu_abort(CPU(cpu), "Unknown CPU: " TARGET_FMT_lx "\n", env->spr[SPR_PVR]); } #endif /* Cache sizes */ @@ -4507,7 +4508,7 @@ static void init_proc_e500 (CPUPPCState *env, int version) l1cfg0 |= 0x1000000; /* 64 byte cache block size */ break; default: - cpu_abort(env, "Unknown CPU: " TARGET_FMT_lx "\n", env->spr[SPR_PVR]); + cpu_abort(CPU(cpu), "Unknown CPU: " TARGET_FMT_lx "\n", env->spr[SPR_PVR]); } gen_spr_BookE206(env, 0x000000DF, tlbncfg); /* XXX : not implemented */ diff --git a/target-s390x/cc_helper.c b/target-s390x/cc_helper.c index d845f20de5..9e676a5ca7 100644 --- a/target-s390x/cc_helper.c +++ b/target-s390x/cc_helper.c @@ -407,6 +407,7 @@ static uint32_t cc_calc_flogr(uint64_t dst) static uint32_t do_calc_cc(CPUS390XState *env, uint32_t cc_op, uint64_t src, uint64_t dst, uint64_t vr) { + S390CPU *cpu = s390_env_get_cpu(env); uint32_t r = 0; switch (cc_op) { @@ -524,7 +525,7 @@ static uint32_t do_calc_cc(CPUS390XState *env, uint32_t cc_op, break; default: - cpu_abort(env, "Unknown CC operation: %s\n", cc_name(cc_op)); + cpu_abort(CPU(cpu), "Unknown CC operation: %s\n", cc_name(cc_op)); } HELPER_LOG("%s: %15s 0x%016lx 0x%016lx 0x%016lx = %d\n", __func__, diff --git a/target-s390x/fpu_helper.c b/target-s390x/fpu_helper.c index 94375b6a63..3e9c7b2d68 100644 --- a/target-s390x/fpu_helper.c +++ b/target-s390x/fpu_helper.c @@ -80,6 +80,8 @@ static void handle_exceptions(CPUS390XState *env, uintptr_t retaddr) static inline int float_comp_to_cc(CPUS390XState *env, int float_compare) { + S390CPU *cpu = s390_env_get_cpu(env); + switch (float_compare) { case float_relation_equal: return 0; @@ -90,7 +92,7 @@ static inline int float_comp_to_cc(CPUS390XState *env, int float_compare) case float_relation_unordered: return 3; default: - cpu_abort(env, "unknown return value for float compare\n"); + cpu_abort(CPU(cpu), "unknown return value for float compare\n"); } } diff --git a/target-s390x/helper.c b/target-s390x/helper.c index 6262f42762..d4ea7d56d1 100644 --- a/target-s390x/helper.c +++ b/target-s390x/helper.c @@ -116,6 +116,7 @@ static void trigger_pgm_exception(CPUS390XState *env, uint32_t code, static int trans_bits(CPUS390XState *env, uint64_t mode) { + S390CPU *cpu = s390_env_get_cpu(env); int bits = 0; switch (mode) { @@ -129,7 +130,7 @@ static int trans_bits(CPUS390XState *env, uint64_t mode) bits = 3; break; default: - cpu_abort(env, "unknown asc mode\n"); + cpu_abort(CPU(cpu), "unknown asc mode\n"); break; } @@ -479,13 +480,14 @@ static uint64_t get_psw_mask(CPUS390XState *env) static LowCore *cpu_map_lowcore(CPUS390XState *env) { + S390CPU *cpu = s390_env_get_cpu(env); LowCore *lowcore; hwaddr len = sizeof(LowCore); lowcore = cpu_physical_memory_map(env->psa, &len, 1); if (len < sizeof(LowCore)) { - cpu_abort(env, "Could not map lowcore\n"); + cpu_abort(CPU(cpu), "Could not map lowcore\n"); } return lowcore; @@ -583,16 +585,17 @@ static void do_program_interrupt(CPUS390XState *env) static void do_ext_interrupt(CPUS390XState *env) { + S390CPU *cpu = s390_env_get_cpu(env); uint64_t mask, addr; LowCore *lowcore; ExtQueue *q; if (!(env->psw.mask & PSW_MASK_EXT)) { - cpu_abort(env, "Ext int w/o ext mask\n"); + cpu_abort(CPU(cpu), "Ext int w/o ext mask\n"); } if (env->ext_index < 0 || env->ext_index > MAX_EXT_QUEUE) { - cpu_abort(env, "Ext queue overrun: %d\n", env->ext_index); + cpu_abort(CPU(cpu), "Ext queue overrun: %d\n", env->ext_index); } q = &env->ext_queue[env->ext_index]; @@ -622,6 +625,7 @@ static void do_ext_interrupt(CPUS390XState *env) static void do_io_interrupt(CPUS390XState *env) { + S390CPU *cpu = s390_env_get_cpu(env); LowCore *lowcore; IOIntQueue *q; uint8_t isc; @@ -629,7 +633,7 @@ static void do_io_interrupt(CPUS390XState *env) int found = 0; if (!(env->psw.mask & PSW_MASK_IO)) { - cpu_abort(env, "I/O int w/o I/O mask\n"); + cpu_abort(CPU(cpu), "I/O int w/o I/O mask\n"); } for (isc = 0; isc < ARRAY_SIZE(env->io_index); isc++) { @@ -639,7 +643,7 @@ static void do_io_interrupt(CPUS390XState *env) continue; } if (env->io_index[isc] > MAX_IO_QUEUE) { - cpu_abort(env, "I/O queue overrun for isc %d: %d\n", + cpu_abort(CPU(cpu), "I/O queue overrun for isc %d: %d\n", isc, env->io_index[isc]); } @@ -686,24 +690,25 @@ static void do_io_interrupt(CPUS390XState *env) static void do_mchk_interrupt(CPUS390XState *env) { + S390CPU *cpu = s390_env_get_cpu(env); uint64_t mask, addr; LowCore *lowcore; MchkQueue *q; int i; if (!(env->psw.mask & PSW_MASK_MCHECK)) { - cpu_abort(env, "Machine check w/o mchk mask\n"); + cpu_abort(CPU(cpu), "Machine check w/o mchk mask\n"); } if (env->mchk_index < 0 || env->mchk_index > MAX_MCHK_QUEUE) { - cpu_abort(env, "Mchk queue overrun: %d\n", env->mchk_index); + cpu_abort(CPU(cpu), "Mchk queue overrun: %d\n", env->mchk_index); } q = &env->mchk_queue[env->mchk_index]; if (q->type != 1) { /* Don't know how to handle this... */ - cpu_abort(env, "Unknown machine check type %d\n", q->type); + cpu_abort(CPU(cpu), "Unknown machine check type %d\n", q->type); } if (!(env->cregs[14] & (1 << 28))) { /* CRW machine checks disabled */ diff --git a/target-s390x/int_helper.c b/target-s390x/int_helper.c index 85e49aafa6..6a929ca1f3 100644 --- a/target-s390x/int_helper.c +++ b/target-s390x/int_helper.c @@ -106,9 +106,10 @@ uint64_t HELPER(divu64)(CPUS390XState *env, uint64_t ah, uint64_t al, runtime_exception(env, PGM_FIXPT_DIVIDE, GETPC()); } #else + S390CPU *cpu = s390_env_get_cpu(env); /* 32-bit hosts would need special wrapper functionality - just abort if we encounter such a case; it's very unlikely anyways. */ - cpu_abort(env, "128 -> 64/64 division not implemented\n"); + cpu_abort(CPU(cpu), "128 -> 64/64 division not implemented\n"); #endif } return ret; diff --git a/target-s390x/mem_helper.c b/target-s390x/mem_helper.c index e1c2ac04d1..21632848ac 100644 --- a/target-s390x/mem_helper.c +++ b/target-s390x/mem_helper.c @@ -72,6 +72,7 @@ void tlb_fill(CPUState *cs, target_ulong addr, int is_write, int mmu_idx, static void mvc_fast_memset(CPUS390XState *env, uint32_t l, uint64_t dest, uint8_t byte) { + S390CPU *cpu = s390_env_get_cpu(env); hwaddr dest_phys; hwaddr len = l; void *dest_p; @@ -80,7 +81,7 @@ static void mvc_fast_memset(CPUS390XState *env, uint32_t l, uint64_t dest, if (mmu_translate(env, dest, 1, asc, &dest_phys, &flags)) { cpu_stb_data(env, dest, byte); - cpu_abort(env, "should never reach here"); + cpu_abort(CPU(cpu), "should never reach here"); } dest_phys |= dest & ~TARGET_PAGE_MASK; @@ -94,6 +95,7 @@ static void mvc_fast_memset(CPUS390XState *env, uint32_t l, uint64_t dest, static void mvc_fast_memmove(CPUS390XState *env, uint32_t l, uint64_t dest, uint64_t src) { + S390CPU *cpu = s390_env_get_cpu(env); hwaddr dest_phys; hwaddr src_phys; hwaddr len = l; @@ -104,13 +106,13 @@ static void mvc_fast_memmove(CPUS390XState *env, uint32_t l, uint64_t dest, if (mmu_translate(env, dest, 1, asc, &dest_phys, &flags)) { cpu_stb_data(env, dest, 0); - cpu_abort(env, "should never reach here"); + cpu_abort(CPU(cpu), "should never reach here"); } dest_phys |= dest & ~TARGET_PAGE_MASK; if (mmu_translate(env, src, 0, asc, &src_phys, &flags)) { cpu_ldub_data(env, src); - cpu_abort(env, "should never reach here"); + cpu_abort(CPU(cpu), "should never reach here"); } src_phys |= src & ~TARGET_PAGE_MASK; @@ -483,6 +485,7 @@ static uint32_t helper_icm(CPUS390XState *env, uint32_t r1, uint64_t address, uint32_t HELPER(ex)(CPUS390XState *env, uint32_t cc, uint64_t v1, uint64_t addr, uint64_t ret) { + S390CPU *cpu = s390_env_get_cpu(env); uint16_t insn = cpu_lduw_code(env, addr); HELPER_LOG("%s: v1 0x%lx addr 0x%lx insn 0x%x\n", __func__, v1, addr, @@ -534,7 +537,7 @@ uint32_t HELPER(ex)(CPUS390XState *env, uint32_t cc, uint64_t v1, cc = helper_icm(env, r1, get_address(env, 0, b2, d2), r3); } else { abort: - cpu_abort(env, "EXECUTE on instruction prefix 0x%x not implemented\n", + cpu_abort(CPU(cpu), "EXECUTE on instruction prefix 0x%x not implemented\n", insn); } return cc; diff --git a/target-sh4/helper.c b/target-sh4/helper.c index 0357cebb81..ba0f269f52 100644 --- a/target-sh4/helper.c +++ b/target-sh4/helper.c @@ -234,15 +234,21 @@ static void update_itlb_use(CPUSH4State * env, int itlbnb) static int itlb_replacement(CPUSH4State * env) { - if ((env->mmucr & 0xe0000000) == 0xe0000000) + SuperHCPU *cpu = sh_env_get_cpu(env); + + if ((env->mmucr & 0xe0000000) == 0xe0000000) { return 0; - if ((env->mmucr & 0x98000000) == 0x18000000) + } + if ((env->mmucr & 0x98000000) == 0x18000000) { return 1; - if ((env->mmucr & 0x54000000) == 0x04000000) + } + if ((env->mmucr & 0x54000000) == 0x04000000) { return 2; - if ((env->mmucr & 0x2c000000) == 0x00000000) + } + if ((env->mmucr & 0x2c000000) == 0x00000000) { return 3; - cpu_abort(env, "Unhandled itlb_replacement"); + } + cpu_abort(CPU(cpu), "Unhandled itlb_replacement"); } /* Find the corresponding entry in the right TLB @@ -498,7 +504,7 @@ int superh_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw, cs->exception_index = 0x100; break; default: - cpu_abort(env, "Unhandled MMU fault"); + cpu_abort(cs, "Unhandled MMU fault"); } return 1; } @@ -522,6 +528,7 @@ hwaddr superh_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) void cpu_load_tlb(CPUSH4State * env) { + SuperHCPU *cpu = sh_env_get_cpu(env); int n = cpu_mmucr_urc(env->mmucr); tlb_t * entry = &env->utlb[n]; @@ -551,7 +558,7 @@ void cpu_load_tlb(CPUSH4State * env) entry->size = 1024 * 1024; /* 1M */ break; default: - cpu_abort(env, "Unhandled load_tlb"); + cpu_abort(CPU(cpu), "Unhandled load_tlb"); break; } entry->sh = (uint8_t)cpu_ptel_sh(env->ptel); diff --git a/target-sh4/op_helper.c b/target-sh4/op_helper.c index b3ce7bad53..720a97b1d1 100644 --- a/target-sh4/op_helper.c +++ b/target-sh4/op_helper.c @@ -58,8 +58,10 @@ void tlb_fill(CPUState *cs, target_ulong addr, int is_write, int mmu_idx, void helper_ldtlb(CPUSH4State *env) { #ifdef CONFIG_USER_ONLY + SuperHCPU *cpu = sh_env_get_cpu(env); + /* XXXXX */ - cpu_abort(env, "Unhandled ldtlb"); + cpu_abort(CPU(cpu), "Unhandled ldtlb"); #else cpu_load_tlb(env); #endif diff --git a/target-sparc/int32_helper.c b/target-sparc/int32_helper.c index f350a903e0..7c380ba2a1 100644 --- a/target-sparc/int32_helper.c +++ b/target-sparc/int32_helper.c @@ -109,7 +109,7 @@ void sparc_cpu_do_interrupt(CPUState *cs) env->def->features & CPU_FEATURE_TA0_SHUTDOWN) { qemu_system_shutdown_request(); } else { - cpu_abort(env, "Trap 0x%02x while interrupts disabled, Error state", + cpu_abort(cs, "Trap 0x%02x while interrupts disabled, Error state", cs->exception_index); } return; diff --git a/target-sparc/int64_helper.c b/target-sparc/int64_helper.c index 1744245f70..bf242323a4 100644 --- a/target-sparc/int64_helper.c +++ b/target-sparc/int64_helper.c @@ -111,7 +111,7 @@ void sparc_cpu_do_interrupt(CPUState *cs) #endif #if !defined(CONFIG_USER_ONLY) if (env->tl >= env->maxtl) { - cpu_abort(env, "Trap 0x%04x while trap level (%d) >= MAXTL (%d)," + cpu_abort(cs, "Trap 0x%04x while trap level (%d) >= MAXTL (%d)," " Error state", cs->exception_index, env->tl, env->maxtl); return; } diff --git a/target-unicore32/helper.c b/target-unicore32/helper.c index 29cf5755bc..195e1bfca9 100644 --- a/target-unicore32/helper.c +++ b/target-unicore32/helper.c @@ -229,26 +229,22 @@ void helper_cp1_putc(target_ulong x) #ifdef CONFIG_USER_ONLY void switch_mode(CPUUniCore32State *env, int mode) { + UniCore32CPU *cpu = uc32_env_get_cpu(env); + if (mode != ASR_MODE_USER) { - cpu_abort(env, "Tried to switch out of user mode\n"); + cpu_abort(CPU(cpu), "Tried to switch out of user mode\n"); } } void uc32_cpu_do_interrupt(CPUState *cs) { - UniCore32CPU *cpu = UNICORE32_CPU(cs); - CPUUniCore32State *env = &cpu->env; - - cpu_abort(env, "NO interrupt in user mode\n"); + cpu_abort(cs, "NO interrupt in user mode\n"); } int uc32_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int access_type, int mmu_idx) { - UniCore32CPU *cpu = UNICORE32_CPU(cs); - CPUUniCore32State *env = &cpu->env; - - cpu_abort(env, "NO mmu fault in user mode\n"); + cpu_abort(cs, "NO mmu fault in user mode\n"); return 1; } #endif diff --git a/target-unicore32/softmmu.c b/target-unicore32/softmmu.c index a55355ebe8..39ecd98907 100644 --- a/target-unicore32/softmmu.c +++ b/target-unicore32/softmmu.c @@ -33,6 +33,8 @@ /* Map CPU modes onto saved register banks. */ static inline int bank_number(CPUUniCore32State *env, int mode) { + UniCore32CPU *cpu = uc32_env_get_cpu(env); + switch (mode) { case ASR_MODE_USER: case ASR_MODE_SUSR: @@ -46,7 +48,7 @@ static inline int bank_number(CPUUniCore32State *env, int mode) case ASR_MODE_INTR: return 4; } - cpu_abort(env, "Bad mode %x\n", mode); + cpu_abort(CPU(cpu), "Bad mode %x\n", mode); return -1; } @@ -99,7 +101,7 @@ void uc32_cpu_do_interrupt(CPUState *cs) addr = 0x18; break; default: - cpu_abort(env, "Unhandled exception 0x%x\n", cs->exception_index); + cpu_abort(cs, "Unhandled exception 0x%x\n", cs->exception_index); return; } /* High vectors. */ @@ -121,7 +123,8 @@ static int get_phys_addr_ucv2(CPUUniCore32State *env, uint32_t address, int access_type, int is_user, uint32_t *phys_ptr, int *prot, target_ulong *page_size) { - CPUState *cs = CPU(uc32_env_get_cpu(env)); + UniCore32CPU *cpu = uc32_env_get_cpu(env); + CPUState *cs = CPU(cpu); int code; uint32_t table; uint32_t desc; @@ -168,11 +171,11 @@ static int get_phys_addr_ucv2(CPUUniCore32State *env, uint32_t address, *page_size = TARGET_PAGE_SIZE; break; default: - cpu_abort(env, "wrong page type!"); + cpu_abort(CPU(cpu), "wrong page type!"); } break; default: - cpu_abort(env, "wrong page type!"); + cpu_abort(CPU(cpu), "wrong page type!"); } *phys_ptr = phys_addr; @@ -268,6 +271,6 @@ hwaddr uc32_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) { UniCore32CPU *cpu = UNICORE32_CPU(cs); - cpu_abort(&cpu->env, "%s not supported yet\n", __func__); + cpu_abort(CPU(cpu), "%s not supported yet\n", __func__); return addr; } diff --git a/target-unicore32/translate.c b/target-unicore32/translate.c index 5032bbe2a0..c2402cf942 100644 --- a/target-unicore32/translate.c +++ b/target-unicore32/translate.c @@ -176,7 +176,7 @@ static void store_reg(DisasContext *s, int reg, TCGv var) #define UCOP_SET_L UCOP_SET(24) #define UCOP_SET_S UCOP_SET(24) -#define ILLEGAL cpu_abort(env, \ +#define ILLEGAL cpu_abort(CPU(cpu), \ "Illegal UniCore32 instruction %x at line %d!", \ insn, __LINE__) @@ -184,6 +184,7 @@ static void store_reg(DisasContext *s, int reg, TCGv var) static void disas_cp0_insn(CPUUniCore32State *env, DisasContext *s, uint32_t insn) { + UniCore32CPU *cpu = uc32_env_get_cpu(env); TCGv tmp, tmp2, tmp3; if ((insn & 0xfe000000) == 0xe0000000) { tmp2 = new_tmp(); @@ -209,6 +210,7 @@ static void disas_cp0_insn(CPUUniCore32State *env, DisasContext *s, static void disas_ocd_insn(CPUUniCore32State *env, DisasContext *s, uint32_t insn) { + UniCore32CPU *cpu = uc32_env_get_cpu(env); TCGv tmp; if ((insn & 0xff003fff) == 0xe1000400) { @@ -689,6 +691,7 @@ static inline long ucf64_reg_offset(int reg) /* UniCore-F64 single load/store I_offset */ static void do_ucf64_ldst_i(CPUUniCore32State *env, DisasContext *s, uint32_t insn) { + UniCore32CPU *cpu = uc32_env_get_cpu(env); int offset; TCGv tmp; TCGv addr; @@ -735,6 +738,7 @@ static void do_ucf64_ldst_i(CPUUniCore32State *env, DisasContext *s, uint32_t in /* UniCore-F64 load/store multiple words */ static void do_ucf64_ldst_m(CPUUniCore32State *env, DisasContext *s, uint32_t insn) { + UniCore32CPU *cpu = uc32_env_get_cpu(env); unsigned int i; int j, n, freg; TCGv tmp; @@ -820,6 +824,7 @@ static void do_ucf64_ldst_m(CPUUniCore32State *env, DisasContext *s, uint32_t in /* UniCore-F64 mrc/mcr */ static void do_ucf64_trans(CPUUniCore32State *env, DisasContext *s, uint32_t insn) { + UniCore32CPU *cpu = uc32_env_get_cpu(env); TCGv tmp; if ((insn & 0xfe0003ff) == 0xe2000000) { @@ -884,6 +889,8 @@ static void do_ucf64_trans(CPUUniCore32State *env, DisasContext *s, uint32_t ins /* UniCore-F64 convert instructions */ static void do_ucf64_fcvt(CPUUniCore32State *env, DisasContext *s, uint32_t insn) { + UniCore32CPU *cpu = uc32_env_get_cpu(env); + if (UCOP_UCF64_FMT == 3) { ILLEGAL; } @@ -950,6 +957,8 @@ static void do_ucf64_fcvt(CPUUniCore32State *env, DisasContext *s, uint32_t insn /* UniCore-F64 compare instructions */ static void do_ucf64_fcmp(CPUUniCore32State *env, DisasContext *s, uint32_t insn) { + UniCore32CPU *cpu = uc32_env_get_cpu(env); + if (UCOP_SET(25)) { ILLEGAL; } @@ -1028,6 +1037,8 @@ static void do_ucf64_fcmp(CPUUniCore32State *env, DisasContext *s, uint32_t insn /* UniCore-F64 data processing */ static void do_ucf64_datap(CPUUniCore32State *env, DisasContext *s, uint32_t insn) { + UniCore32CPU *cpu = uc32_env_get_cpu(env); + if (UCOP_UCF64_FMT == 3) { ILLEGAL; } @@ -1061,6 +1072,8 @@ static void do_ucf64_datap(CPUUniCore32State *env, DisasContext *s, uint32_t ins /* Disassemble an F64 instruction */ static void disas_ucf64_insn(CPUUniCore32State *env, DisasContext *s, uint32_t insn) { + UniCore32CPU *cpu = uc32_env_get_cpu(env); + if (!UCOP_SET(29)) { if (UCOP_SET(26)) { do_ucf64_ldst_m(env, s, insn); @@ -1167,6 +1180,8 @@ static void gen_exception_return(DisasContext *s, TCGv pc) static void disas_coproc_insn(CPUUniCore32State *env, DisasContext *s, uint32_t insn) { + UniCore32CPU *cpu = uc32_env_get_cpu(env); + switch (UCOP_CPNUM) { #ifndef CONFIG_USER_ONLY case 0: @@ -1181,13 +1196,14 @@ static void disas_coproc_insn(CPUUniCore32State *env, DisasContext *s, break; default: /* Unknown coprocessor. */ - cpu_abort(env, "Unknown coprocessor!"); + cpu_abort(CPU(cpu), "Unknown coprocessor!"); } } /* data processing instructions */ static void do_datap(CPUUniCore32State *env, DisasContext *s, uint32_t insn) { + UniCore32CPU *cpu = uc32_env_get_cpu(env); TCGv tmp; TCGv tmp2; int logic_cc; @@ -1421,6 +1437,7 @@ static void do_mult(CPUUniCore32State *env, DisasContext *s, uint32_t insn) /* miscellaneous instructions */ static void do_misc(CPUUniCore32State *env, DisasContext *s, uint32_t insn) { + UniCore32CPU *cpu = uc32_env_get_cpu(env); unsigned int val; TCGv tmp; @@ -1546,6 +1563,7 @@ static void do_ldst_ir(CPUUniCore32State *env, DisasContext *s, uint32_t insn) /* SWP instruction */ static void do_swap(CPUUniCore32State *env, DisasContext *s, uint32_t insn) { + UniCore32CPU *cpu = uc32_env_get_cpu(env); TCGv addr; TCGv tmp; TCGv tmp2; @@ -1573,6 +1591,7 @@ static void do_swap(CPUUniCore32State *env, DisasContext *s, uint32_t insn) /* load/store hw/sb */ static void do_ldst_hwsb(CPUUniCore32State *env, DisasContext *s, uint32_t insn) { + UniCore32CPU *cpu = uc32_env_get_cpu(env); TCGv addr; TCGv tmp; @@ -1625,6 +1644,7 @@ static void do_ldst_hwsb(CPUUniCore32State *env, DisasContext *s, uint32_t insn) /* load/store multiple words */ static void do_ldst_m(CPUUniCore32State *env, DisasContext *s, uint32_t insn) { + UniCore32CPU *cpu = uc32_env_get_cpu(env); unsigned int val, i, mmu_idx; int j, n, reg, user, loaded_base; TCGv tmp; @@ -1766,6 +1786,7 @@ static void do_ldst_m(CPUUniCore32State *env, DisasContext *s, uint32_t insn) /* branch (and link) */ static void do_branch(CPUUniCore32State *env, DisasContext *s, uint32_t insn) { + UniCore32CPU *cpu = uc32_env_get_cpu(env); unsigned int val; int32_t offset; TCGv tmp; @@ -1795,6 +1816,7 @@ static void do_branch(CPUUniCore32State *env, DisasContext *s, uint32_t insn) static void disas_uc32_insn(CPUUniCore32State *env, DisasContext *s) { + UniCore32CPU *cpu = uc32_env_get_cpu(env); unsigned int insn; if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP | CPU_LOG_TB_OP_OPT))) { @@ -1978,7 +2000,7 @@ static inline void gen_intermediate_code_internal(UniCore32CPU *cpu, if (dc->condjmp) { /* FIXME: This can theoretically happen with self-modifying code. */ - cpu_abort(env, "IO on conditional branch instruction"); + cpu_abort(cs, "IO on conditional branch instruction"); } gen_io_end(); } diff --git a/target-unicore32/ucf64_helper.c b/target-unicore32/ucf64_helper.c index a516edd319..34fa2a5b40 100644 --- a/target-unicore32/ucf64_helper.c +++ b/target-unicore32/ucf64_helper.c @@ -76,6 +76,7 @@ static inline int ucf64_exceptbits_to_host(int target_bits) void HELPER(ucf64_set_fpscr)(CPUUniCore32State *env, uint32_t val) { + UniCore32CPU *cpu = uc32_env_get_cpu(env); int i; uint32_t changed; @@ -99,7 +100,7 @@ void HELPER(ucf64_set_fpscr)(CPUUniCore32State *env, uint32_t val) i = float_round_down; break; default: /* 100 and 101 not implement */ - cpu_abort(env, "Unsupported UniCore-F64 round mode"); + cpu_abort(CPU(cpu), "Unsupported UniCore-F64 round mode"); } set_float_rounding_mode(i, &env->ucf64.fp_status); } diff --git a/translate-all.c b/translate-all.c index e35fcbe86a..f243c10094 100644 --- a/translate-all.c +++ b/translate-all.c @@ -688,7 +688,7 @@ static void page_flush_tb(void) /* XXX: tb_flush is currently not thread safe */ void tb_flush(CPUArchState *env1) { - CPUState *cpu; + CPUState *cpu = ENV_GET_CPU(env1); #if defined(DEBUG_FLUSH) printf("qemu: flush code_size=%ld nb_tbs=%d avg_tb_size=%ld\n", @@ -699,7 +699,7 @@ void tb_flush(CPUArchState *env1) #endif if ((unsigned long)(tcg_ctx.code_gen_ptr - tcg_ctx.code_gen_buffer) > tcg_ctx.code_gen_buffer_size) { - cpu_abort(env1, "Internal error: code buffer overflow\n"); + cpu_abort(cpu, "Internal error: code buffer overflow\n"); } tcg_ctx.tb_ctx.nb_tbs = 0; @@ -1374,12 +1374,11 @@ void tb_invalidate_phys_addr(AddressSpace *as, hwaddr addr) void tb_check_watchpoint(CPUState *cpu) { - CPUArchState *env = cpu->env_ptr; TranslationBlock *tb; tb = tb_find_pc(cpu->mem_io_pc); if (!tb) { - cpu_abort(env, "check_watchpoint: could not find TB for pc=%p", + cpu_abort(cpu, "check_watchpoint: could not find TB for pc=%p", (void *)cpu->mem_io_pc); } cpu_restore_state_from_tb(cpu, tb, cpu->mem_io_pc); @@ -1390,7 +1389,6 @@ void tb_check_watchpoint(CPUState *cpu) /* mask must never be zero, except for A20 change call */ static void tcg_handle_interrupt(CPUState *cpu, int mask) { - CPUArchState *env = cpu->env_ptr; int old_mask; old_mask = cpu->interrupt_request; @@ -1409,7 +1407,7 @@ static void tcg_handle_interrupt(CPUState *cpu, int mask) cpu->icount_decr.u16.high = 0xffff; if (!cpu_can_do_io(cpu) && (mask & ~old_mask) != 0) { - cpu_abort(env, "Raised interrupt while not in I/O function"); + cpu_abort(cpu, "Raised interrupt while not in I/O function"); } } else { cpu->tcg_exit_req = 1; @@ -1422,7 +1420,9 @@ CPUInterruptHandler cpu_interrupt_handler = tcg_handle_interrupt; must be at the end of the TB */ void cpu_io_recompile(CPUState *cpu, uintptr_t retaddr) { +#if defined(TARGET_MIPS) || defined(TARGET_SH4) CPUArchState *env = cpu->env_ptr; +#endif TranslationBlock *tb; uint32_t n, cflags; target_ulong pc, cs_base; @@ -1430,7 +1430,7 @@ void cpu_io_recompile(CPUState *cpu, uintptr_t retaddr) tb = tb_find_pc(retaddr); if (!tb) { - cpu_abort(env, "cpu_io_recompile: could not find TB for pc=%p", + cpu_abort(cpu, "cpu_io_recompile: could not find TB for pc=%p", (void *)retaddr); } n = cpu->icount_decr.u16.low + tb->icount; @@ -1460,7 +1460,7 @@ void cpu_io_recompile(CPUState *cpu, uintptr_t retaddr) #endif /* This should never happen. */ if (n > CF_COUNT_MASK) { - cpu_abort(env, "TB too big during recompile"); + cpu_abort(cpu, "TB too big during recompile"); } cflags = n | CF_LAST_IO; -- cgit 1.4.1 From 31b030d4abc5bea89c2b33b39d3b302836f6b6ee Mon Sep 17 00:00:00 2001 From: Andreas Färber Date: Wed, 4 Sep 2013 01:29:02 +0200 Subject: cputlb: Change tlb_flush_page() argument to CPUState MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Andreas Färber --- cputlb.c | 4 +-- exec.c | 7 ++---- include/exec/exec-all.h | 4 +-- target-alpha/sys_helper.c | 2 +- target-arm/helper.c | 14 ++++++++--- target-cris/mmu.c | 3 ++- target-cris/op_helper.c | 12 ++++++--- target-i386/misc_helper.c | 4 ++- target-i386/svm_helper.c | 3 ++- target-microblaze/mmu.c | 3 ++- target-mips/helper.c | 8 ++++-- target-openrisc/sys_helper.c | 4 +-- target-ppc/mmu_helper.c | 58 +++++++++++++++++++++++++------------------- target-s390x/mem_helper.c | 6 ++--- target-s390x/misc_helper.c | 6 +++-- target-sh4/helper.c | 19 +++++++++------ target-sparc/ldst_helper.c | 9 ++++--- target-xtensa/op_helper.c | 10 +++++--- 18 files changed, 106 insertions(+), 70 deletions(-) (limited to 'include/exec') diff --git a/cputlb.c b/cputlb.c index 22810536f5..9a12248004 100644 --- a/cputlb.c +++ b/cputlb.c @@ -77,9 +77,9 @@ static inline void tlb_flush_entry(CPUTLBEntry *tlb_entry, target_ulong addr) } } -void tlb_flush_page(CPUArchState *env, target_ulong addr) +void tlb_flush_page(CPUState *cpu, target_ulong addr) { - CPUState *cpu = ENV_GET_CPU(env); + CPUArchState *env = cpu->env_ptr; int i; int mmu_idx; diff --git a/exec.c b/exec.c index 5224b31e9f..c03193266a 100644 --- a/exec.c +++ b/exec.c @@ -543,7 +543,6 @@ int cpu_watchpoint_insert(CPUState *cpu, vaddr addr, vaddr len, int cpu_watchpoint_insert(CPUState *cpu, vaddr addr, vaddr len, int flags, CPUWatchpoint **watchpoint) { - CPUArchState *env = cpu->env_ptr; vaddr len_mask = ~(len - 1); CPUWatchpoint *wp; @@ -567,7 +566,7 @@ int cpu_watchpoint_insert(CPUState *cpu, vaddr addr, vaddr len, QTAILQ_INSERT_TAIL(&cpu->watchpoints, wp, entry); } - tlb_flush_page(env, addr); + tlb_flush_page(cpu, addr); if (watchpoint) *watchpoint = wp; @@ -594,11 +593,9 @@ int cpu_watchpoint_remove(CPUState *cpu, vaddr addr, vaddr len, /* Remove a specific watchpoint by reference. */ void cpu_watchpoint_remove_by_ref(CPUState *cpu, CPUWatchpoint *watchpoint) { - CPUArchState *env = cpu->env_ptr; - QTAILQ_REMOVE(&cpu->watchpoints, watchpoint, entry); - tlb_flush_page(env, watchpoint->vaddr); + tlb_flush_page(cpu, watchpoint->vaddr); g_free(watchpoint); } diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index 01b8eba9bc..33633a2fae 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -98,14 +98,14 @@ void tb_invalidate_phys_range(tb_page_addr_t start, tb_page_addr_t end, #if !defined(CONFIG_USER_ONLY) void tcg_cpu_address_space_init(CPUState *cpu, AddressSpace *as); /* cputlb.c */ -void tlb_flush_page(CPUArchState *env, target_ulong addr); +void tlb_flush_page(CPUState *cpu, target_ulong addr); void tlb_flush(CPUArchState *env, int flush_global); void tlb_set_page(CPUArchState *env, target_ulong vaddr, hwaddr paddr, int prot, int mmu_idx, target_ulong size); void tb_invalidate_phys_addr(AddressSpace *as, hwaddr addr); #else -static inline void tlb_flush_page(CPUArchState *env, target_ulong addr) +static inline void tlb_flush_page(CPUState *cpu, target_ulong addr) { } diff --git a/target-alpha/sys_helper.c b/target-alpha/sys_helper.c index 035810c27c..5f7d7dde0e 100644 --- a/target-alpha/sys_helper.c +++ b/target-alpha/sys_helper.c @@ -69,7 +69,7 @@ void helper_tbia(CPUAlphaState *env) void helper_tbis(CPUAlphaState *env, uint64_t p) { - tlb_flush_page(env, p); + tlb_flush_page(CPU(alpha_env_get_cpu(env)), p); } void helper_tb_flush(CPUAlphaState *env) diff --git a/target-arm/helper.c b/target-arm/helper.c index 0a9c6fc5e2..1fda6be295 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -342,7 +342,9 @@ static void tlbimva_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { /* Invalidate single TLB entry by MVA and ASID (TLBIMVA) */ - tlb_flush_page(env, value & TARGET_PAGE_MASK); + ARMCPU *cpu = arm_env_get_cpu(env); + + tlb_flush_page(CPU(cpu), value & TARGET_PAGE_MASK); } static void tlbiasid_write(CPUARMState *env, const ARMCPRegInfo *ri, @@ -356,7 +358,9 @@ static void tlbimvaa_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { /* Invalidate single entry by MVA, all ASIDs (TLBIMVAA) */ - tlb_flush_page(env, value & TARGET_PAGE_MASK); + ARMCPU *cpu = arm_env_get_cpu(env); + + tlb_flush_page(CPU(cpu), value & TARGET_PAGE_MASK); } static const ARMCPRegInfo cp_reginfo[] = { @@ -1686,16 +1690,18 @@ static void tlbi_aa64_va_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { /* Invalidate by VA (AArch64 version) */ + ARMCPU *cpu = arm_env_get_cpu(env); uint64_t pageaddr = value << 12; - tlb_flush_page(env, pageaddr); + tlb_flush_page(CPU(cpu), pageaddr); } static void tlbi_aa64_vaa_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { /* Invalidate by VA, all ASIDs (AArch64 version) */ + ARMCPU *cpu = arm_env_get_cpu(env); uint64_t pageaddr = value << 12; - tlb_flush_page(env, pageaddr); + tlb_flush_page(CPU(cpu), pageaddr); } static void tlbi_aa64_asid_write(CPUARMState *env, const ARMCPRegInfo *ri, diff --git a/target-cris/mmu.c b/target-cris/mmu.c index 512e28b481..1c95a415f2 100644 --- a/target-cris/mmu.c +++ b/target-cris/mmu.c @@ -290,6 +290,7 @@ static int cris_mmu_translate_page(struct cris_mmu_result *res, void cris_mmu_flush_pid(CPUCRISState *env, uint32_t pid) { + CRISCPU *cpu = cris_env_get_cpu(env); target_ulong vaddr; unsigned int idx; uint32_t lo, hi; @@ -315,7 +316,7 @@ void cris_mmu_flush_pid(CPUCRISState *env, uint32_t pid) vaddr = tlb_vpn << TARGET_PAGE_BITS; D_LOG("flush pid=%x vaddr=%x\n", pid, vaddr); - tlb_flush_page(env, vaddr); + tlb_flush_page(CPU(cpu), vaddr); } } } diff --git a/target-cris/op_helper.c b/target-cris/op_helper.c index d28bd61778..bd9a583f9a 100644 --- a/target-cris/op_helper.c +++ b/target-cris/op_helper.c @@ -98,8 +98,11 @@ void helper_tlb_flush_pid(CPUCRISState *env, uint32_t pid) void helper_spc_write(CPUCRISState *env, uint32_t new_spc) { #if !defined(CONFIG_USER_ONLY) - tlb_flush_page(env, env->pregs[PR_SPC]); - tlb_flush_page(env, new_spc); + CRISCPU *cpu = cris_env_get_cpu(env); + CPUState *cs = CPU(cpu); + + tlb_flush_page(cs, env->pregs[PR_SPC]); + tlb_flush_page(cs, new_spc); #endif } @@ -114,6 +117,9 @@ void helper_dump(uint32_t a0, uint32_t a1, uint32_t a2) void helper_movl_sreg_reg(CPUCRISState *env, uint32_t sreg, uint32_t reg) { +#if !defined(CONFIG_USER_ONLY) + CRISCPU *cpu = cris_env_get_cpu(env); +#endif uint32_t srs; srs = env->pregs[PR_SRS]; srs &= 3; @@ -155,7 +161,7 @@ void helper_movl_sreg_reg(CPUCRISState *env, uint32_t sreg, uint32_t reg) D_LOG("tlb flush vaddr=%x v=%d pc=%x\n", vaddr, tlb_v, env->pc); if (tlb_v) { - tlb_flush_page(env, vaddr); + tlb_flush_page(CPU(cpu), vaddr); } } } diff --git a/target-i386/misc_helper.c b/target-i386/misc_helper.c index 8c6b9bfce2..1e2da1ed68 100644 --- a/target-i386/misc_helper.c +++ b/target-i386/misc_helper.c @@ -221,8 +221,10 @@ void helper_lmsw(CPUX86State *env, target_ulong t0) void helper_invlpg(CPUX86State *env, target_ulong addr) { + X86CPU *cpu = x86_env_get_cpu(env); + cpu_svm_check_intercept_param(env, SVM_EXIT_INVLPG, 0); - tlb_flush_page(env, addr); + tlb_flush_page(CPU(cpu), addr); } void helper_rdtsc(CPUX86State *env) diff --git a/target-i386/svm_helper.c b/target-i386/svm_helper.c index de2c2eebe0..6e7c3b7224 100644 --- a/target-i386/svm_helper.c +++ b/target-i386/svm_helper.c @@ -469,6 +469,7 @@ void helper_skinit(CPUX86State *env) void helper_invlpga(CPUX86State *env, int aflag) { + X86CPU *cpu = x86_env_get_cpu(env); target_ulong addr; cpu_svm_check_intercept_param(env, SVM_EXIT_INVLPGA, 0); @@ -481,7 +482,7 @@ void helper_invlpga(CPUX86State *env, int aflag) /* XXX: could use the ASID to see if it is needed to do the flush */ - tlb_flush_page(env, addr); + tlb_flush_page(CPU(cpu), addr); } void helper_svm_check_intercept_param(CPUX86State *env, uint32_t type, diff --git a/target-microblaze/mmu.c b/target-microblaze/mmu.c index 73bf8059be..7ee1be046c 100644 --- a/target-microblaze/mmu.c +++ b/target-microblaze/mmu.c @@ -34,6 +34,7 @@ static unsigned int tlb_decode_size(unsigned int f) static void mmu_flush_idx(CPUMBState *env, unsigned int idx) { + CPUState *cs = CPU(mb_env_get_cpu(env)); struct microblaze_mmu *mmu = &env->mmu; unsigned int tlb_size; uint32_t tlb_tag, end, t; @@ -47,7 +48,7 @@ static void mmu_flush_idx(CPUMBState *env, unsigned int idx) end = tlb_tag + tlb_size; while (tlb_tag < end) { - tlb_flush_page(env, tlb_tag); + tlb_flush_page(cs, tlb_tag); tlb_tag += TARGET_PAGE_SIZE; } } diff --git a/target-mips/helper.c b/target-mips/helper.c index 698c3d1adb..f3879eddda 100644 --- a/target-mips/helper.c +++ b/target-mips/helper.c @@ -653,6 +653,8 @@ void mips_cpu_do_interrupt(CPUState *cs) #if !defined(CONFIG_USER_ONLY) void r4k_invalidate_tlb (CPUMIPSState *env, int idx, int use_extra) { + MIPSCPU *cpu = mips_env_get_cpu(env); + CPUState *cs; r4k_tlb_t *tlb; target_ulong addr; target_ulong end; @@ -678,6 +680,7 @@ void r4k_invalidate_tlb (CPUMIPSState *env, int idx, int use_extra) /* 1k pages are not supported. */ mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1); if (tlb->V0) { + cs = CPU(cpu); addr = tlb->VPN & ~mask; #if defined(TARGET_MIPS64) if (addr >= (0xFFFFFFFF80000000ULL & env->SEGMask)) { @@ -686,11 +689,12 @@ void r4k_invalidate_tlb (CPUMIPSState *env, int idx, int use_extra) #endif end = addr | (mask >> 1); while (addr < end) { - tlb_flush_page (env, addr); + tlb_flush_page(cs, addr); addr += TARGET_PAGE_SIZE; } } if (tlb->V1) { + cs = CPU(cpu); addr = (tlb->VPN & ~mask) | ((mask >> 1) + 1); #if defined(TARGET_MIPS64) if (addr >= (0xFFFFFFFF80000000ULL & env->SEGMask)) { @@ -699,7 +703,7 @@ void r4k_invalidate_tlb (CPUMIPSState *env, int idx, int use_extra) #endif end = addr | mask; while (addr - 1 < end) { - tlb_flush_page (env, addr); + tlb_flush_page(cs, addr); addr += TARGET_PAGE_SIZE; } } diff --git a/target-openrisc/sys_helper.c b/target-openrisc/sys_helper.c index be06c4565b..f1ff3adca9 100644 --- a/target-openrisc/sys_helper.c +++ b/target-openrisc/sys_helper.c @@ -84,7 +84,7 @@ void HELPER(mtspr)(CPUOpenRISCState *env, case TO_SPR(1, 512) ... TO_SPR(1, 512+DTLB_SIZE-1): /* DTLBW0MR 0-127 */ idx = spr - TO_SPR(1, 512); if (!(rb & 1)) { - tlb_flush_page(env, env->tlb->dtlb[0][idx].mr & TARGET_PAGE_MASK); + tlb_flush_page(cs, env->tlb->dtlb[0][idx].mr & TARGET_PAGE_MASK); } env->tlb->dtlb[0][idx].mr = rb; break; @@ -103,7 +103,7 @@ void HELPER(mtspr)(CPUOpenRISCState *env, case TO_SPR(2, 512) ... TO_SPR(2, 512+ITLB_SIZE-1): /* ITLBW0MR 0-127 */ idx = spr - TO_SPR(2, 512); if (!(rb & 1)) { - tlb_flush_page(env, env->tlb->itlb[0][idx].mr & TARGET_PAGE_MASK); + tlb_flush_page(cs, env->tlb->itlb[0][idx].mr & TARGET_PAGE_MASK); } env->tlb->itlb[0][idx].mr = rb; break; diff --git a/target-ppc/mmu_helper.c b/target-ppc/mmu_helper.c index 845a7252b3..8dc262cfd1 100644 --- a/target-ppc/mmu_helper.c +++ b/target-ppc/mmu_helper.c @@ -252,6 +252,7 @@ static inline void ppc6xx_tlb_invalidate_virt2(CPUPPCState *env, int is_code, int match_epn) { #if !defined(FLUSH_ALL_TLBS) + CPUState *cs = CPU(ppc_env_get_cpu(env)); ppc6xx_tlb_t *tlb; int way, nr; @@ -263,7 +264,7 @@ static inline void ppc6xx_tlb_invalidate_virt2(CPUPPCState *env, LOG_SWTLB("TLB invalidate %d/%d " TARGET_FMT_lx "\n", nr, env->nb_tlb, eaddr); pte_invalidate(&tlb->pte0); - tlb_flush_page(env, tlb->EPN); + tlb_flush_page(cs, tlb->EPN); } } #else @@ -657,6 +658,7 @@ static inline void ppc4xx_tlb_invalidate_virt(CPUPPCState *env, target_ulong eaddr, uint32_t pid) { #if !defined(FLUSH_ALL_TLBS) + CPUState *cs = CPU(ppc_env_get_cpu(env)); ppcemb_tlb_t *tlb; hwaddr raddr; target_ulong page, end; @@ -667,7 +669,7 @@ static inline void ppc4xx_tlb_invalidate_virt(CPUPPCState *env, if (ppcemb_tlb_check(env, tlb, &raddr, eaddr, pid, 0, i) == 0) { end = tlb->EPN + tlb->size; for (page = tlb->EPN; page < end; page += TARGET_PAGE_SIZE) { - tlb_flush_page(env, page); + tlb_flush_page(cs, page); } tlb->prot &= ~PAGE_VALID; break; @@ -1727,6 +1729,7 @@ static int cpu_ppc_handle_mmu_fault(CPUPPCState *env, target_ulong address, static inline void do_invalidate_BAT(CPUPPCState *env, target_ulong BATu, target_ulong mask) { + CPUState *cs = CPU(ppc_env_get_cpu(env)); target_ulong base, end, page; base = BATu & ~0x0001FFFF; @@ -1734,7 +1737,7 @@ static inline void do_invalidate_BAT(CPUPPCState *env, target_ulong BATu, LOG_BATS("Flush BAT from " TARGET_FMT_lx " to " TARGET_FMT_lx " (" TARGET_FMT_lx ")\n", base, end, mask); for (page = base; page != end; page += TARGET_PAGE_SIZE) { - tlb_flush_page(env, page); + tlb_flush_page(cs, page); } LOG_BATS("Flush done\n"); } @@ -1941,6 +1944,7 @@ void ppc_tlb_invalidate_one(CPUPPCState *env, target_ulong addr) { #if !defined(FLUSH_ALL_TLBS) PowerPCCPU *cpu = ppc_env_get_cpu(env); + CPUState *cs; addr &= TARGET_PAGE_MASK; switch (env->mmu_model) { @@ -1974,25 +1978,26 @@ void ppc_tlb_invalidate_one(CPUPPCState *env, target_ulong addr) case POWERPC_MMU_601: /* tlbie invalidate TLBs for all segments */ addr &= ~((target_ulong)-1ULL << 28); + cs = CPU(cpu); /* XXX: this case should be optimized, * giving a mask to tlb_flush_page */ - tlb_flush_page(env, addr | (0x0 << 28)); - tlb_flush_page(env, addr | (0x1 << 28)); - tlb_flush_page(env, addr | (0x2 << 28)); - tlb_flush_page(env, addr | (0x3 << 28)); - tlb_flush_page(env, addr | (0x4 << 28)); - tlb_flush_page(env, addr | (0x5 << 28)); - tlb_flush_page(env, addr | (0x6 << 28)); - tlb_flush_page(env, addr | (0x7 << 28)); - tlb_flush_page(env, addr | (0x8 << 28)); - tlb_flush_page(env, addr | (0x9 << 28)); - tlb_flush_page(env, addr | (0xA << 28)); - tlb_flush_page(env, addr | (0xB << 28)); - tlb_flush_page(env, addr | (0xC << 28)); - tlb_flush_page(env, addr | (0xD << 28)); - tlb_flush_page(env, addr | (0xE << 28)); - tlb_flush_page(env, addr | (0xF << 28)); + tlb_flush_page(cs, addr | (0x0 << 28)); + tlb_flush_page(cs, addr | (0x1 << 28)); + tlb_flush_page(cs, addr | (0x2 << 28)); + tlb_flush_page(cs, addr | (0x3 << 28)); + tlb_flush_page(cs, addr | (0x4 << 28)); + tlb_flush_page(cs, addr | (0x5 << 28)); + tlb_flush_page(cs, addr | (0x6 << 28)); + tlb_flush_page(cs, addr | (0x7 << 28)); + tlb_flush_page(cs, addr | (0x8 << 28)); + tlb_flush_page(cs, addr | (0x9 << 28)); + tlb_flush_page(cs, addr | (0xA << 28)); + tlb_flush_page(cs, addr | (0xB << 28)); + tlb_flush_page(cs, addr | (0xC << 28)); + tlb_flush_page(cs, addr | (0xD << 28)); + tlb_flush_page(cs, addr | (0xE << 28)); + tlb_flush_page(cs, addr | (0xF << 28)); break; #if defined(TARGET_PPC64) case POWERPC_MMU_64B: @@ -2325,6 +2330,7 @@ void helper_4xx_tlbwe_hi(CPUPPCState *env, target_ulong entry, target_ulong val) { PowerPCCPU *cpu = ppc_env_get_cpu(env); + CPUState *cs = CPU(cpu); ppcemb_tlb_t *tlb; target_ulong page, end; @@ -2338,7 +2344,7 @@ void helper_4xx_tlbwe_hi(CPUPPCState *env, target_ulong entry, LOG_SWTLB("%s: invalidate old TLB %d start " TARGET_FMT_lx " end " TARGET_FMT_lx "\n", __func__, (int)entry, tlb->EPN, end); for (page = tlb->EPN; page < end; page += TARGET_PAGE_SIZE) { - tlb_flush_page(env, page); + tlb_flush_page(cs, page); } } tlb->size = booke_tlb_to_page_size((val >> PPC4XX_TLBHI_SIZE_SHIFT) @@ -2348,7 +2354,7 @@ void helper_4xx_tlbwe_hi(CPUPPCState *env, target_ulong entry, * of the ppc or ppc64 one */ if ((val & PPC4XX_TLBHI_V) && tlb->size < TARGET_PAGE_SIZE) { - cpu_abort(CPU(cpu), "TLB size " TARGET_FMT_lu " < %u " + cpu_abort(cs, "TLB size " TARGET_FMT_lu " < %u " "are not supported (%d)\n", tlb->size, TARGET_PAGE_SIZE, (int)((val >> 7) & 0x7)); } @@ -2357,7 +2363,7 @@ void helper_4xx_tlbwe_hi(CPUPPCState *env, target_ulong entry, tlb->prot |= PAGE_VALID; if (val & PPC4XX_TLBHI_E) { /* XXX: TO BE FIXED */ - cpu_abort(CPU(cpu), + cpu_abort(cs, "Little-endian TLB entries are not supported by now\n"); } } else { @@ -2377,7 +2383,7 @@ void helper_4xx_tlbwe_hi(CPUPPCState *env, target_ulong entry, LOG_SWTLB("%s: invalidate TLB %d start " TARGET_FMT_lx " end " TARGET_FMT_lx "\n", __func__, (int)entry, tlb->EPN, end); for (page = tlb->EPN; page < end; page += TARGET_PAGE_SIZE) { - tlb_flush_page(env, page); + tlb_flush_page(cs, page); } } } @@ -2666,7 +2672,7 @@ void helper_booke206_tlbwe(CPUPPCState *env) } if (booke206_tlb_to_page_size(env, tlb) == TARGET_PAGE_SIZE) { - tlb_flush_page(env, tlb->mas2 & MAS2_EPN_MASK); + tlb_flush_page(CPU(cpu), tlb->mas2 & MAS2_EPN_MASK); } else { tlb_flush(env, 1); } @@ -2775,6 +2781,8 @@ static inline void booke206_invalidate_ea_tlb(CPUPPCState *env, int tlbn, void helper_booke206_tlbivax(CPUPPCState *env, target_ulong address) { + PowerPCCPU *cpu = ppc_env_get_cpu(env); + if (address & 0x4) { /* flush all entries */ if (address & 0x8) { @@ -2794,7 +2802,7 @@ void helper_booke206_tlbivax(CPUPPCState *env, target_ulong address) } else { /* flush TLB0 entries */ booke206_invalidate_ea_tlb(env, 0, address); - tlb_flush_page(env, address & MAS2_EPN_MASK); + tlb_flush_page(CPU(cpu), address & MAS2_EPN_MASK); } } diff --git a/target-s390x/mem_helper.c b/target-s390x/mem_helper.c index 21632848ac..607501890c 100644 --- a/target-s390x/mem_helper.c +++ b/target-s390x/mem_helper.c @@ -1027,13 +1027,13 @@ void HELPER(ipte)(CPUS390XState *env, uint64_t pte_addr, uint64_t vaddr) /* XXX we exploit the fact that Linux passes the exact virtual address here - it's not obliged to! */ - tlb_flush_page(env, page); + tlb_flush_page(cs, page); /* XXX 31-bit hack */ if (page & 0x80000000) { - tlb_flush_page(env, page & ~0x80000000); + tlb_flush_page(cs, page & ~0x80000000); } else { - tlb_flush_page(env, page | 0x80000000); + tlb_flush_page(cs, page | 0x80000000); } } diff --git a/target-s390x/misc_helper.c b/target-s390x/misc_helper.c index 942b5f7487..294b3ed4fb 100644 --- a/target-s390x/misc_helper.c +++ b/target-s390x/misc_helper.c @@ -237,11 +237,13 @@ uint64_t HELPER(diag)(CPUS390XState *env, uint32_t num, uint64_t mem, /* Set Prefix */ void HELPER(spx)(CPUS390XState *env, uint64_t a1) { + CPUState *cs = CPU(s390_env_get_cpu(env)); uint32_t prefix = a1 & 0x7fffe000; + env->psa = prefix; qemu_log("prefix: %#x\n", prefix); - tlb_flush_page(env, 0); - tlb_flush_page(env, TARGET_PAGE_SIZE); + tlb_flush_page(cs, 0); + tlb_flush_page(cs, TARGET_PAGE_SIZE); } static inline uint64_t clock_value(CPUS390XState *env) diff --git a/target-sh4/helper.c b/target-sh4/helper.c index ba0f269f52..9eb258517f 100644 --- a/target-sh4/helper.c +++ b/target-sh4/helper.c @@ -304,7 +304,7 @@ static int copy_utlb_entry_itlb(CPUSH4State *env, int utlb) itlb = itlb_replacement(env); ientry = &env->itlb[itlb]; if (ientry->v) { - tlb_flush_page(env, ientry->vpn << 10); + tlb_flush_page(CPU(sh_env_get_cpu(env)), ientry->vpn << 10); } *ientry = env->utlb[utlb]; update_itlb_use(env, itlb); @@ -535,7 +535,7 @@ void cpu_load_tlb(CPUSH4State * env) if (entry->v) { /* Overwriting valid entry in utlb. */ target_ulong address = entry->vpn << 10; - tlb_flush_page(env, address); + tlb_flush_page(CPU(cpu), address); } /* Take values into cpu status from registers. */ @@ -611,7 +611,7 @@ void cpu_sh4_write_mmaped_itlb_addr(CPUSH4State *s, hwaddr addr, if (entry->v) { /* Overwriting valid entry in itlb. */ target_ulong address = entry->vpn << 10; - tlb_flush_page(s, address); + tlb_flush_page(CPU(sh_env_get_cpu(s)), address); } entry->asid = asid; entry->vpn = vpn; @@ -653,7 +653,7 @@ void cpu_sh4_write_mmaped_itlb_data(CPUSH4State *s, hwaddr addr, if (entry->v) { /* Overwriting valid entry in utlb. */ target_ulong address = entry->vpn << 10; - tlb_flush_page(s, address); + tlb_flush_page(CPU(sh_env_get_cpu(s)), address); } entry->ppn = (mem_value & 0x1ffffc00) >> 10; entry->v = (mem_value & 0x00000100) >> 8; @@ -737,16 +737,19 @@ void cpu_sh4_write_mmaped_utlb_addr(CPUSH4State *s, hwaddr addr, } } - if (needs_tlb_flush) - tlb_flush_page(s, vpn << 10); + if (needs_tlb_flush) { + tlb_flush_page(CPU(sh_env_get_cpu(s)), vpn << 10); + } } else { int index = (addr & 0x00003f00) >> 8; tlb_t * entry = &s->utlb[index]; if (entry->v) { + CPUState *cs = CPU(sh_env_get_cpu(s)); + /* Overwriting valid entry in utlb. */ target_ulong address = entry->vpn << 10; - tlb_flush_page(s, address); + tlb_flush_page(cs, address); } entry->asid = asid; entry->vpn = vpn; @@ -797,7 +800,7 @@ void cpu_sh4_write_mmaped_utlb_data(CPUSH4State *s, hwaddr addr, if (entry->v) { /* Overwriting valid entry in utlb. */ target_ulong address = entry->vpn << 10; - tlb_flush_page(s, address); + tlb_flush_page(CPU(sh_env_get_cpu(s)), address); } entry->ppn = (mem_value & 0x1ffffc00) >> 10; entry->v = (mem_value & 0x00000100) >> 8; diff --git a/target-sparc/ldst_helper.c b/target-sparc/ldst_helper.c index 1f6df49e88..36fe2de441 100644 --- a/target-sparc/ldst_helper.c +++ b/target-sparc/ldst_helper.c @@ -141,6 +141,7 @@ static void replace_tlb_entry(SparcTLBEntry *tlb, /* flush page range if translation is valid */ if (TTE_IS_VALID(tlb->tte)) { + CPUState *cs = CPU(sparc_env_get_cpu(env1)); mask = 0xffffffffffffe000ULL; mask <<= 3 * ((tlb->tte >> 61) & 3); @@ -149,7 +150,7 @@ static void replace_tlb_entry(SparcTLBEntry *tlb, va = tlb->tag & mask; for (offset = 0; offset < size; offset += TARGET_PAGE_SIZE) { - tlb_flush_page(env1, va + offset); + tlb_flush_page(cs, va + offset); } } @@ -716,7 +717,9 @@ uint64_t helper_ld_asi(CPUSPARCState *env, target_ulong addr, int asi, int size, void helper_st_asi(CPUSPARCState *env, target_ulong addr, uint64_t val, int asi, int size) { - CPUState *cs = CPU(sparc_env_get_cpu(env)); + SPARCCPU *cpu = sparc_env_get_cpu(env); + CPUState *cs = CPU(cpu); + helper_check_align(env, addr, size - 1); switch (asi) { case 2: /* SuperSparc MXCC registers and Leon3 cache control */ @@ -862,7 +865,7 @@ void helper_st_asi(CPUSPARCState *env, target_ulong addr, uint64_t val, int asi, DPRINTF_MMU("mmu flush level %d\n", mmulev); switch (mmulev) { case 0: /* flush page */ - tlb_flush_page(env, addr & 0xfffff000); + tlb_flush_page(CPU(cpu), addr & 0xfffff000); break; case 1: /* flush segment (256k) */ case 2: /* flush region (16M) */ diff --git a/target-xtensa/op_helper.c b/target-xtensa/op_helper.c index 07b00a4335..cae9cf4ad6 100644 --- a/target-xtensa/op_helper.c +++ b/target-xtensa/op_helper.c @@ -687,7 +687,7 @@ void HELPER(itlb)(CPUXtensaState *env, uint32_t v, uint32_t dtlb) uint32_t wi; xtensa_tlb_entry *entry = get_tlb_entry(env, v, dtlb, &wi); if (entry->variable && entry->asid) { - tlb_flush_page(env, entry->vaddr); + tlb_flush_page(CPU(xtensa_env_get_cpu(env)), entry->vaddr); entry->asid = 0; } } @@ -732,21 +732,23 @@ void xtensa_tlb_set_entry_mmu(const CPUXtensaState *env, void xtensa_tlb_set_entry(CPUXtensaState *env, bool dtlb, unsigned wi, unsigned ei, uint32_t vpn, uint32_t pte) { + XtensaCPU *cpu = xtensa_env_get_cpu(env); + CPUState *cs = CPU(cpu); xtensa_tlb_entry *entry = xtensa_tlb_get_entry(env, dtlb, wi, ei); if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) { if (entry->variable) { if (entry->asid) { - tlb_flush_page(env, entry->vaddr); + tlb_flush_page(cs, entry->vaddr); } xtensa_tlb_set_entry_mmu(env, entry, dtlb, wi, ei, vpn, pte); - tlb_flush_page(env, entry->vaddr); + tlb_flush_page(cs, entry->vaddr); } else { qemu_log("%s %d, %d, %d trying to set immutable entry\n", __func__, dtlb, wi, ei); } } else { - tlb_flush_page(env, entry->vaddr); + tlb_flush_page(cs, entry->vaddr); if (xtensa_option_enabled(env->config, XTENSA_OPTION_REGION_TRANSLATION)) { entry->paddr = pte & REGION_PAGE_MASK; -- cgit 1.4.1 From 00c8cb0a36f51a6866a83c08962d12a0eb21864b Mon Sep 17 00:00:00 2001 From: Andreas Färber Date: Wed, 4 Sep 2013 02:19:44 +0200 Subject: cputlb: Change tlb_flush() argument to CPUState MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Andreas Färber --- cputlb.c | 6 +++--- exec.c | 4 +--- hw/sh4/sh7750.c | 2 +- include/exec/exec-all.h | 4 ++-- target-alpha/cpu.c | 2 +- target-alpha/sys_helper.c | 2 +- target-arm/cpu.c | 2 +- target-arm/helper.c | 39 ++++++++++++++++++++++++--------- target-cris/cpu.c | 2 +- target-i386/cpu.c | 2 +- target-i386/helper.c | 17 ++++++++++----- target-i386/machine.c | 2 +- target-i386/svm_helper.c | 2 +- target-lm32/cpu.c | 2 +- target-m68k/cpu.c | 2 +- target-microblaze/cpu.c | 2 +- target-microblaze/mmu.c | 3 ++- target-mips/cpu.c | 2 +- target-mips/machine.c | 3 ++- target-mips/op_helper.c | 4 +++- target-moxie/cpu.c | 2 +- target-openrisc/cpu.c | 2 +- target-openrisc/interrupt.c | 2 +- target-openrisc/interrupt_helper.c | 2 +- target-openrisc/sys_helper.c | 2 +- target-ppc/excp_helper.c | 4 ++-- target-ppc/helper_regs.h | 2 +- target-ppc/misc_helper.c | 4 +++- target-ppc/mmu-hash64.c | 6 ++++-- target-ppc/mmu_helper.c | 44 ++++++++++++++++++++++++-------------- target-ppc/translate_init.c | 2 +- target-s390x/cpu.c | 4 ++-- target-s390x/mem_helper.c | 13 +++++++---- target-sh4/cpu.c | 2 +- target-sh4/helper.c | 2 +- target-sparc/cpu.c | 2 +- target-sparc/ldst_helper.c | 18 +++++++++------- target-sparc/machine.c | 3 ++- target-unicore32/cpu.c | 2 +- target-unicore32/helper.c | 4 +++- target-xtensa/op_helper.c | 4 +++- 41 files changed, 143 insertions(+), 87 deletions(-) (limited to 'include/exec') diff --git a/cputlb.c b/cputlb.c index 9a12248004..b280e81c6f 100644 --- a/cputlb.c +++ b/cputlb.c @@ -46,9 +46,9 @@ int tlb_flush_count; * entries from the TLB at any time, so flushing more entries than * required is only an efficiency issue, not a correctness issue. */ -void tlb_flush(CPUArchState *env, int flush_global) +void tlb_flush(CPUState *cpu, int flush_global) { - CPUState *cpu = ENV_GET_CPU(env); + CPUArchState *env = cpu->env_ptr; #if defined(DEBUG_TLB) printf("tlb_flush:\n"); @@ -93,7 +93,7 @@ void tlb_flush_page(CPUState *cpu, target_ulong addr) TARGET_FMT_lx "/" TARGET_FMT_lx ")\n", env->tlb_flush_addr, env->tlb_flush_mask); #endif - tlb_flush(env, 1); + tlb_flush(cpu, 1); return; } /* must reset current TB so that interrupts cannot modify the diff --git a/exec.c b/exec.c index c03193266a..6a0bc94a0a 100644 --- a/exec.c +++ b/exec.c @@ -1834,14 +1834,12 @@ static void tcg_commit(MemoryListener *listener) reset the modified entries */ /* XXX: slow ! */ CPU_FOREACH(cpu) { - CPUArchState *env = cpu->env_ptr; - /* FIXME: Disentangle the cpu.h circular files deps so we can directly get the right CPU from listener. */ if (cpu->tcg_as_listener != listener) { continue; } - tlb_flush(env, 1); + tlb_flush(cpu, 1); } } diff --git a/hw/sh4/sh7750.c b/hw/sh4/sh7750.c index 1439ba44e5..4a39357529 100644 --- a/hw/sh4/sh7750.c +++ b/hw/sh4/sh7750.c @@ -416,7 +416,7 @@ static void sh7750_mem_writel(void *opaque, hwaddr addr, case SH7750_PTEH_A7: /* If asid changes, clear all registered tlb entries. */ if ((s->cpu->env.pteh & 0xff) != (mem_value & 0xff)) { - tlb_flush(&s->cpu->env, 1); + tlb_flush(CPU(s->cpu), 1); } s->cpu->env.pteh = mem_value; return; diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index 33633a2fae..4cc11bb652 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -99,7 +99,7 @@ void tb_invalidate_phys_range(tb_page_addr_t start, tb_page_addr_t end, void tcg_cpu_address_space_init(CPUState *cpu, AddressSpace *as); /* cputlb.c */ void tlb_flush_page(CPUState *cpu, target_ulong addr); -void tlb_flush(CPUArchState *env, int flush_global); +void tlb_flush(CPUState *cpu, int flush_global); void tlb_set_page(CPUArchState *env, target_ulong vaddr, hwaddr paddr, int prot, int mmu_idx, target_ulong size); @@ -109,7 +109,7 @@ static inline void tlb_flush_page(CPUState *cpu, target_ulong addr) { } -static inline void tlb_flush(CPUArchState *env, int flush_global) +static inline void tlb_flush(CPUState *cpu, int flush_global) { } #endif diff --git a/target-alpha/cpu.c b/target-alpha/cpu.c index 4d8263f37d..7ec46b90fc 100644 --- a/target-alpha/cpu.c +++ b/target-alpha/cpu.c @@ -258,7 +258,7 @@ static void alpha_cpu_initfn(Object *obj) cs->env_ptr = env; cpu_exec_init(env); - tlb_flush(env, 1); + tlb_flush(cs, 1); alpha_translate_init(); diff --git a/target-alpha/sys_helper.c b/target-alpha/sys_helper.c index 5f7d7dde0e..187ccf7297 100644 --- a/target-alpha/sys_helper.c +++ b/target-alpha/sys_helper.c @@ -64,7 +64,7 @@ void helper_call_pal(CPUAlphaState *env, uint64_t pc, uint64_t entry_ofs) void helper_tbia(CPUAlphaState *env) { - tlb_flush(env, 1); + tlb_flush(CPU(alpha_env_get_cpu(env)), 1); } void helper_tbis(CPUAlphaState *env, uint64_t p) diff --git a/target-arm/cpu.c b/target-arm/cpu.c index ecd0b7ecde..c32d8c4855 100644 --- a/target-arm/cpu.c +++ b/target-arm/cpu.c @@ -149,7 +149,7 @@ static void arm_cpu_reset(CPUState *s) &env->vfp.fp_status); set_float_detect_tininess(float_tininess_before_rounding, &env->vfp.standard_fp_status); - tlb_flush(env, 1); + tlb_flush(s, 1); /* Reset is a state change for some CPUARMState fields which we * bake assumptions about into translated code, so we need to * tb_flush(). diff --git a/target-arm/helper.c b/target-arm/helper.c index 1fda6be295..a9db2796c5 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -303,17 +303,21 @@ void init_cpreg_list(ARMCPU *cpu) static void dacr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { + ARMCPU *cpu = arm_env_get_cpu(env); + env->cp15.c3 = value; - tlb_flush(env, 1); /* Flush TLB as domain not tracked in TLB */ + tlb_flush(CPU(cpu), 1); /* Flush TLB as domain not tracked in TLB */ } static void fcse_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { + ARMCPU *cpu = arm_env_get_cpu(env); + if (env->cp15.c13_fcse != value) { /* Unlike real hardware the qemu TLB uses virtual addresses, * not modified virtual addresses, so this causes a TLB flush. */ - tlb_flush(env, 1); + tlb_flush(CPU(cpu), 1); env->cp15.c13_fcse = value; } } @@ -321,12 +325,14 @@ static void fcse_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) static void contextidr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { + ARMCPU *cpu = arm_env_get_cpu(env); + if (env->cp15.c13_context != value && !arm_feature(env, ARM_FEATURE_MPU)) { /* For VMSA (when not using the LPAE long descriptor page table * format) this register includes the ASID, so do a TLB flush. * For PMSA it is purely a process ID and no action is needed. */ - tlb_flush(env, 1); + tlb_flush(CPU(cpu), 1); } env->cp15.c13_context = value; } @@ -335,7 +341,9 @@ static void tlbiall_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { /* Invalidate all (TLBIALL) */ - tlb_flush(env, 1); + ARMCPU *cpu = arm_env_get_cpu(env); + + tlb_flush(CPU(cpu), 1); } static void tlbimva_write(CPUARMState *env, const ARMCPRegInfo *ri, @@ -351,7 +359,9 @@ static void tlbiasid_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { /* Invalidate by ASID (TLBIASID) */ - tlb_flush(env, value == 0); + ARMCPU *cpu = arm_env_get_cpu(env); + + tlb_flush(CPU(cpu), value == 0); } static void tlbimvaa_write(CPUARMState *env, const ARMCPRegInfo *ri, @@ -1352,11 +1362,13 @@ static void vmsa_ttbcr_raw_write(CPUARMState *env, const ARMCPRegInfo *ri, static void vmsa_ttbcr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { + ARMCPU *cpu = arm_env_get_cpu(env); + if (arm_feature(env, ARM_FEATURE_LPAE)) { /* With LPAE the TTBCR could result in a change of ASID * via the TTBCR.A1 bit, so do a TLB flush. */ - tlb_flush(env, 1); + tlb_flush(CPU(cpu), 1); } vmsa_ttbcr_raw_write(env, ri, value); } @@ -1371,8 +1383,10 @@ static void vmsa_ttbcr_reset(CPUARMState *env, const ARMCPRegInfo *ri) static void vmsa_tcr_el1_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { + ARMCPU *cpu = arm_env_get_cpu(env); + /* For AArch64 the A1 bit could result in a change of ASID, so TLB flush. */ - tlb_flush(env, 1); + tlb_flush(CPU(cpu), 1); env->cp15.c2_control = value; } @@ -1383,7 +1397,9 @@ static void vmsa_ttbr_write(CPUARMState *env, const ARMCPRegInfo *ri, * must flush the TLB. */ if (cpreg_field_is_64bit(ri)) { - tlb_flush(env, 1); + ARMCPU *cpu = arm_env_get_cpu(env); + + tlb_flush(CPU(cpu), 1); } raw_write(env, ri, value); } @@ -1708,8 +1724,9 @@ static void tlbi_aa64_asid_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { /* Invalidate by ASID (AArch64 version) */ + ARMCPU *cpu = arm_env_get_cpu(env); int asid = extract64(value, 48, 16); - tlb_flush(env, asid == 0); + tlb_flush(CPU(cpu), asid == 0); } static const ARMCPRegInfo v8_cp_reginfo[] = { @@ -1835,10 +1852,12 @@ static const ARMCPRegInfo v8_cp_reginfo[] = { static void sctlr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { + ARMCPU *cpu = arm_env_get_cpu(env); + env->cp15.c1_sys = value; /* ??? Lots of these bits are not implemented. */ /* This may enable/disable the MMU, so do a TLB flush. */ - tlb_flush(env, 1); + tlb_flush(CPU(cpu), 1); } static CPAccessResult ctr_el0_access(CPUARMState *env, const ARMCPRegInfo *ri) diff --git a/target-cris/cpu.c b/target-cris/cpu.c index 95b6a8889b..20d8809699 100644 --- a/target-cris/cpu.c +++ b/target-cris/cpu.c @@ -51,7 +51,7 @@ static void cris_cpu_reset(CPUState *s) vr = env->pregs[PR_VR]; memset(env, 0, offsetof(CPUCRISState, load_info)); env->pregs[PR_VR] = vr; - tlb_flush(env, 1); + tlb_flush(s, 1); #if defined(CONFIG_USER_ONLY) /* start in user mode with interrupts enabled. */ diff --git a/target-i386/cpu.c b/target-i386/cpu.c index 659ec9a11b..e7e62c5897 100644 --- a/target-i386/cpu.c +++ b/target-i386/cpu.c @@ -2412,7 +2412,7 @@ static void x86_cpu_reset(CPUState *s) memset(env, 0, offsetof(CPUX86State, pat)); - tlb_flush(env, 1); + tlb_flush(s, 1); env->old_exception = -1; diff --git a/target-i386/helper.c b/target-i386/helper.c index 8c70d62af5..54899a0542 100644 --- a/target-i386/helper.c +++ b/target-i386/helper.c @@ -385,22 +385,25 @@ void x86_cpu_set_a20(X86CPU *cpu, int a20_state) a20_state = (a20_state != 0); if (a20_state != ((env->a20_mask >> 20) & 1)) { + CPUState *cs = CPU(cpu); + #if defined(DEBUG_MMU) printf("A20 update: a20=%d\n", a20_state); #endif /* if the cpu is currently executing code, we must unlink it and all the potentially executing TB */ - cpu_interrupt(CPU(cpu), CPU_INTERRUPT_EXITTB); + cpu_interrupt(cs, CPU_INTERRUPT_EXITTB); /* when a20 is changed, all the MMU mappings are invalid, so we must flush everything */ - tlb_flush(env, 1); + tlb_flush(cs, 1); env->a20_mask = ~(1 << 20) | (a20_state << 20); } } void cpu_x86_update_cr0(CPUX86State *env, uint32_t new_cr0) { + X86CPU *cpu = x86_env_get_cpu(env); int pe_state; #if defined(DEBUG_MMU) @@ -408,7 +411,7 @@ void cpu_x86_update_cr0(CPUX86State *env, uint32_t new_cr0) #endif if ((new_cr0 & (CR0_PG_MASK | CR0_WP_MASK | CR0_PE_MASK)) != (env->cr[0] & (CR0_PG_MASK | CR0_WP_MASK | CR0_PE_MASK))) { - tlb_flush(env, 1); + tlb_flush(CPU(cpu), 1); } #ifdef TARGET_X86_64 @@ -444,24 +447,28 @@ void cpu_x86_update_cr0(CPUX86State *env, uint32_t new_cr0) the PDPT */ void cpu_x86_update_cr3(CPUX86State *env, target_ulong new_cr3) { + X86CPU *cpu = x86_env_get_cpu(env); + env->cr[3] = new_cr3; if (env->cr[0] & CR0_PG_MASK) { #if defined(DEBUG_MMU) printf("CR3 update: CR3=" TARGET_FMT_lx "\n", new_cr3); #endif - tlb_flush(env, 0); + tlb_flush(CPU(cpu), 0); } } void cpu_x86_update_cr4(CPUX86State *env, uint32_t new_cr4) { + X86CPU *cpu = x86_env_get_cpu(env); + #if defined(DEBUG_MMU) printf("CR4 update: CR4=%08x\n", (uint32_t)env->cr[4]); #endif if ((new_cr4 ^ env->cr[4]) & (CR4_PGE_MASK | CR4_PAE_MASK | CR4_PSE_MASK | CR4_SMEP_MASK | CR4_SMAP_MASK)) { - tlb_flush(env, 1); + tlb_flush(CPU(cpu), 1); } /* SSE handling */ if (!(env->features[FEAT_1_EDX] & CPUID_SSE)) { diff --git a/target-i386/machine.c b/target-i386/machine.c index ed159a8c06..24bc373b9c 100644 --- a/target-i386/machine.c +++ b/target-i386/machine.c @@ -325,7 +325,7 @@ static int cpu_post_load(void *opaque, int version_id) for (i = 0; i < DR7_MAX_BP; i++) { hw_breakpoint_insert(env, i); } - tlb_flush(env, 1); + tlb_flush(cs, 1); return 0; } diff --git a/target-i386/svm_helper.c b/target-i386/svm_helper.c index 6e7c3b7224..aa17ecdece 100644 --- a/target-i386/svm_helper.c +++ b/target-i386/svm_helper.c @@ -294,7 +294,7 @@ void helper_vmrun(CPUX86State *env, int aflag, int next_eip_addend) break; case TLB_CONTROL_FLUSH_ALL_ASID: /* FIXME: this is not 100% correct but should work for now */ - tlb_flush(env, 1); + tlb_flush(cs, 1); break; } diff --git a/target-lm32/cpu.c b/target-lm32/cpu.c index d0c66bc0f5..c5c20d74c4 100644 --- a/target-lm32/cpu.c +++ b/target-lm32/cpu.c @@ -128,7 +128,7 @@ static void lm32_cpu_reset(CPUState *s) memset(env, 0, offsetof(CPULM32State, eba)); lm32_cpu_init_cfg_reg(cpu); - tlb_flush(env, 1); + tlb_flush(s, 1); } static void lm32_cpu_realizefn(DeviceState *dev, Error **errp) diff --git a/target-m68k/cpu.c b/target-m68k/cpu.c index a88da20b46..c9cff19efc 100644 --- a/target-m68k/cpu.c +++ b/target-m68k/cpu.c @@ -58,7 +58,7 @@ static void m68k_cpu_reset(CPUState *s) env->cc_op = CC_OP_FLAGS; /* TODO: We should set PC from the interrupt vector. */ env->pc = 0; - tlb_flush(env, 1); + tlb_flush(s, 1); } /* CPU models */ diff --git a/target-microblaze/cpu.c b/target-microblaze/cpu.c index 3177fe6d12..8e0481186a 100644 --- a/target-microblaze/cpu.c +++ b/target-microblaze/cpu.c @@ -65,7 +65,7 @@ static void mb_cpu_reset(CPUState *s) memset(env, 0, sizeof(CPUMBState)); env->res_addr = RES_ADDR_NONE; - tlb_flush(env, 1); + tlb_flush(s, 1); /* Disable stack protector. */ env->shr = ~0; diff --git a/target-microblaze/mmu.c b/target-microblaze/mmu.c index 7ee1be046c..728da133da 100644 --- a/target-microblaze/mmu.c +++ b/target-microblaze/mmu.c @@ -219,6 +219,7 @@ uint32_t mmu_read(CPUMBState *env, uint32_t rn) void mmu_write(CPUMBState *env, uint32_t rn, uint32_t v) { + MicroBlazeCPU *cpu = mb_env_get_cpu(env); unsigned int i; D(qemu_log("%s rn=%d=%x old=%x\n", __func__, rn, v, env->mmu.regs[rn])); @@ -252,7 +253,7 @@ void mmu_write(CPUMBState *env, uint32_t rn, uint32_t v) /* Changes to the zone protection reg flush the QEMU TLB. Fortunately, these are very uncommon. */ if (v != env->mmu.regs[rn]) { - tlb_flush(env, 1); + tlb_flush(CPU(cpu), 1); } env->mmu.regs[rn] = v; break; diff --git a/target-mips/cpu.c b/target-mips/cpu.c index cf4d856d6b..ae37ae26c0 100644 --- a/target-mips/cpu.c +++ b/target-mips/cpu.c @@ -84,7 +84,7 @@ static void mips_cpu_reset(CPUState *s) mcc->parent_reset(s); memset(env, 0, offsetof(CPUMIPSState, mvp)); - tlb_flush(env, 1); + tlb_flush(s, 1); cpu_state_reset(env); } diff --git a/target-mips/machine.c b/target-mips/machine.c index 23504ba9ae..0a07db8540 100644 --- a/target-mips/machine.c +++ b/target-mips/machine.c @@ -191,6 +191,7 @@ static void load_fpu(QEMUFile *f, CPUMIPSFPUContext *fpu) int cpu_load(QEMUFile *f, void *opaque, int version_id) { CPUMIPSState *env = opaque; + MIPSCPU *cpu = mips_env_get_cpu(env); int i; if (version_id != 3) @@ -303,6 +304,6 @@ int cpu_load(QEMUFile *f, void *opaque, int version_id) load_fpu(f, &env->fpus[i]); /* XXX: ensure compatibility for halted bit ? */ - tlb_flush(env, 1); + tlb_flush(CPU(cpu), 1); return 0; } diff --git a/target-mips/op_helper.c b/target-mips/op_helper.c index 1a785c23d9..e56f038d71 100644 --- a/target-mips/op_helper.c +++ b/target-mips/op_helper.c @@ -1787,8 +1787,10 @@ target_ulong helper_yield(CPUMIPSState *env, target_ulong arg) /* TLB management */ static void cpu_mips_tlb_flush (CPUMIPSState *env, int flush_global) { + MIPSCPU *cpu = mips_env_get_cpu(env); + /* Flush qemu's TLB and discard all shadowed entries. */ - tlb_flush (env, flush_global); + tlb_flush(CPU(cpu), flush_global); env->tlb->tlb_in_use = env->tlb->nb_tlb; } diff --git a/target-moxie/cpu.c b/target-moxie/cpu.c index 14d1a24438..47b617f5cd 100644 --- a/target-moxie/cpu.c +++ b/target-moxie/cpu.c @@ -45,7 +45,7 @@ static void moxie_cpu_reset(CPUState *s) memset(env, 0, sizeof(CPUMoxieState)); env->pc = 0x1000; - tlb_flush(env, 1); + tlb_flush(s, 1); } static void moxie_cpu_realizefn(DeviceState *dev, Error **errp) diff --git a/target-openrisc/cpu.c b/target-openrisc/cpu.c index a00369bef5..08e724c126 100644 --- a/target-openrisc/cpu.c +++ b/target-openrisc/cpu.c @@ -47,7 +47,7 @@ static void openrisc_cpu_reset(CPUState *s) memset(&cpu->env, 0, offsetof(CPUOpenRISCState, irq)); #endif - tlb_flush(&cpu->env, 1); + tlb_flush(s, 1); /*tb_flush(&cpu->env); FIXME: Do we need it? */ cpu->env.pc = 0x100; diff --git a/target-openrisc/interrupt.c b/target-openrisc/interrupt.c index e312300853..3de567eee8 100644 --- a/target-openrisc/interrupt.c +++ b/target-openrisc/interrupt.c @@ -43,7 +43,7 @@ void openrisc_cpu_do_interrupt(CPUState *cs) /* For machine-state changed between user-mode and supervisor mode, we need flush TLB when we enter&exit EXCP. */ - tlb_flush(env, 1); + tlb_flush(cs, 1); env->esr = env->sr; env->sr &= ~SR_DME; diff --git a/target-openrisc/interrupt_helper.c b/target-openrisc/interrupt_helper.c index 844648f780..819405701d 100644 --- a/target-openrisc/interrupt_helper.c +++ b/target-openrisc/interrupt_helper.c @@ -51,7 +51,7 @@ void HELPER(rfe)(CPUOpenRISCState *env) } if (need_flush_tlb) { - tlb_flush(&cpu->env, 1); + tlb_flush(cs, 1); } #endif cs->interrupt_request |= CPU_INTERRUPT_EXITTB; diff --git a/target-openrisc/sys_helper.c b/target-openrisc/sys_helper.c index f1ff3adca9..fedcbed4f7 100644 --- a/target-openrisc/sys_helper.c +++ b/target-openrisc/sys_helper.c @@ -45,7 +45,7 @@ void HELPER(mtspr)(CPUOpenRISCState *env, case TO_SPR(0, 17): /* SR */ if ((env->sr & (SR_IME | SR_DME | SR_SM)) ^ (rb & (SR_IME | SR_DME | SR_SM))) { - tlb_flush(env, 1); + tlb_flush(cs, 1); } env->sr = rb; env->sr |= SR_FO; /* FO is const equal to 1 */ diff --git a/target-ppc/excp_helper.c b/target-ppc/excp_helper.c index a2226d1923..19bc6b66ba 100644 --- a/target-ppc/excp_helper.c +++ b/target-ppc/excp_helper.c @@ -616,7 +616,7 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int excp_model, int excp) } /* If we disactivated any translation, flush TLBs */ if (msr & ((1 << MSR_IR) | (1 << MSR_DR))) { - tlb_flush(env, 1); + tlb_flush(cs, 1); } #ifdef TARGET_PPC64 @@ -671,7 +671,7 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int excp_model, int excp) /* XXX: The BookE changes address space when switching modes, we should probably implement that as different MMU indexes, but for the moment we do it the slow way and flush all. */ - tlb_flush(env, 1); + tlb_flush(cs, 1); } } diff --git a/target-ppc/helper_regs.h b/target-ppc/helper_regs.h index c02e8da4e4..f7ec9c2b81 100644 --- a/target-ppc/helper_regs.h +++ b/target-ppc/helper_regs.h @@ -83,7 +83,7 @@ static inline int hreg_store_msr(CPUPPCState *env, target_ulong value, if (((value >> MSR_IR) & 1) != msr_ir || ((value >> MSR_DR) & 1) != msr_dr) { /* Flush all tlb when changing translation mode */ - tlb_flush(env, 1); + tlb_flush(cs, 1); excp = POWERPC_EXCP_NONE; cs->interrupt_request |= CPU_INTERRUPT_EXITTB; } diff --git a/target-ppc/misc_helper.c b/target-ppc/misc_helper.c index dc2ebfc452..2eb2fa6e20 100644 --- a/target-ppc/misc_helper.c +++ b/target-ppc/misc_helper.c @@ -62,10 +62,12 @@ void helper_store_hid0_601(CPUPPCState *env, target_ulong val) void helper_store_403_pbr(CPUPPCState *env, uint32_t num, target_ulong value) { + PowerPCCPU *cpu = ppc_env_get_cpu(env); + if (likely(env->pb[num] != value)) { env->pb[num] = value; /* Should be optimized */ - tlb_flush(env, 1); + tlb_flush(CPU(cpu), 1); } } diff --git a/target-ppc/mmu-hash64.c b/target-ppc/mmu-hash64.c index 98cfb35f69..3f405b3cc9 100644 --- a/target-ppc/mmu-hash64.c +++ b/target-ppc/mmu-hash64.c @@ -99,6 +99,7 @@ void dump_slb(FILE *f, fprintf_function cpu_fprintf, CPUPPCState *env) void helper_slbia(CPUPPCState *env) { + PowerPCCPU *cpu = ppc_env_get_cpu(env); int n, do_invalidate; do_invalidate = 0; @@ -116,12 +117,13 @@ void helper_slbia(CPUPPCState *env) } } if (do_invalidate) { - tlb_flush(env, 1); + tlb_flush(CPU(cpu), 1); } } void helper_slbie(CPUPPCState *env, target_ulong addr) { + PowerPCCPU *cpu = ppc_env_get_cpu(env); ppc_slb_t *slb; slb = slb_lookup(env, addr); @@ -136,7 +138,7 @@ void helper_slbie(CPUPPCState *env, target_ulong addr) * and we still don't have a tlb_flush_mask(env, n, mask) * in QEMU, we just invalidate all TLBs */ - tlb_flush(env, 1); + tlb_flush(CPU(cpu), 1); } } diff --git a/target-ppc/mmu_helper.c b/target-ppc/mmu_helper.c index 8dc262cfd1..653e50230e 100644 --- a/target-ppc/mmu_helper.c +++ b/target-ppc/mmu_helper.c @@ -231,6 +231,7 @@ static inline int ppc6xx_tlb_getnum(CPUPPCState *env, target_ulong eaddr, static inline void ppc6xx_tlb_invalidate_all(CPUPPCState *env) { + PowerPCCPU *cpu = ppc_env_get_cpu(env); ppc6xx_tlb_t *tlb; int nr, max; @@ -244,7 +245,7 @@ static inline void ppc6xx_tlb_invalidate_all(CPUPPCState *env) tlb = &env->tlb.tlb6[nr]; pte_invalidate(&tlb->pte0); } - tlb_flush(env, 1); + tlb_flush(CPU(cpu), 1); } static inline void ppc6xx_tlb_invalidate_virt2(CPUPPCState *env, @@ -644,6 +645,7 @@ static int ppcemb_tlb_search(CPUPPCState *env, target_ulong address, /* Helpers specific to PowerPC 40x implementations */ static inline void ppc4xx_tlb_invalidate_all(CPUPPCState *env) { + PowerPCCPU *cpu = ppc_env_get_cpu(env); ppcemb_tlb_t *tlb; int i; @@ -651,7 +653,7 @@ static inline void ppc4xx_tlb_invalidate_all(CPUPPCState *env) tlb = &env->tlb.tlbe[i]; tlb->prot &= ~PAGE_VALID; } - tlb_flush(env, 1); + tlb_flush(CPU(cpu), 1); } static inline void ppc4xx_tlb_invalidate_virt(CPUPPCState *env, @@ -862,6 +864,7 @@ static int mmubooke_get_physical_address(CPUPPCState *env, mmu_ctx_t *ctx, static void booke206_flush_tlb(CPUPPCState *env, int flags, const int check_iprot) { + PowerPCCPU *cpu = ppc_env_get_cpu(env); int tlb_size; int i, j; ppcmas_tlb_t *tlb = env->tlb.tlbm; @@ -878,7 +881,7 @@ static void booke206_flush_tlb(CPUPPCState *env, int flags, tlb += booke206_tlb_size(env, i); } - tlb_flush(env, 1); + tlb_flush(CPU(cpu), 1); } static hwaddr booke206_tlb_to_page_size(CPUPPCState *env, @@ -1918,7 +1921,7 @@ void ppc_tlb_invalidate_all(CPUPPCState *env) cpu_abort(CPU(cpu), "MPC8xx MMU model is not implemented\n"); break; case POWERPC_MMU_BOOKE: - tlb_flush(env, 1); + tlb_flush(CPU(cpu), 1); break; case POWERPC_MMU_BOOKE206: booke206_flush_tlb(env, -1, 0); @@ -1931,7 +1934,7 @@ void ppc_tlb_invalidate_all(CPUPPCState *env) case POWERPC_MMU_2_06a: case POWERPC_MMU_2_06d: #endif /* defined(TARGET_PPC64) */ - tlb_flush(env, 1); + tlb_flush(CPU(cpu), 1); break; default: /* XXX: TODO */ @@ -2009,7 +2012,7 @@ void ppc_tlb_invalidate_one(CPUPPCState *env, target_ulong addr) * and we still don't have a tlb_flush_mask(env, n, mask) in QEMU, * we just invalidate all TLBs */ - tlb_flush(env, 1); + tlb_flush(CPU(cpu), 1); break; #endif /* defined(TARGET_PPC64) */ default: @@ -2026,6 +2029,8 @@ void ppc_tlb_invalidate_one(CPUPPCState *env, target_ulong addr) /* Special registers manipulation */ void ppc_store_sdr1(CPUPPCState *env, target_ulong value) { + PowerPCCPU *cpu = ppc_env_get_cpu(env); + LOG_MMU("%s: " TARGET_FMT_lx "\n", __func__, value); assert(!env->external_htab); if (env->spr[SPR_SDR1] != value) { @@ -2048,7 +2053,7 @@ void ppc_store_sdr1(CPUPPCState *env, target_ulong value) env->htab_mask = ((value & SDR_32_HTABMASK) << 16) | 0xFFFF; env->htab_base = value & SDR_32_HTABORG; } - tlb_flush(env, 1); + tlb_flush(CPU(cpu), 1); } } @@ -2066,6 +2071,8 @@ target_ulong helper_load_sr(CPUPPCState *env, target_ulong sr_num) void helper_store_sr(CPUPPCState *env, target_ulong srnum, target_ulong value) { + PowerPCCPU *cpu = ppc_env_get_cpu(env); + LOG_MMU("%s: reg=%d " TARGET_FMT_lx " " TARGET_FMT_lx "\n", __func__, (int)srnum, value, env->sr[srnum]); #if defined(TARGET_PPC64) @@ -2098,11 +2105,11 @@ void helper_store_sr(CPUPPCState *env, target_ulong srnum, target_ulong value) page = (16 << 20) * srnum; end = page + (16 << 20); for (; page != end; page += TARGET_PAGE_SIZE) { - tlb_flush_page(env, page); + tlb_flush_page(CPU(cpu), page); } } #else - tlb_flush(env, 1); + tlb_flush(CPU(cpu), 1); #endif } } @@ -2424,6 +2431,7 @@ target_ulong helper_4xx_tlbsx(CPUPPCState *env, target_ulong address) void helper_440_tlbwe(CPUPPCState *env, uint32_t word, target_ulong entry, target_ulong value) { + PowerPCCPU *cpu = ppc_env_get_cpu(env); ppcemb_tlb_t *tlb; target_ulong EPN, RPN, size; int do_flush_tlbs; @@ -2459,13 +2467,13 @@ void helper_440_tlbwe(CPUPPCState *env, uint32_t word, target_ulong entry, } tlb->PID = env->spr[SPR_440_MMUCR] & 0x000000FF; if (do_flush_tlbs) { - tlb_flush(env, 1); + tlb_flush(CPU(cpu), 1); } break; case 1: RPN = value & 0xFFFFFC0F; if ((tlb->prot & PAGE_VALID) && tlb->RPN != RPN) { - tlb_flush(env, 1); + tlb_flush(CPU(cpu), 1); } tlb->RPN = RPN; break; @@ -2577,9 +2585,11 @@ static ppcmas_tlb_t *booke206_cur_tlb(CPUPPCState *env) void helper_booke_setpid(CPUPPCState *env, uint32_t pidn, target_ulong pid) { + PowerPCCPU *cpu = ppc_env_get_cpu(env); + env->spr[pidn] = pid; /* changing PIDs mean we're in a different address space now */ - tlb_flush(env, 1); + tlb_flush(CPU(cpu), 1); } void helper_booke206_tlbwe(CPUPPCState *env) @@ -2674,7 +2684,7 @@ void helper_booke206_tlbwe(CPUPPCState *env) if (booke206_tlb_to_page_size(env, tlb) == TARGET_PAGE_SIZE) { tlb_flush_page(CPU(cpu), tlb->mas2 & MAS2_EPN_MASK); } else { - tlb_flush(env, 1); + tlb_flush(CPU(cpu), 1); } } @@ -2798,7 +2808,7 @@ void helper_booke206_tlbivax(CPUPPCState *env, target_ulong address) if (address & 0x8) { /* flush TLB1 entries */ booke206_invalidate_ea_tlb(env, 1, address); - tlb_flush(env, 1); + tlb_flush(CPU(cpu), 1); } else { /* flush TLB0 entries */ booke206_invalidate_ea_tlb(env, 0, address); @@ -2814,6 +2824,7 @@ void helper_booke206_tlbilx0(CPUPPCState *env, target_ulong address) void helper_booke206_tlbilx1(CPUPPCState *env, target_ulong address) { + PowerPCCPU *cpu = ppc_env_get_cpu(env); int i, j; int tid = (env->spr[SPR_BOOKE_MAS6] & MAS6_SPID); ppcmas_tlb_t *tlb = env->tlb.tlbm; @@ -2830,11 +2841,12 @@ void helper_booke206_tlbilx1(CPUPPCState *env, target_ulong address) } tlb += booke206_tlb_size(env, i); } - tlb_flush(env, 1); + tlb_flush(CPU(cpu), 1); } void helper_booke206_tlbilx3(CPUPPCState *env, target_ulong address) { + PowerPCCPU *cpu = ppc_env_get_cpu(env); int i, j; ppcmas_tlb_t *tlb; int tid = (env->spr[SPR_BOOKE_MAS6] & MAS6_SPID); @@ -2870,7 +2882,7 @@ void helper_booke206_tlbilx3(CPUPPCState *env, target_ulong address) tlb->mas1 &= ~MAS1_VALID; } } - tlb_flush(env, 1); + tlb_flush(CPU(cpu), 1); } void helper_booke206_tlbflush(CPUPPCState *env, uint32_t type) diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c index 267a3765b4..6084f40f28 100644 --- a/target-ppc/translate_init.c +++ b/target-ppc/translate_init.c @@ -8435,7 +8435,7 @@ static void ppc_cpu_reset(CPUState *s) #endif /* TARGET_PPC64 */ /* Flush all TLBs */ - tlb_flush(env, 1); + tlb_flush(s, 1); } static void ppc_cpu_initfn(Object *obj) diff --git a/target-s390x/cpu.c b/target-s390x/cpu.c index ae78ebc5f7..dfd83e8aef 100644 --- a/target-s390x/cpu.c +++ b/target-s390x/cpu.c @@ -98,7 +98,7 @@ static void s390_cpu_reset(CPUState *s) #if !defined(CONFIG_USER_ONLY) s->halted = 1; #endif - tlb_flush(env, 1); + tlb_flush(s, 1); } /* S390CPUClass::initial_reset() */ @@ -153,7 +153,7 @@ static void s390_cpu_full_reset(CPUState *s) #if !defined(CONFIG_USER_ONLY) s->halted = 1; #endif - tlb_flush(env, 1); + tlb_flush(s, 1); } #if !defined(CONFIG_USER_ONLY) diff --git a/target-s390x/mem_helper.c b/target-s390x/mem_helper.c index 607501890c..d8ca3007f8 100644 --- a/target-s390x/mem_helper.c +++ b/target-s390x/mem_helper.c @@ -810,6 +810,7 @@ void HELPER(tr)(CPUS390XState *env, uint32_t len, uint64_t array, #if !defined(CONFIG_USER_ONLY) void HELPER(lctlg)(CPUS390XState *env, uint32_t r1, uint64_t a2, uint32_t r3) { + S390CPU *cpu = s390_env_get_cpu(env); int i; uint64_t src = a2; @@ -824,11 +825,12 @@ void HELPER(lctlg)(CPUS390XState *env, uint32_t r1, uint64_t a2, uint32_t r3) } } - tlb_flush(env, 1); + tlb_flush(CPU(cpu), 1); } void HELPER(lctl)(CPUS390XState *env, uint32_t r1, uint64_t a2, uint32_t r3) { + S390CPU *cpu = s390_env_get_cpu(env); int i; uint64_t src = a2; @@ -842,7 +844,7 @@ void HELPER(lctl)(CPUS390XState *env, uint32_t r1, uint64_t a2, uint32_t r3) } } - tlb_flush(env, 1); + tlb_flush(CPU(cpu), 1); } void HELPER(stctg)(CPUS390XState *env, uint32_t r1, uint64_t a2, uint32_t r3) @@ -935,6 +937,7 @@ uint32_t HELPER(rrbe)(CPUS390XState *env, uint64_t r2) /* compare and swap and purge */ uint32_t HELPER(csp)(CPUS390XState *env, uint32_t r1, uint64_t r2) { + S390CPU *cpu = s390_env_get_cpu(env); uint32_t cc; uint32_t o1 = env->regs[r1]; uint64_t a2 = r2 & ~3ULL; @@ -944,7 +947,7 @@ uint32_t HELPER(csp)(CPUS390XState *env, uint32_t r1, uint64_t r2) cpu_stl_data(env, a2, env->regs[(r1 + 1) & 15]); if (r2 & 0x3) { /* flush TLB / ALB */ - tlb_flush(env, 1); + tlb_flush(CPU(cpu), 1); } cc = 0; } else { @@ -1040,7 +1043,9 @@ void HELPER(ipte)(CPUS390XState *env, uint64_t pte_addr, uint64_t vaddr) /* flush local tlb */ void HELPER(ptlb)(CPUS390XState *env) { - tlb_flush(env, 1); + S390CPU *cpu = s390_env_get_cpu(env); + + tlb_flush(CPU(cpu), 1); } /* store using real address */ diff --git a/target-sh4/cpu.c b/target-sh4/cpu.c index 4e0e2179cc..e7f05212da 100644 --- a/target-sh4/cpu.c +++ b/target-sh4/cpu.c @@ -54,7 +54,7 @@ static void superh_cpu_reset(CPUState *s) scc->parent_reset(s); memset(env, 0, offsetof(CPUSH4State, id)); - tlb_flush(env, 1); + tlb_flush(s, 1); env->pc = 0xA0000000; #if defined(CONFIG_USER_ONLY) diff --git a/target-sh4/helper.c b/target-sh4/helper.c index 9eb258517f..88f69be216 100644 --- a/target-sh4/helper.c +++ b/target-sh4/helper.c @@ -585,7 +585,7 @@ void cpu_load_tlb(CPUSH4State * env) entry->v = 0; } - tlb_flush(s, 1); + tlb_flush(CPU(sh_env_get_cpu(s)), 1); } uint32_t cpu_sh4_read_mmaped_itlb_addr(CPUSH4State *s, diff --git a/target-sparc/cpu.c b/target-sparc/cpu.c index 8465a0b18a..d9f37e9b6a 100644 --- a/target-sparc/cpu.c +++ b/target-sparc/cpu.c @@ -34,7 +34,7 @@ static void sparc_cpu_reset(CPUState *s) scc->parent_reset(s); memset(env, 0, offsetof(CPUSPARCState, version)); - tlb_flush(env, 1); + tlb_flush(s, 1); env->cwp = 0; #ifndef TARGET_SPARC64 env->wim = 1; diff --git a/target-sparc/ldst_helper.c b/target-sparc/ldst_helper.c index 36fe2de441..ec14802573 100644 --- a/target-sparc/ldst_helper.c +++ b/target-sparc/ldst_helper.c @@ -871,7 +871,7 @@ void helper_st_asi(CPUSPARCState *env, target_ulong addr, uint64_t val, int asi, case 2: /* flush region (16M) */ case 3: /* flush context (4G) */ case 4: /* flush entire */ - tlb_flush(env, 1); + tlb_flush(CPU(cpu), 1); break; default: break; @@ -896,7 +896,7 @@ void helper_st_asi(CPUSPARCState *env, target_ulong addr, uint64_t val, int asi, disabled mode are invalid in normal mode */ if ((oldreg & (MMU_E | MMU_NF | env->def->mmu_bm)) != (env->mmuregs[reg] & (MMU_E | MMU_NF | env->def->mmu_bm))) { - tlb_flush(env, 1); + tlb_flush(CPU(cpu), 1); } break; case 1: /* Context Table Pointer Register */ @@ -907,7 +907,7 @@ void helper_st_asi(CPUSPARCState *env, target_ulong addr, uint64_t val, int asi, if (oldreg != env->mmuregs[reg]) { /* we flush when the MMU context changes because QEMU has no MMU context support */ - tlb_flush(env, 1); + tlb_flush(CPU(cpu), 1); } break; case 3: /* Synchronous Fault Status Register with Clear */ @@ -1663,7 +1663,9 @@ uint64_t helper_ld_asi(CPUSPARCState *env, target_ulong addr, int asi, int size, void helper_st_asi(CPUSPARCState *env, target_ulong addr, target_ulong val, int asi, int size) { - CPUState *cs = CPU(sparc_env_get_cpu(env)); + SPARCCPU *cpu = sparc_env_get_cpu(env); + CPUState *cs = CPU(cpu); + #ifdef DEBUG_ASI dump_asi("write", addr, asi, size, val); #endif @@ -1872,7 +1874,7 @@ void helper_st_asi(CPUSPARCState *env, target_ulong addr, target_ulong val, #ifdef DEBUG_MMU dump_mmu(stdout, fprintf, env); #endif - tlb_flush(env, 1); + tlb_flush(CPU(cpu), 1); } return; } @@ -1961,13 +1963,13 @@ void helper_st_asi(CPUSPARCState *env, target_ulong addr, target_ulong val, env->dmmu.mmu_primary_context = val; /* can be optimized to only flush MMU_USER_IDX and MMU_KERNEL_IDX entries */ - tlb_flush(env, 1); + tlb_flush(CPU(cpu), 1); break; case 2: /* Secondary context */ env->dmmu.mmu_secondary_context = val; /* can be optimized to only flush MMU_USER_SECONDARY_IDX and MMU_KERNEL_SECONDARY_IDX entries */ - tlb_flush(env, 1); + tlb_flush(CPU(cpu), 1); break; case 5: /* TSB access */ DPRINTF_MMU("dmmu TSB write: 0x%016" PRIx64 " -> 0x%016" @@ -2397,7 +2399,7 @@ void sparc_cpu_unassigned_access(CPUState *cs, hwaddr addr, /* flush neverland mappings created during no-fault mode, so the sequential MMU faults report proper fault types */ if (env->mmuregs[0] & MMU_NF) { - tlb_flush(env, 1); + tlb_flush(cs, 1); } } #else diff --git a/target-sparc/machine.c b/target-sparc/machine.c index a353dabdd9..3f3de4c65a 100644 --- a/target-sparc/machine.c +++ b/target-sparc/machine.c @@ -112,6 +112,7 @@ void cpu_save(QEMUFile *f, void *opaque) int cpu_load(QEMUFile *f, void *opaque, int version_id) { CPUSPARCState *env = opaque; + SPARCCPU *cpu = sparc_env_get_cpu(env); int i; uint32_t tmp; @@ -212,6 +213,6 @@ int cpu_load(QEMUFile *f, void *opaque, int version_id) qemu_get_be64s(f, &env->ssr); cpu_get_timer(f, env->hstick); #endif - tlb_flush(env, 1); + tlb_flush(CPU(cpu), 1); return 0; } diff --git a/target-unicore32/cpu.c b/target-unicore32/cpu.c index 24dec13985..2d2c429a35 100644 --- a/target-unicore32/cpu.c +++ b/target-unicore32/cpu.c @@ -121,7 +121,7 @@ static void uc32_cpu_initfn(Object *obj) env->regs[31] = 0x03000000; #endif - tlb_flush(env, 1); + tlb_flush(cs, 1); if (tcg_enabled() && !inited) { inited = true; diff --git a/target-unicore32/helper.c b/target-unicore32/helper.c index 195e1bfca9..169c85cb4d 100644 --- a/target-unicore32/helper.c +++ b/target-unicore32/helper.c @@ -50,6 +50,8 @@ uint32_t HELPER(clz)(uint32_t x) void helper_cp0_set(CPUUniCore32State *env, uint32_t val, uint32_t creg, uint32_t cop) { + UniCore32CPU *cpu = uc32_env_get_cpu(env); + /* * movc pp.nn, rn, #imm9 * rn: UCOP_REG_D @@ -118,7 +120,7 @@ void helper_cp0_set(CPUUniCore32State *env, uint32_t val, uint32_t creg, case 6: if ((cop <= 6) && (cop >= 2)) { /* invalid all tlb */ - tlb_flush(env, 1); + tlb_flush(CPU(cpu), 1); return; } break; diff --git a/target-xtensa/op_helper.c b/target-xtensa/op_helper.c index cae9cf4ad6..1eec89155c 100644 --- a/target-xtensa/op_helper.c +++ b/target-xtensa/op_helper.c @@ -487,10 +487,12 @@ void HELPER(check_atomctl)(CPUXtensaState *env, uint32_t pc, uint32_t vaddr) void HELPER(wsr_rasid)(CPUXtensaState *env, uint32_t v) { + XtensaCPU *cpu = xtensa_env_get_cpu(env); + v = (v & 0xffffff00) | 0x1; if (v != env->sregs[RASID]) { env->sregs[RASID] = v; - tlb_flush(env, 1); + tlb_flush(CPU(cpu), 1); } } -- cgit 1.4.1 From 0c591eb0a9d0593d71d7cb61f4184222ac14fdd2 Mon Sep 17 00:00:00 2001 From: Andreas Färber Date: Tue, 3 Sep 2013 13:59:37 +0200 Subject: cputlb: Change tlb_set_page() argument to CPUState MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Andreas Färber --- cputlb.c | 4 ++-- include/exec/exec-all.h | 2 +- target-alpha/helper.c | 2 +- target-arm/helper.c | 2 +- target-cris/helper.c | 2 +- target-i386/helper.c | 2 +- target-lm32/helper.c | 6 +++--- target-m68k/helper.c | 3 +-- target-microblaze/helper.c | 4 ++-- target-mips/helper.c | 2 +- target-moxie/helper.c | 2 +- target-openrisc/mmu.c | 2 +- target-ppc/mmu-hash32.c | 8 ++++---- target-ppc/mmu-hash64.c | 4 ++-- target-ppc/mmu_helper.c | 2 +- target-s390x/helper.c | 2 +- target-sh4/helper.c | 2 +- target-sparc/mmu_helper.c | 6 +++--- target-unicore32/softmmu.c | 2 +- target-xtensa/op_helper.c | 8 ++++---- 20 files changed, 33 insertions(+), 34 deletions(-) (limited to 'include/exec') diff --git a/cputlb.c b/cputlb.c index b280e81c6f..7bd3573025 100644 --- a/cputlb.c +++ b/cputlb.c @@ -221,10 +221,11 @@ static void tlb_add_large_page(CPUArchState *env, target_ulong vaddr, /* Add a new TLB entry. At most one entry for a given virtual address is permitted. Only a single TARGET_PAGE_SIZE region is mapped, the supplied size is only used by tlb_flush_page. */ -void tlb_set_page(CPUArchState *env, target_ulong vaddr, +void tlb_set_page(CPUState *cpu, target_ulong vaddr, hwaddr paddr, int prot, int mmu_idx, target_ulong size) { + CPUArchState *env = cpu->env_ptr; MemoryRegionSection *section; unsigned int index; target_ulong address; @@ -232,7 +233,6 @@ void tlb_set_page(CPUArchState *env, target_ulong vaddr, uintptr_t addend; CPUTLBEntry *te; hwaddr iotlb, xlat, sz; - CPUState *cpu = ENV_GET_CPU(env); assert(size >= TARGET_PAGE_SIZE); if (size != TARGET_PAGE_SIZE) { diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index 4cc11bb652..502b7aa084 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -100,7 +100,7 @@ void tcg_cpu_address_space_init(CPUState *cpu, AddressSpace *as); /* cputlb.c */ void tlb_flush_page(CPUState *cpu, target_ulong addr); void tlb_flush(CPUState *cpu, int flush_global); -void tlb_set_page(CPUArchState *env, target_ulong vaddr, +void tlb_set_page(CPUState *cpu, target_ulong vaddr, hwaddr paddr, int prot, int mmu_idx, target_ulong size); void tb_invalidate_phys_addr(AddressSpace *as, hwaddr addr); diff --git a/target-alpha/helper.c b/target-alpha/helper.c index fdb033564c..cbd03c415b 100644 --- a/target-alpha/helper.c +++ b/target-alpha/helper.c @@ -345,7 +345,7 @@ int alpha_cpu_handle_mmu_fault(CPUState *cs, vaddr addr, int rw, return 1; } - tlb_set_page(env, addr & TARGET_PAGE_MASK, phys & TARGET_PAGE_MASK, + tlb_set_page(cs, addr & TARGET_PAGE_MASK, phys & TARGET_PAGE_MASK, prot, mmu_idx, TARGET_PAGE_SIZE); return 0; } diff --git a/target-arm/helper.c b/target-arm/helper.c index a9db2796c5..aa5f22d14f 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -3676,7 +3676,7 @@ int arm_cpu_handle_mmu_fault(CPUState *cs, vaddr address, /* Map a single [sub]page. */ phys_addr &= ~(hwaddr)0x3ff; address &= ~(uint32_t)0x3ff; - tlb_set_page (env, address, phys_addr, prot, mmu_idx, page_size); + tlb_set_page(cs, address, phys_addr, prot, mmu_idx, page_size); return 0; } diff --git a/target-cris/helper.c b/target-cris/helper.c index ec84b57c0b..4092d279ba 100644 --- a/target-cris/helper.c +++ b/target-cris/helper.c @@ -106,7 +106,7 @@ int cris_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw, */ phy = res.phy & ~0x80000000; prot = res.prot; - tlb_set_page(env, address & TARGET_PAGE_MASK, phy, + tlb_set_page(cs, address & TARGET_PAGE_MASK, phy, prot, mmu_idx, TARGET_PAGE_SIZE); r = 0; } diff --git a/target-i386/helper.c b/target-i386/helper.c index 54899a0542..4f447b8cf9 100644 --- a/target-i386/helper.c +++ b/target-i386/helper.c @@ -877,7 +877,7 @@ int x86_cpu_handle_mmu_fault(CPUState *cs, vaddr addr, paddr = (pte & TARGET_PAGE_MASK) + page_offset; vaddr = virt_addr + page_offset; - tlb_set_page(env, vaddr, paddr, prot, mmu_idx, page_size); + tlb_set_page(cs, vaddr, paddr, prot, mmu_idx, page_size); return 0; do_fault_protect: error_code = PG_ERROR_P_MASK; diff --git a/target-lm32/helper.c b/target-lm32/helper.c index 3adfea9ef0..783aa16a45 100644 --- a/target-lm32/helper.c +++ b/target-lm32/helper.c @@ -30,10 +30,10 @@ int lm32_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw, address &= TARGET_PAGE_MASK; prot = PAGE_BITS; if (env->flags & LM32_FLAG_IGNORE_MSB) { - tlb_set_page(env, address, address & 0x7fffffff, prot, mmu_idx, - TARGET_PAGE_SIZE); + tlb_set_page(cs, address, address & 0x7fffffff, prot, mmu_idx, + TARGET_PAGE_SIZE); } else { - tlb_set_page(env, address, address, prot, mmu_idx, TARGET_PAGE_SIZE); + tlb_set_page(cs, address, address, prot, mmu_idx, TARGET_PAGE_SIZE); } return 0; diff --git a/target-m68k/helper.c b/target-m68k/helper.c index 276fb4bcc9..077b653f24 100644 --- a/target-m68k/helper.c +++ b/target-m68k/helper.c @@ -303,12 +303,11 @@ hwaddr m68k_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) int m68k_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw, int mmu_idx) { - M68kCPU *cpu = M68K_CPU(cs); int prot; address &= TARGET_PAGE_MASK; prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; - tlb_set_page(&cpu->env, address, address, prot, mmu_idx, TARGET_PAGE_SIZE); + tlb_set_page(cs, address, address, prot, mmu_idx, TARGET_PAGE_SIZE); return 0; } diff --git a/target-microblaze/helper.c b/target-microblaze/helper.c index 11d8aa266d..59c9ad5aef 100644 --- a/target-microblaze/helper.c +++ b/target-microblaze/helper.c @@ -77,7 +77,7 @@ int mb_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw, DMMU(qemu_log("MMU map mmu=%d v=%x p=%x prot=%x\n", mmu_idx, vaddr, paddr, lu.prot)); - tlb_set_page(env, vaddr, paddr, lu.prot, mmu_idx, TARGET_PAGE_SIZE); + tlb_set_page(cs, vaddr, paddr, lu.prot, mmu_idx, TARGET_PAGE_SIZE); r = 0; } else { env->sregs[SR_EAR] = address; @@ -108,7 +108,7 @@ int mb_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw, /* MMU disabled or not available. */ address &= TARGET_PAGE_MASK; prot = PAGE_BITS; - tlb_set_page(env, address, address, prot, mmu_idx, TARGET_PAGE_SIZE); + tlb_set_page(cs, address, address, prot, mmu_idx, TARGET_PAGE_SIZE); r = 0; } return r; diff --git a/target-mips/helper.c b/target-mips/helper.c index f3879eddda..b28ae9b033 100644 --- a/target-mips/helper.c +++ b/target-mips/helper.c @@ -300,7 +300,7 @@ int mips_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw, " prot %d\n", __func__, address, ret, physical, prot); if (ret == TLBRET_MATCH) { - tlb_set_page(env, address & TARGET_PAGE_MASK, + tlb_set_page(cs, address & TARGET_PAGE_MASK, physical & TARGET_PAGE_MASK, prot | PAGE_EXEC, mmu_idx, TARGET_PAGE_SIZE); ret = 0; diff --git a/target-moxie/helper.c b/target-moxie/helper.c index 04b36b78b5..3d0c34dd0a 100644 --- a/target-moxie/helper.c +++ b/target-moxie/helper.c @@ -148,7 +148,7 @@ int moxie_cpu_handle_mmu_fault(CPUState *cs, vaddr address, phy = res.phy; r = 0; } - tlb_set_page(env, address, phy, prot, mmu_idx, TARGET_PAGE_SIZE); + tlb_set_page(cs, address, phy, prot, mmu_idx, TARGET_PAGE_SIZE); return r; } diff --git a/target-openrisc/mmu.c b/target-openrisc/mmu.c index 4222219acd..750a93636b 100644 --- a/target-openrisc/mmu.c +++ b/target-openrisc/mmu.c @@ -187,7 +187,7 @@ int openrisc_cpu_handle_mmu_fault(CPUState *cs, address, rw); if (ret == TLBRET_MATCH) { - tlb_set_page(&cpu->env, address & TARGET_PAGE_MASK, + tlb_set_page(cs, address & TARGET_PAGE_MASK, physical & TARGET_PAGE_MASK, prot, mmu_idx, TARGET_PAGE_SIZE); ret = 0; diff --git a/target-ppc/mmu-hash32.c b/target-ppc/mmu-hash32.c index 6a4d6a8025..1cc19162b7 100644 --- a/target-ppc/mmu-hash32.c +++ b/target-ppc/mmu-hash32.c @@ -400,7 +400,7 @@ int ppc_hash32_handle_mmu_fault(PowerPCCPU *cpu, target_ulong eaddr, int rwx, if (((rwx == 2) && (msr_ir == 0)) || ((rwx != 2) && (msr_dr == 0))) { /* Translation is off */ raddr = eaddr; - tlb_set_page(env, eaddr & TARGET_PAGE_MASK, raddr & TARGET_PAGE_MASK, + tlb_set_page(cs, eaddr & TARGET_PAGE_MASK, raddr & TARGET_PAGE_MASK, PAGE_READ | PAGE_WRITE | PAGE_EXEC, mmu_idx, TARGET_PAGE_SIZE); return 0; @@ -427,7 +427,7 @@ int ppc_hash32_handle_mmu_fault(PowerPCCPU *cpu, target_ulong eaddr, int rwx, return 1; } - tlb_set_page(env, eaddr & TARGET_PAGE_MASK, + tlb_set_page(cs, eaddr & TARGET_PAGE_MASK, raddr & TARGET_PAGE_MASK, prot, mmu_idx, TARGET_PAGE_SIZE); return 0; @@ -441,7 +441,7 @@ int ppc_hash32_handle_mmu_fault(PowerPCCPU *cpu, target_ulong eaddr, int rwx, if (sr & SR32_T) { if (ppc_hash32_direct_store(env, sr, eaddr, rwx, &raddr, &prot) == 0) { - tlb_set_page(env, eaddr & TARGET_PAGE_MASK, + tlb_set_page(cs, eaddr & TARGET_PAGE_MASK, raddr & TARGET_PAGE_MASK, prot, mmu_idx, TARGET_PAGE_SIZE); return 0; @@ -522,7 +522,7 @@ int ppc_hash32_handle_mmu_fault(PowerPCCPU *cpu, target_ulong eaddr, int rwx, raddr = ppc_hash32_pte_raddr(sr, pte, eaddr); - tlb_set_page(env, eaddr & TARGET_PAGE_MASK, raddr & TARGET_PAGE_MASK, + tlb_set_page(cs, eaddr & TARGET_PAGE_MASK, raddr & TARGET_PAGE_MASK, prot, mmu_idx, TARGET_PAGE_SIZE); return 0; diff --git a/target-ppc/mmu-hash64.c b/target-ppc/mmu-hash64.c index 3f405b3cc9..1fefe5881e 100644 --- a/target-ppc/mmu-hash64.c +++ b/target-ppc/mmu-hash64.c @@ -476,7 +476,7 @@ int ppc_hash64_handle_mmu_fault(PowerPCCPU *cpu, target_ulong eaddr, /* Translation is off */ /* In real mode the top 4 effective address bits are ignored */ raddr = eaddr & 0x0FFFFFFFFFFFFFFFULL; - tlb_set_page(env, eaddr & TARGET_PAGE_MASK, raddr & TARGET_PAGE_MASK, + tlb_set_page(cs, eaddr & TARGET_PAGE_MASK, raddr & TARGET_PAGE_MASK, PAGE_READ | PAGE_WRITE | PAGE_EXEC, mmu_idx, TARGET_PAGE_SIZE); return 0; @@ -578,7 +578,7 @@ int ppc_hash64_handle_mmu_fault(PowerPCCPU *cpu, target_ulong eaddr, raddr = ppc_hash64_pte_raddr(slb, pte, eaddr); - tlb_set_page(env, eaddr & TARGET_PAGE_MASK, raddr & TARGET_PAGE_MASK, + tlb_set_page(cs, eaddr & TARGET_PAGE_MASK, raddr & TARGET_PAGE_MASK, prot, mmu_idx, TARGET_PAGE_SIZE); return 0; diff --git a/target-ppc/mmu_helper.c b/target-ppc/mmu_helper.c index 653e50230e..1771863dff 100644 --- a/target-ppc/mmu_helper.c +++ b/target-ppc/mmu_helper.c @@ -1514,7 +1514,7 @@ static int cpu_ppc_handle_mmu_fault(CPUPPCState *env, target_ulong address, } ret = get_physical_address(env, &ctx, address, rw, access_type); if (ret == 0) { - tlb_set_page(env, address & TARGET_PAGE_MASK, + tlb_set_page(cs, address & TARGET_PAGE_MASK, ctx.raddr & TARGET_PAGE_MASK, ctx.prot, mmu_idx, TARGET_PAGE_SIZE); ret = 0; diff --git a/target-s390x/helper.c b/target-s390x/helper.c index d4ea7d56d1..aa628b8fe2 100644 --- a/target-s390x/helper.c +++ b/target-s390x/helper.c @@ -417,7 +417,7 @@ int s390_cpu_handle_mmu_fault(CPUState *cs, vaddr orig_vaddr, DPRINTF("%s: set tlb %" PRIx64 " -> %" PRIx64 " (%x)\n", __func__, (uint64_t)vaddr, (uint64_t)raddr, prot); - tlb_set_page(env, orig_vaddr, raddr, prot, + tlb_set_page(cs, orig_vaddr, raddr, prot, mmu_idx, TARGET_PAGE_SIZE); return 0; diff --git a/target-sh4/helper.c b/target-sh4/helper.c index 88f69be216..9ebdd5c9b5 100644 --- a/target-sh4/helper.c +++ b/target-sh4/helper.c @@ -512,7 +512,7 @@ int superh_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw, address &= TARGET_PAGE_MASK; physical &= TARGET_PAGE_MASK; - tlb_set_page(env, address, physical, prot, mmu_idx, TARGET_PAGE_SIZE); + tlb_set_page(cs, address, physical, prot, mmu_idx, TARGET_PAGE_SIZE); return 0; } diff --git a/target-sparc/mmu_helper.c b/target-sparc/mmu_helper.c index 1571c6a026..61afbcf048 100644 --- a/target-sparc/mmu_helper.c +++ b/target-sparc/mmu_helper.c @@ -217,7 +217,7 @@ int sparc_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw, printf("Translate at %" VADDR_PRIx " -> " TARGET_FMT_plx ", vaddr " TARGET_FMT_lx "\n", address, paddr, vaddr); #endif - tlb_set_page(env, vaddr, paddr, prot, mmu_idx, page_size); + tlb_set_page(cs, vaddr, paddr, prot, mmu_idx, page_size); return 0; } @@ -233,7 +233,7 @@ int sparc_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw, neverland. Fake/overridden mappings will be flushed when switching to normal mode. */ prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; - tlb_set_page(env, vaddr, paddr, prot, mmu_idx, TARGET_PAGE_SIZE); + tlb_set_page(cs, vaddr, paddr, prot, mmu_idx, TARGET_PAGE_SIZE); return 0; } else { if (rw & 2) { @@ -729,7 +729,7 @@ int sparc_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw, env->dmmu.mmu_primary_context, env->dmmu.mmu_secondary_context); - tlb_set_page(env, vaddr, paddr, prot, mmu_idx, page_size); + tlb_set_page(cs, vaddr, paddr, prot, mmu_idx, page_size); return 0; } /* XXX */ diff --git a/target-unicore32/softmmu.c b/target-unicore32/softmmu.c index 39ecd98907..9a3786dddb 100644 --- a/target-unicore32/softmmu.c +++ b/target-unicore32/softmmu.c @@ -253,7 +253,7 @@ int uc32_cpu_handle_mmu_fault(CPUState *cs, vaddr address, /* Map a single page. */ phys_addr &= TARGET_PAGE_MASK; address &= TARGET_PAGE_MASK; - tlb_set_page(env, address, phys_addr, prot, mmu_idx, page_size); + tlb_set_page(cs, address, phys_addr, prot, mmu_idx, page_size); return 0; } diff --git a/target-xtensa/op_helper.c b/target-xtensa/op_helper.c index 1eec89155c..b531019488 100644 --- a/target-xtensa/op_helper.c +++ b/target-xtensa/op_helper.c @@ -77,10 +77,10 @@ void tlb_fill(CPUState *cs, vaddr, is_write, mmu_idx, paddr, ret); if (ret == 0) { - tlb_set_page(env, - vaddr & TARGET_PAGE_MASK, - paddr & TARGET_PAGE_MASK, - access, mmu_idx, page_size); + tlb_set_page(cs, + vaddr & TARGET_PAGE_MASK, + paddr & TARGET_PAGE_MASK, + access, mmu_idx, page_size); } else { cpu_restore_state(cs, retaddr); HELPER(exception_cause_vaddr)(env, env->pc, ret, vaddr); -- cgit 1.4.1