From e4a9bc0aae9f98c64a9689f9471234636e6d3ae0 Mon Sep 17 00:00:00 2001 From: Luc Michel Date: Fri, 26 Sep 2025 09:07:46 +0200 Subject: hw/arm/xlnx-versal: ddr: refactor creation MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Refactor the DDR aperture regions creation using the VersalMap structure. Device creation and FDT node creation are split into two functions because the later must happen during ARM virtual bootloader modify_dtb callback. Signed-off-by: Luc Michel Reviewed-by: Francisco Iglesias Reviewed-by: Edgar E. Iglesias Tested-by: Philippe Mathieu-Daudé Message-id: 20250926070806.292065-29-luc.michel@amd.com Signed-off-by: Peter Maydell --- include/hw/arm/xlnx-versal.h | 7 ++----- 1 file changed, 2 insertions(+), 5 deletions(-) (limited to 'include/hw/arm/xlnx-versal.h') diff --git a/include/hw/arm/xlnx-versal.h b/include/hw/arm/xlnx-versal.h index e1d6e54549..39bc414c85 100644 --- a/include/hw/arm/xlnx-versal.h +++ b/include/hw/arm/xlnx-versal.h @@ -43,11 +43,6 @@ struct Versal { GArray *intc; MemoryRegion mr_ps; - struct { - /* 4 ranges to access DDR. */ - MemoryRegion mr_ddr_ranges[4]; - } noc; - struct { uint32_t clk_25mhz; uint32_t clk_125mhz; @@ -73,6 +68,8 @@ static inline void versal_set_fdt(Versal *s, void *fdt) s->cfg.fdt = fdt; } +void versal_fdt_add_memory_nodes(Versal *s, uint64_t ram_size); + DeviceState *versal_get_boot_cpu(Versal *s); void versal_sdhci_plug_card(Versal *s, int sd_idx, BlockBackend *blk); void versal_efuse_attach_drive(Versal *s, BlockBackend *blk); -- cgit 1.4.1