From a714b8aa029c2a6cc0b99a798f4f8b6d4282e711 Mon Sep 17 00:00:00 2001 From: Alistair Francis Date: Mon, 30 Aug 2021 15:34:36 +1000 Subject: hw/intc: sifive_clint: Use RISC-V CPU GPIO lines Instead of using riscv_cpu_update_mip() let's instead use the new RISC-V CPU GPIO lines to set the timer and soft MIP bits. Signed-off-by: Alistair Francis Reviewed-by: Bin Meng Tested-by: Bin Meng Reviewed-by: LIU Zhiwei Message-id: 946e1ef5e268b24084c7ddad84c146de62a56736.1630301632.git.alistair.francis@wdc.com --- include/hw/intc/sifive_clint.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'include/hw/intc/sifive_clint.h') diff --git a/include/hw/intc/sifive_clint.h b/include/hw/intc/sifive_clint.h index a30be0f3d6..921b1561dd 100644 --- a/include/hw/intc/sifive_clint.h +++ b/include/hw/intc/sifive_clint.h @@ -40,6 +40,8 @@ typedef struct SiFiveCLINTState { uint32_t time_base; uint32_t aperture_size; uint32_t timebase_freq; + qemu_irq *timer_irqs; + qemu_irq *soft_irqs; } SiFiveCLINTState; DeviceState *sifive_clint_create(hwaddr addr, hwaddr size, -- cgit 1.4.1