From 59c54c1ceb1d84cb48d27a5b26d6f21cb76ee9e1 Mon Sep 17 00:00:00 2001 From: Bibo Mao Date: Tue, 7 Jan 2025 11:08:13 +0800 Subject: hw/intc/loongarch_ipi: Implement realize interface Add realize interface for loongarch ipi device. Signed-off-by: Bibo Mao Reviewed-by: Bibo Mao --- include/hw/intc/loongarch_ipi.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include/hw/intc') diff --git a/include/hw/intc/loongarch_ipi.h b/include/hw/intc/loongarch_ipi.h index 276b3040a3..923bf21ecb 100644 --- a/include/hw/intc/loongarch_ipi.h +++ b/include/hw/intc/loongarch_ipi.h @@ -20,6 +20,7 @@ struct LoongarchIPIState { struct LoongarchIPIClass { LoongsonIPICommonClass parent_class; + DeviceRealize parent_realize; }; #endif -- cgit 1.4.1 From 14dc02b56a3d4434401ad92415cbec3e30ff3fa5 Mon Sep 17 00:00:00 2001 From: Bibo Mao Date: Tue, 7 Jan 2025 11:08:16 +0800 Subject: hw/intc/loongarch_ipi: Get cpu number from possible_cpu_arch_ids Supported CPU number can be acquired from function possible_cpu_arch_ids(), cpu-num property is not necessary and can be removed. Signed-off-by: Bibo Mao Reviewed-by: Bibo Mao --- hw/intc/loongarch_ipi.c | 13 ++++++++----- include/hw/intc/loongson_ipi_common.h | 2 ++ 2 files changed, 10 insertions(+), 5 deletions(-) (limited to 'include/hw/intc') diff --git a/hw/intc/loongarch_ipi.c b/hw/intc/loongarch_ipi.c index 9c7636c4d6..49b4595d90 100644 --- a/hw/intc/loongarch_ipi.c +++ b/hw/intc/loongarch_ipi.c @@ -55,6 +55,9 @@ static void loongarch_ipi_realize(DeviceState *dev, Error **errp) { LoongsonIPICommonState *lics = LOONGSON_IPI_COMMON(dev); LoongarchIPIClass *lic = LOONGARCH_IPI_GET_CLASS(dev); + MachineState *machine = MACHINE(qdev_get_machine()); + MachineClass *mc = MACHINE_GET_CLASS(machine); + const CPUArchIdList *id_list; Error *local_err = NULL; int i; @@ -64,13 +67,13 @@ static void loongarch_ipi_realize(DeviceState *dev, Error **errp) return; } - if (lics->num_cpu == 0) { - error_setg(errp, "num-cpu must be at least 1"); - return; - } - + assert(mc->possible_cpu_arch_ids); + id_list = mc->possible_cpu_arch_ids(machine); + lics->num_cpu = id_list->len; lics->cpu = g_new0(IPICore, lics->num_cpu); for (i = 0; i < lics->num_cpu; i++) { + lics->cpu[i].arch_id = id_list->cpus[i].arch_id; + lics->cpu[i].cpu = CPU(id_list->cpus[i].cpu); lics->cpu[i].ipi = lics; qdev_init_gpio_out(dev, &lics->cpu[i].irq, 1); } diff --git a/include/hw/intc/loongson_ipi_common.h b/include/hw/intc/loongson_ipi_common.h index df9d9c5168..4192f3d548 100644 --- a/include/hw/intc/loongson_ipi_common.h +++ b/include/hw/intc/loongson_ipi_common.h @@ -27,6 +27,8 @@ typedef struct IPICore { /* 64bit buf divide into 2 32-bit buf */ uint32_t buf[IPI_MBX_NUM * 2]; qemu_irq irq; + uint64_t arch_id; + CPUState *cpu; } IPICore; struct LoongsonIPICommonState { -- cgit 1.4.1 From 999b112d90be8404547eec0793f8d7c0b5d2a547 Mon Sep 17 00:00:00 2001 From: Bibo Mao Date: Tue, 7 Jan 2025 11:08:18 +0800 Subject: hw/intc/loongson_ipi: Add more input parameter for cpu_by_arch_id Add logic cpu index input parameter for function cpu_by_arch_id, CPUState::cpu_index is logic cpu slot index for possible_cpus. At the same time it is logic index with LoongsonIPICommonState::IPICore, here hide access for CPUState::cpu_index directly, it comes from function cpu_by_arch_id(). Signed-off-by: Bibo Mao Reviewed-by: Bibo Mao --- hw/intc/loongarch_ipi.c | 19 +++++++++++++++---- hw/intc/loongson_ipi.c | 23 ++++++++++++++++++++++- hw/intc/loongson_ipi_common.c | 21 ++++++++++++--------- include/hw/intc/loongson_ipi_common.h | 3 ++- 4 files changed, 51 insertions(+), 15 deletions(-) (limited to 'include/hw/intc') diff --git a/hw/intc/loongarch_ipi.c b/hw/intc/loongarch_ipi.c index 41d9625dcb..515549e8a5 100644 --- a/hw/intc/loongarch_ipi.c +++ b/hw/intc/loongarch_ipi.c @@ -38,17 +38,28 @@ static CPUArchId *find_cpu_by_archid(MachineState *ms, uint32_t id) return found_cpu; } -static CPUState *loongarch_cpu_by_arch_id(int64_t arch_id) +static int loongarch_cpu_by_arch_id(LoongsonIPICommonState *lics, + int64_t arch_id, int *index, CPUState **pcs) { MachineState *machine = MACHINE(qdev_get_machine()); CPUArchId *archid; + CPUState *cs; archid = find_cpu_by_archid(machine, arch_id); - if (archid) { - return CPU(archid->cpu); + if (archid && archid->cpu) { + cs = archid->cpu; + if (index) { + *index = cs->cpu_index; + } + + if (pcs) { + *pcs = cs; + } + + return MEMTX_OK; } - return NULL; + return MEMTX_ERROR; } static void loongarch_ipi_realize(DeviceState *dev, Error **errp) diff --git a/hw/intc/loongson_ipi.c b/hw/intc/loongson_ipi.c index 29e92d48fd..d2268a27f8 100644 --- a/hw/intc/loongson_ipi.c +++ b/hw/intc/loongson_ipi.c @@ -20,6 +20,27 @@ static AddressSpace *get_iocsr_as(CPUState *cpu) return NULL; } +static int loongson_cpu_by_arch_id(LoongsonIPICommonState *lics, + int64_t arch_id, int *index, CPUState **pcs) +{ + CPUState *cs; + + cs = cpu_by_arch_id(arch_id); + if (cs == NULL) { + return MEMTX_ERROR; + } + + if (index) { + *index = cs->cpu_index; + } + + if (pcs) { + *pcs = cs; + } + + return MEMTX_OK; +} + static const MemoryRegionOps loongson_ipi_core_ops = { .read_with_attrs = loongson_ipi_core_readl, .write_with_attrs = loongson_ipi_core_writel, @@ -92,7 +113,7 @@ static void loongson_ipi_class_init(ObjectClass *klass, void *data) &lic->parent_unrealize); device_class_set_props(dc, loongson_ipi_properties); licc->get_iocsr_as = get_iocsr_as; - licc->cpu_by_arch_id = cpu_by_arch_id; + licc->cpu_by_arch_id = loongson_cpu_by_arch_id; } static const TypeInfo loongson_ipi_types[] = { diff --git a/hw/intc/loongson_ipi_common.c b/hw/intc/loongson_ipi_common.c index 363cddc54c..f5ab5024c0 100644 --- a/hw/intc/loongson_ipi_common.c +++ b/hw/intc/loongson_ipi_common.c @@ -103,16 +103,17 @@ static MemTxResult mail_send(LoongsonIPICommonState *ipi, uint32_t cpuid; hwaddr addr; CPUState *cs; + int cpu, ret; cpuid = extract32(val, 16, 10); - cs = licc->cpu_by_arch_id(cpuid); - if (cs == NULL) { + ret = licc->cpu_by_arch_id(ipi, cpuid, &cpu, &cs); + if (ret != MEMTX_OK) { return MEMTX_DECODE_ERROR; } /* override requester_id */ addr = SMP_IPI_MAILBOX + CORE_BUF_20 + (val & 0x1c); - attrs.requester_id = cs->cpu_index; + attrs.requester_id = cpu; return send_ipi_data(ipi, cs, val, addr, attrs); } @@ -123,16 +124,17 @@ static MemTxResult any_send(LoongsonIPICommonState *ipi, uint32_t cpuid; hwaddr addr; CPUState *cs; + int cpu, ret; cpuid = extract32(val, 16, 10); - cs = licc->cpu_by_arch_id(cpuid); - if (cs == NULL) { + ret = licc->cpu_by_arch_id(ipi, cpuid, &cpu, &cs); + if (ret != MEMTX_OK) { return MEMTX_DECODE_ERROR; } /* override requester_id */ addr = val & 0xffff; - attrs.requester_id = cs->cpu_index; + attrs.requester_id = cpu; return send_ipi_data(ipi, cs, val, addr, attrs); } @@ -146,6 +148,7 @@ MemTxResult loongson_ipi_core_writel(void *opaque, hwaddr addr, uint64_t val, uint32_t cpuid; uint8_t vector; CPUState *cs; + int cpu, ret; addr &= 0xff; trace_loongson_ipi_write(size, (uint64_t)addr, val); @@ -176,11 +179,11 @@ MemTxResult loongson_ipi_core_writel(void *opaque, hwaddr addr, uint64_t val, cpuid = extract32(val, 16, 10); /* IPI status vector */ vector = extract8(val, 0, 5); - cs = licc->cpu_by_arch_id(cpuid); - if (cs == NULL || cs->cpu_index >= ipi->num_cpu) { + ret = licc->cpu_by_arch_id(ipi, cpuid, &cpu, &cs); + if (ret != MEMTX_OK || cpu >= ipi->num_cpu) { return MEMTX_DECODE_ERROR; } - loongson_ipi_core_writel(&ipi->cpu[cs->cpu_index], CORE_SET_OFF, + loongson_ipi_core_writel(&ipi->cpu[cpu], CORE_SET_OFF, BIT(vector), 4, attrs); break; default: diff --git a/include/hw/intc/loongson_ipi_common.h b/include/hw/intc/loongson_ipi_common.h index 4192f3d548..b587f9c571 100644 --- a/include/hw/intc/loongson_ipi_common.h +++ b/include/hw/intc/loongson_ipi_common.h @@ -46,7 +46,8 @@ struct LoongsonIPICommonClass { DeviceRealize parent_realize; DeviceUnrealize parent_unrealize; AddressSpace *(*get_iocsr_as)(CPUState *cpu); - CPUState *(*cpu_by_arch_id)(int64_t id); + int (*cpu_by_arch_id)(LoongsonIPICommonState *lics, int64_t id, + int *index, CPUState **pcs); }; MemTxResult loongson_ipi_core_readl(void *opaque, hwaddr addr, uint64_t *data, -- cgit 1.4.1