From b1ce38e12baf64c9cbe6e71c5b165a87248451b2 Mon Sep 17 00:00:00 2001 From: Peter Maydell Date: Fri, 2 Mar 2018 10:45:40 +0000 Subject: hw/misc/iotkit-secctl: Add remaining simple registers Add remaining easy registers to iotkit-secctl: * NSCCFG just routes its two bits out to external GPIO lines * BRGINSTAT/BRGINTCLR/BRGINTEN can be dummies, because QEMU's bus fabric can never report errors Signed-off-by: Peter Maydell Message-id: 20180220180325.29818-18-peter.maydell@linaro.org --- include/hw/misc/iotkit-secctl.h | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'include/hw/misc/iotkit-secctl.h') diff --git a/include/hw/misc/iotkit-secctl.h b/include/hw/misc/iotkit-secctl.h index ea3d62967f..faad0c9190 100644 --- a/include/hw/misc/iotkit-secctl.h +++ b/include/hw/misc/iotkit-secctl.h @@ -18,6 +18,7 @@ * + sysbus MMIO region 1 is the "non-secure privilege control block" registers * + named GPIO output "sec_resp_cfg" indicating whether blocked accesses * should RAZ/WI or bus error + * + named GPIO output "nsc_cfg" whose value tracks the NSCCFG register value * Controlling the 2 APB PPCs in the IoTKit: * + named GPIO outputs apb_ppc0_nonsec[0..2] and apb_ppc1_nonsec * + named GPIO outputs apb_ppc0_ap[0..2] and apb_ppc1_ap @@ -83,6 +84,7 @@ struct IoTKitSecCtl { /*< public >*/ qemu_irq sec_resp_cfg; + qemu_irq nsc_cfg_irq; MemoryRegion s_regs; MemoryRegion ns_regs; @@ -90,6 +92,8 @@ struct IoTKitSecCtl { uint32_t secppcintstat; uint32_t secppcinten; uint32_t secrespcfg; + uint32_t nsccfg; + uint32_t brginten; IoTKitSecCtlPPC apb[IOTS_NUM_APB_PPC]; IoTKitSecCtlPPC apbexp[IOTS_NUM_APB_EXP_PPC]; -- cgit 1.4.1