From 6487653efd54ea16c9fa39f0f7a648f27bc2c548 Mon Sep 17 00:00:00 2001 From: Arnaud Minier Date: Sun, 3 Mar 2024 15:06:38 +0100 Subject: hw/misc/stm32l4x5_rcc: Add an internal PLL Clock object MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This object represents the PLLs and their channels. The PLLs allow for a more fine-grained control of the clocks frequency. The migration handling is based on hw/misc/zynq_sclr.c. Three phase reset will be handled in a later commit. Signed-off-by: Arnaud Minier Signed-off-by: Inès Varhol Message-id: 20240303140643.81957-4-arnaud.minier@telecom-paris.fr Signed-off-by: Peter Maydell Reviewed-by: Peter Maydell --- include/hw/misc/stm32l4x5_rcc.h | 40 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 40 insertions(+) (limited to 'include/hw/misc/stm32l4x5_rcc.h') diff --git a/include/hw/misc/stm32l4x5_rcc.h b/include/hw/misc/stm32l4x5_rcc.h index 6719be9fbe..0fbfba5c40 100644 --- a/include/hw/misc/stm32l4x5_rcc.h +++ b/include/hw/misc/stm32l4x5_rcc.h @@ -26,6 +26,15 @@ OBJECT_DECLARE_SIMPLE_TYPE(Stm32l4x5RccState, STM32L4X5_RCC) /* In the Stm32l4x5 clock tree, mux have at most 7 sources */ #define RCC_NUM_CLOCK_MUX_SRC 7 + +typedef enum PllCommonChannels { + RCC_PLL_COMMON_CHANNEL_P = 0, + RCC_PLL_COMMON_CHANNEL_Q = 1, + RCC_PLL_COMMON_CHANNEL_R = 2, + + RCC_NUM_CHANNEL_PLL_OUT = 3 +} PllCommonChannels; + /* NB: Prescaler are assimilated to mux with one source and one output */ typedef enum RccClockMux { /* Internal muxes that arent't exposed publicly to other peripherals */ @@ -124,6 +133,14 @@ typedef enum RccClockMux { RCC_NUM_CLOCK_MUX } RccClockMux; +typedef enum RccPll { + RCC_PLL_PLL, + RCC_PLL_PLLSAI1, + RCC_PLL_PLLSAI2, + + RCC_NUM_PLL +} RccPll; + typedef struct RccClockMuxState { DeviceState parent_obj; @@ -142,6 +159,26 @@ typedef struct RccClockMuxState { struct RccClockMuxState *backref[RCC_NUM_CLOCK_MUX_SRC]; } RccClockMuxState; +typedef struct RccPllState { + DeviceState parent_obj; + + RccPll id; + Clock *in; + uint32_t vco_multiplier; + Clock *channels[RCC_NUM_CHANNEL_PLL_OUT]; + /* Global pll enabled flag */ + bool enabled; + /* 'enabled' refers to the runtime configuration */ + bool channel_enabled[RCC_NUM_CHANNEL_PLL_OUT]; + /* + * 'exists' refers to the physical configuration + * It should only be set at pll initialization. + * e.g. pllsai2 doesn't have a Q output. + */ + bool channel_exists[RCC_NUM_CHANNEL_PLL_OUT]; + uint32_t channel_divider[RCC_NUM_CHANNEL_PLL_OUT]; +} RccPllState; + struct Stm32l4x5RccState { SysBusDevice parent_obj; @@ -187,6 +224,9 @@ struct Stm32l4x5RccState { Clock *sai1_extclk; Clock *sai2_extclk; + /* PLLs */ + RccPllState plls[RCC_NUM_PLL]; + /* Muxes ~= outputs */ RccClockMuxState clock_muxes[RCC_NUM_CLOCK_MUX]; -- cgit 1.4.1