From d9e6b8424fd2523a0361972d5dd841471879479c Mon Sep 17 00:00:00 2001 From: Shameer Kolothum Date: Fri, 29 Aug 2025 09:25:23 +0100 Subject: hw/arm/smmu-common: Check SMMU has PCIe Root Complex association We only allow default PCIe Root Complex(pcie.0) or pxb-pcie based extra root complexes to be associated with SMMU. Although this change does not affect functionality at present, it is required when we add support for user-creatable SMMUv3 devices in future patches. Note: Added a specific check to identify pxb-pcie to avoid matching pxb-cxl host bridges, which are also of type PCI_HOST_BRIDGE. This restriction can be relaxed once support for CXL devices on arm/virt is added and validated with SMMUv3. Reviewed-by: Jonathan Cameron Reviewed-by: Eric Auger Tested-by: Nathan Chen Tested-by: Eric Auger Reviewed-by: Nicolin Chen Tested-by: Nicolin Chen Signed-off-by: Shameer Kolothum Signed-off-by: Shameer Kolothum Reviewed-by: Donald Dutile Message-id: 20250829082543.7680-2-skolothumtho@nvidia.com Signed-off-by: Peter Maydell --- include/hw/pci/pci_bridge.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include/hw/pci/pci_bridge.h') diff --git a/include/hw/pci/pci_bridge.h b/include/hw/pci/pci_bridge.h index 8cdacbc4e1..a055fd8d32 100644 --- a/include/hw/pci/pci_bridge.h +++ b/include/hw/pci/pci_bridge.h @@ -104,6 +104,7 @@ typedef struct PXBPCIEDev { PXBDev parent_obj; } PXBPCIEDev; +#define TYPE_PXB_PCIE_BUS "pxb-pcie-bus" #define TYPE_PXB_CXL_BUS "pxb-cxl-bus" #define TYPE_PXB_DEV "pxb" OBJECT_DECLARE_SIMPLE_TYPE(PXBDev, PXB_DEV) -- cgit 1.4.1