From f55d613bc97cd8d08487eddec313c3298a906a91 Mon Sep 17 00:00:00 2001 From: Andrew Jeffery Date: Mon, 4 Sep 2017 15:21:54 +0100 Subject: watchdog: wdt_aspeed: Add support for the reset width register MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The reset width register controls how the pulse on the SoC's WDTRST{1,2} pins behaves. A pulse is emitted if the external reset bit is set in WDT_CTRL. On the AST2500 WDT_RESET_WIDTH can consume magic bit patterns to configure push-pull/open-drain and active-high/active-low behaviours and thus needs some special handling in the write path. As some of the capabilities depend on the SoC version a silicon-rev property is introduced, which is used to guard version-specific behaviour. Signed-off-by: Andrew Jeffery Reviewed-by: Cédric Le Goater Signed-off-by: Peter Maydell --- include/hw/watchdog/wdt_aspeed.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'include/hw/watchdog/wdt_aspeed.h') diff --git a/include/hw/watchdog/wdt_aspeed.h b/include/hw/watchdog/wdt_aspeed.h index 080c223122..7de3e5c224 100644 --- a/include/hw/watchdog/wdt_aspeed.h +++ b/include/hw/watchdog/wdt_aspeed.h @@ -27,6 +27,8 @@ typedef struct AspeedWDTState { uint32_t regs[ASPEED_WDT_REGS_MAX]; uint32_t pclk_freq; + uint32_t silicon_rev; + uint32_t ext_pulse_width_mask; } AspeedWDTState; #endif /* ASPEED_WDT_H */ -- cgit 1.4.1