From 0dcbc88865432504dc452d9ded8218dff3bdf0d2 Mon Sep 17 00:00:00 2001 From: Aditya Gupta Date: Thu, 25 Sep 2025 23:00:45 +0530 Subject: ppc/pnv: Add XIVE2 controller to Power11 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add a XIVE2 controller to Power11 chip and machine. The controller has the same logic as Power10. Reviewed-by: Cédric Le Goater Signed-off-by: Aditya Gupta Tested-by: Amit Machhiwal Tested-by: Cédric Le Goater Signed-off-by: Harsh Prateek Bora Link: https://lore.kernel.org/r/20250925173049.891406-5-adityag@linux.ibm.com Message-ID: <20250925173049.891406-5-adityag@linux.ibm.com> --- include/hw/ppc/pnv.h | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) (limited to 'include') diff --git a/include/hw/ppc/pnv.h b/include/hw/ppc/pnv.h index f0002627bc..cbdddfc73c 100644 --- a/include/hw/ppc/pnv.h +++ b/include/hw/ppc/pnv.h @@ -270,6 +270,24 @@ void pnv_bmc_set_pnor(IPMIBmc *bmc, PnvPnor *pnor); #define PNV11_PSIHB_SIZE PNV10_PSIHB_SIZE #define PNV11_PSIHB_BASE(chip) PNV10_PSIHB_BASE(chip) +#define PNV11_XIVE2_IC_SIZE PNV10_XIVE2_IC_SIZE +#define PNV11_XIVE2_IC_BASE(chip) PNV10_XIVE2_IC_BASE(chip) + +#define PNV11_XIVE2_TM_SIZE PNV10_XIVE2_TM_SIZE +#define PNV11_XIVE2_TM_BASE(chip) PNV10_XIVE2_TM_BASE(chip) + +#define PNV11_XIVE2_NVC_SIZE PNV10_XIVE2_NVC_SIZE +#define PNV11_XIVE2_NVC_BASE(chip) PNV10_XIVE2_NVC_BASE(chip) + +#define PNV11_XIVE2_NVPG_SIZE PNV10_XIVE2_NVPG_SIZE +#define PNV11_XIVE2_NVPG_BASE(chip) PNV10_XIVE2_NVPG_BASE(chip) + +#define PNV11_XIVE2_ESB_SIZE PNV10_XIVE2_ESB_SIZE +#define PNV11_XIVE2_ESB_BASE(chip) PNV10_XIVE2_ESB_BASE(chip) + +#define PNV11_XIVE2_END_SIZE PNV10_XIVE2_END_SIZE +#define PNV11_XIVE2_END_BASE(chip) PNV10_XIVE2_END_BASE(chip) + #define PNV11_OCC_SENSOR_BASE(chip) PNV10_OCC_SENSOR_BASE(chip) #endif /* PPC_PNV_H */ -- cgit 1.4.1