From 1239b472bb0dba8060f1af29d40dafbc1b2860d4 Mon Sep 17 00:00:00 2001 From: Kwok Cheung Yeung Date: Fri, 17 May 2013 14:51:21 -0700 Subject: linux-user: Save the correct resume address for MIPS signal handling The current ISA mode needs to be saved in bit 0 of the resume address. If the current instruction happens to be in a branch delay slot, then the address of the preceding jump instruction should be stored instead. exception_resume_pc already does both of these tasks, so it is made available and reused. MIPS_HFLAG_BMASK in hflags is cleared, otherwise QEMU may treat the first instruction of the signal handler as a delay slot instruction. Signed-off-by: Kwok Cheung Yeung Signed-off-by: Aurelien Jarno --- target-mips/cpu.h | 1 + 1 file changed, 1 insertion(+) (limited to 'target-mips/cpu.h') diff --git a/target-mips/cpu.h b/target-mips/cpu.h index cedf03df43..6e761e03b6 100644 --- a/target-mips/cpu.h +++ b/target-mips/cpu.h @@ -668,6 +668,7 @@ void r4k_invalidate_tlb (CPUMIPSState *env, int idx, int use_extra); hwaddr cpu_mips_translate_address (CPUMIPSState *env, target_ulong address, int rw); #endif +target_ulong exception_resume_pc (CPUMIPSState *env); static inline void cpu_get_tb_cpu_state(CPUMIPSState *env, target_ulong *pc, target_ulong *cs_base, int *flags) -- cgit 1.4.1