From 8a60ffe9a8f46ed514656eb4a40d1386c439daf8 Mon Sep 17 00:00:00 2001 From: Gustavo Romero Date: Tue, 26 Aug 2025 11:21:28 +0100 Subject: target/arm: Implement FEAT_SCTLR2 and enable with -cpu max Add FEAT_SCTLR2, which introduces the SCTLR2_EL1, SCTLR2_EL2, and SCTLR2_EL3 registers. These registers are extensions of the SCTLR_ELx ones. Signed-off-by: Gustavo Romero Reviewed-by: Richard Henderson Signed-off-by: Richard Henderson Message-id: 20250727074202.83141-4-richard.henderson@linaro.org Message-ID: <20250711140828.1714666-4-gustavo.romero@linaro.org> [rth: Remove FEAT_MEC code; handle SCR and HCRX enable bits.] Signed-off-by: Richard Henderson Signed-off-by: Peter Maydell --- target/arm/cpu-features.h | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'target/arm/cpu-features.h') diff --git a/target/arm/cpu-features.h b/target/arm/cpu-features.h index 5876162428..e372543bf3 100644 --- a/target/arm/cpu-features.h +++ b/target/arm/cpu-features.h @@ -904,6 +904,11 @@ static inline bool isar_feature_aa64_nv2(const ARMISARegisters *id) return FIELD_EX64_IDREG(id, ID_AA64MMFR2, NV) >= 2; } +static inline bool isar_feature_aa64_sctlr2(const ARMISARegisters *id) +{ + return FIELD_EX64_IDREG(id, ID_AA64MMFR3, SCTLRX) != 0; +} + static inline bool isar_feature_aa64_pmuv3p1(const ARMISARegisters *id) { return FIELD_EX64_IDREG(id, ID_AA64DFR0, PMUVER) >= 4 && -- cgit 1.4.1