From 21c2dd77a6aa5173764abe1371b06cc2a7541c4f Mon Sep 17 00:00:00 2001 From: Peter Maydell Date: Wed, 31 Mar 2021 16:48:22 +0100 Subject: Revert "target/arm: Make number of counters in PMCR follow the CPU" This reverts commit f7fb73b8cdd3f77e26f9fcff8cf24ff1b58d200f. This change turned out to be a bit half-baked, and doesn't work with KVM, which fails with the error: "qemu-system-aarch64: Failed to retrieve host CPU features" because KVM does not allow accessing of the PMCR_EL0 value in the scratch "query CPU ID registers" VM unless we have first set the KVM_ARM_VCPU_PMU_V3 feature on the VM. Revert the change for 6.0. Reported-by: Zenghui Yu Signed-off-by: Peter Maydell Tested-by: Zenghui Yu Message-id: 20210331154822.23332-1-peter.maydell@linaro.org --- target/arm/cpu64.c | 3 --- 1 file changed, 3 deletions(-) (limited to 'target/arm/cpu64.c') diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 5d9d56a33c..f0a9e968c9 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -141,7 +141,6 @@ static void aarch64_a57_initfn(Object *obj) cpu->gic_num_lrs = 4; cpu->gic_vpribits = 5; cpu->gic_vprebits = 5; - cpu->isar.reset_pmcr_el0 = 0x41013000; define_arm_cp_regs(cpu, cortex_a72_a57_a53_cp_reginfo); } @@ -195,7 +194,6 @@ static void aarch64_a53_initfn(Object *obj) cpu->gic_num_lrs = 4; cpu->gic_vpribits = 5; cpu->gic_vprebits = 5; - cpu->isar.reset_pmcr_el0 = 0x41033000; define_arm_cp_regs(cpu, cortex_a72_a57_a53_cp_reginfo); } @@ -247,7 +245,6 @@ static void aarch64_a72_initfn(Object *obj) cpu->gic_num_lrs = 4; cpu->gic_vpribits = 5; cpu->gic_vprebits = 5; - cpu->isar.reset_pmcr_el0 = 0x41023000; define_arm_cp_regs(cpu, cortex_a72_a57_a53_cp_reginfo); } -- cgit 1.4.1