From fc6177af1137789dccb9e257bfae778d18381f90 Mon Sep 17 00:00:00 2001 From: Peter Maydell Date: Sat, 22 Jan 2022 18:24:31 +0000 Subject: target/arm: Log CPU index in 'Taking exception' log MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit In an SMP system it can be unclear which CPU is taking an exception; add the CPU index (which is the same value used in the TCG 'Trace %d:' logging) to the "Taking exception" log line to clarify it. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-id: 20220122182444.724087-2-peter.maydell@linaro.org --- target/arm/helper.c | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) (limited to 'target/arm/helper.c') diff --git a/target/arm/helper.c b/target/arm/helper.c index cfca0f5ba6..4df1239402 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -9317,8 +9317,10 @@ uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx, return target_el; } -void arm_log_exception(int idx) +void arm_log_exception(CPUState *cs) { + int idx = cs->exception_index; + if (qemu_loglevel_mask(CPU_LOG_INT)) { const char *exc = NULL; static const char * const excnames[] = { @@ -9352,7 +9354,8 @@ void arm_log_exception(int idx) if (!exc) { exc = "unknown"; } - qemu_log_mask(CPU_LOG_INT, "Taking exception %d [%s]\n", idx, exc); + qemu_log_mask(CPU_LOG_INT, "Taking exception %d [%s] on CPU %d\n", + idx, exc, cs->cpu_index); } } @@ -10185,7 +10188,7 @@ void arm_cpu_do_interrupt(CPUState *cs) assert(!arm_feature(env, ARM_FEATURE_M)); - arm_log_exception(cs->exception_index); + arm_log_exception(cs); qemu_log_mask(CPU_LOG_INT, "...from EL%d to EL%d\n", arm_current_el(env), new_el); if (qemu_loglevel_mask(CPU_LOG_INT) -- cgit 1.4.1 From 2c023d3675a3ffb54fc30504dcd715bc6f6e234f Mon Sep 17 00:00:00 2001 From: Peter Maydell Date: Mon, 17 Jan 2022 13:19:53 +0000 Subject: target/arm: Use correct entrypoint for SVC taken from Hyp to Hyp The exception caused by an SVC instruction may be taken to AArch32 Hyp mode for two reasons: * HCR.TGE indicates that exceptions from EL0 should trap to EL2 * we were already in Hyp mode The entrypoint in the vector table to be used differs in these two cases: for an exception routed to Hyp mode from EL0, we enter at the common 0x14 "hyp trap" entrypoint. For SVC from Hyp mode to Hyp mode, we enter at the 0x08 (svc/hvc trap) entrypoint. In the v8A Arm ARM pseudocode this is done in AArch32.TakeSVCException. QEMU incorrectly routed both of these exceptions to the 0x14 entrypoint. Correct the entrypoint for SVC from Hyp to Hyp by making use of the existing logic which handles "normal entrypoint for Hyp-to-Hyp, otherwise 0x14" for traps like UNDEF and data/prefetch aborts (reproduced here since it's outside the visible context in the diff for this commit): if (arm_current_el(env) != 2 && addr < 0x14) { addr = 0x14; } Signed-off-by: Peter Maydell Reviewed-by: Edgar E. Iglesias Reviewed-by: Richard Henderson Message-id: 20220117131953.3936137-1-peter.maydell@linaro.org --- target/arm/helper.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'target/arm/helper.c') diff --git a/target/arm/helper.c b/target/arm/helper.c index 4df1239402..6dd241fbef 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -9658,7 +9658,7 @@ static void arm_cpu_do_interrupt_aarch32_hyp(CPUState *cs) * separately here. * * The vector table entry used is always the 0x14 Hyp mode entry point, - * unless this is an UNDEF/HVC/abort taken from Hyp to Hyp. + * unless this is an UNDEF/SVC/HVC/abort taken from Hyp to Hyp. * The offset applied to the preferred return address is always zero * (see DDI0487C.a section G1.12.3). * PSTATE A/I/F masks are set based only on the SCR.EA/IRQ/FIQ values. @@ -9672,7 +9672,7 @@ static void arm_cpu_do_interrupt_aarch32_hyp(CPUState *cs) addr = 0x04; break; case EXCP_SWI: - addr = 0x14; + addr = 0x08; break; case EXCP_BKPT: /* Fall through to prefetch abort. */ -- cgit 1.4.1