From 8b80bd28a5cf8d8af7d38abcf1c7d81a1b226ec3 Mon Sep 17 00:00:00 2001 From: Philippe Mathieu-Daudé Date: Mon, 17 May 2021 12:51:31 +0200 Subject: cpu: Introduce SysemuCPUOps structure MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Introduce a structure to hold handler specific to sysemu. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20210517105140.1062037-15-f4bug@amsat.org> [rth: Squash "restrict hw/core/sysemu-cpu-ops.h" patch] Signed-off-by: Richard Henderson --- target/avr/cpu.c | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'target/avr/cpu.c') diff --git a/target/avr/cpu.c b/target/avr/cpu.c index 3353bcb9fc..b95caf8c0f 100644 --- a/target/avr/cpu.c +++ b/target/avr/cpu.c @@ -184,6 +184,11 @@ static void avr_cpu_dump_state(CPUState *cs, FILE *f, int flags) qemu_fprintf(f, "\n"); } +#include "hw/core/sysemu-cpu-ops.h" + +static const struct SysemuCPUOps avr_sysemu_ops = { +}; + #include "hw/core/tcg-cpu-ops.h" static struct TCGCPUOps avr_tcg_ops = { @@ -214,6 +219,7 @@ static void avr_cpu_class_init(ObjectClass *oc, void *data) cc->memory_rw_debug = avr_cpu_memory_rw_debug; cc->get_phys_page_debug = avr_cpu_get_phys_page_debug; dc->vmsd = &vms_avr_cpu; + cc->sysemu_ops = &avr_sysemu_ops; cc->disas_set_info = avr_cpu_disas_set_info; cc->gdb_read_register = avr_cpu_gdb_read_register; cc->gdb_write_register = avr_cpu_gdb_write_register; -- cgit 1.4.1