From c53e401ed9ffe4a5f5fe914828c0bfe9bf813cff Mon Sep 17 00:00:00 2001 From: Richard Henderson Date: Tue, 17 Oct 2023 21:11:19 -0700 Subject: target/hppa: Remove TARGET_REGISTER_BITS Rely only on TARGET_LONG_BITS, fixed at 64, and hppa_is_pa20. Signed-off-by: Richard Henderson --- target/hppa/int_helper.c | 17 ++++++++--------- 1 file changed, 8 insertions(+), 9 deletions(-) (limited to 'target/hppa/int_helper.c') diff --git a/target/hppa/int_helper.c b/target/hppa/int_helper.c index 3ab9934a1d..f355c4c76b 100644 --- a/target/hppa/int_helper.c +++ b/target/hppa/int_helper.c @@ -52,9 +52,9 @@ static void io_eir_write(void *opaque, hwaddr addr, uint64_t data, unsigned size) { HPPACPU *cpu = opaque; - int le_bit = ~data & (TARGET_REGISTER_BITS - 1); + int le_bit = ~data & 31; - cpu->env.cr[CR_EIRR] |= (target_ureg)1 << le_bit; + cpu->env.cr[CR_EIRR] |= (target_ulong)1 << le_bit; eval_interrupt(cpu); } @@ -73,7 +73,7 @@ void hppa_cpu_alarm_timer(void *opaque) io_eir_write(opaque, 0, 0, 4); } -void HELPER(write_eirr)(CPUHPPAState *env, target_ureg val) +void HELPER(write_eirr)(CPUHPPAState *env, target_ulong val) { env->cr[CR_EIRR] &= ~val; qemu_mutex_lock_iothread(); @@ -81,7 +81,7 @@ void HELPER(write_eirr)(CPUHPPAState *env, target_ureg val) qemu_mutex_unlock_iothread(); } -void HELPER(write_eiem)(CPUHPPAState *env, target_ureg val) +void HELPER(write_eiem)(CPUHPPAState *env, target_ulong val) { env->cr[CR_EIEM] = val; qemu_mutex_lock_iothread(); @@ -94,12 +94,11 @@ void hppa_cpu_do_interrupt(CPUState *cs) HPPACPU *cpu = HPPA_CPU(cs); CPUHPPAState *env = &cpu->env; int i = cs->exception_index; - target_ureg iaoq_f = env->iaoq_f; - target_ureg iaoq_b = env->iaoq_b; + target_ulong iaoq_f = env->iaoq_f; + target_ulong iaoq_b = env->iaoq_b; uint64_t iasq_f = env->iasq_f; uint64_t iasq_b = env->iasq_b; - - target_ureg old_psw; + target_ulong old_psw; /* As documented in pa2.0 -- interruption handling. */ /* step 1 */ @@ -240,7 +239,7 @@ void hppa_cpu_do_interrupt(CPUState *cs) name = unknown; } qemu_log("INT %6d: %s @ " TARGET_FMT_lx "," TARGET_FMT_lx - " -> " TREG_FMT_lx " " TARGET_FMT_lx "\n", + " -> " TARGET_FMT_lx " " TARGET_FMT_lx "\n", ++count, name, hppa_form_gva(env, iasq_f, iaoq_f), hppa_form_gva(env, iasq_b, iaoq_b), -- cgit 1.4.1 From ab9af359c175378c6aa716de0f8e2acbcbcba376 Mon Sep 17 00:00:00 2001 From: Helge Deller Date: Tue, 17 Oct 2023 11:36:37 +0200 Subject: target/hppa: Fix interruption based on default PSW The default PSW is set by the operating system with the PDC_PSW firmware call. Use that setting to decide if wide mode is to be enabled for interruptions and EIRR usage. Signed-off-by: Helge Deller Reviewed-by: Richard Henderson Signed-off-by: Richard Henderson --- target/hppa/cpu.h | 2 ++ target/hppa/int_helper.c | 18 ++++++++++++++---- 2 files changed, 16 insertions(+), 4 deletions(-) (limited to 'target/hppa/int_helper.c') diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h index ea676ba062..ea8e7e99a4 100644 --- a/target/hppa/cpu.h +++ b/target/hppa/cpu.h @@ -137,6 +137,8 @@ #define PSW_SM_W 0x200 /* PA2.0 only : Enable Wide Mode */ #define CR_RC 0 +#define CR_PSW_DEFAULT 6 /* see SeaBIOS PDC_PSW firmware call */ +#define PDC_PSW_WIDE_BIT 2 #define CR_PID1 8 #define CR_PID2 9 #define CR_PID3 12 diff --git a/target/hppa/int_helper.c b/target/hppa/int_helper.c index f355c4c76b..a11d607b31 100644 --- a/target/hppa/int_helper.c +++ b/target/hppa/int_helper.c @@ -52,9 +52,17 @@ static void io_eir_write(void *opaque, hwaddr addr, uint64_t data, unsigned size) { HPPACPU *cpu = opaque; - int le_bit = ~data & 31; + CPUHPPAState *env = &cpu->env; + int widthm1 = 31; + int le_bit; + + /* The default PSW.W controls the width of EIRR. */ + if (hppa_is_pa20(env) && env->cr[CR_PSW_DEFAULT] & PDC_PSW_WIDE_BIT) { + widthm1 = 63; + } + le_bit = ~data & widthm1; - cpu->env.cr[CR_EIRR] |= (target_ulong)1 << le_bit; + env->cr[CR_EIRR] |= 1ull << le_bit; eval_interrupt(cpu); } @@ -104,8 +112,10 @@ void hppa_cpu_do_interrupt(CPUState *cs) /* step 1 */ env->cr[CR_IPSW] = old_psw = cpu_hppa_get_psw(env); - /* step 2 -- note PSW_W == 0 for !HPPA64. */ - cpu_hppa_put_psw(env, PSW_W | (i == EXCP_HPMC ? PSW_M : 0)); + /* step 2 -- Note PSW_W is masked out again for pa1.x */ + cpu_hppa_put_psw(env, + (env->cr[CR_PSW_DEFAULT] & PDC_PSW_WIDE_BIT ? PSW_W : 0) | + (i == EXCP_HPMC ? PSW_M : 0)); /* step 3 */ env->cr[CR_IIASQ] = iasq_f >> 32; -- cgit 1.4.1 From b10700d826c864872deae6c28aca041fc97df79f Mon Sep 17 00:00:00 2001 From: Richard Henderson Date: Fri, 27 Oct 2023 04:10:45 -0700 Subject: target/hppa: Update IIAOQ, IIASQ for pa2.0 These registers have a different format for pa2.0. Signed-off-by: Richard Henderson --- target/hppa/int_helper.c | 46 ++++++++++++++++++++++++++++------------------ target/hppa/sys_helper.c | 10 ++++++++++ 2 files changed, 38 insertions(+), 18 deletions(-) (limited to 'target/hppa/int_helper.c') diff --git a/target/hppa/int_helper.c b/target/hppa/int_helper.c index a11d607b31..54875442e7 100644 --- a/target/hppa/int_helper.c +++ b/target/hppa/int_helper.c @@ -102,11 +102,7 @@ void hppa_cpu_do_interrupt(CPUState *cs) HPPACPU *cpu = HPPA_CPU(cs); CPUHPPAState *env = &cpu->env; int i = cs->exception_index; - target_ulong iaoq_f = env->iaoq_f; - target_ulong iaoq_b = env->iaoq_b; - uint64_t iasq_f = env->iasq_f; - uint64_t iasq_b = env->iasq_b; - target_ulong old_psw; + uint64_t old_psw; /* As documented in pa2.0 -- interruption handling. */ /* step 1 */ @@ -118,10 +114,25 @@ void hppa_cpu_do_interrupt(CPUState *cs) (i == EXCP_HPMC ? PSW_M : 0)); /* step 3 */ - env->cr[CR_IIASQ] = iasq_f >> 32; - env->cr_back[0] = iasq_b >> 32; - env->cr[CR_IIAOQ] = iaoq_f; - env->cr_back[1] = iaoq_b; + /* + * For pa1.x, IIASQ is simply a copy of IASQ. + * For pa2.0, IIASQ is the top bits of the virtual address, + * or zero if translation is disabled. + */ + if (!hppa_is_pa20(env)) { + env->cr[CR_IIASQ] = env->iasq_f >> 32; + env->cr_back[0] = env->iasq_b >> 32; + } else if (old_psw & PSW_C) { + env->cr[CR_IIASQ] = + hppa_form_gva_psw(old_psw, env->iasq_f, env->iaoq_f) >> 32; + env->cr_back[0] = + hppa_form_gva_psw(old_psw, env->iasq_f, env->iaoq_f) >> 32; + } else { + env->cr[CR_IIASQ] = 0; + env->cr_back[0] = 0; + } + env->cr[CR_IIAOQ] = env->iaoq_f; + env->cr_back[1] = env->iaoq_b; if (old_psw & PSW_Q) { /* step 5 */ @@ -154,14 +165,13 @@ void hppa_cpu_do_interrupt(CPUState *cs) /* ??? An alternate fool-proof method would be to store the instruction data into the unwind info. That's probably a bit too much in the way of extra storage required. */ - vaddr vaddr; - hwaddr paddr; + vaddr vaddr = env->iaoq_f & -4; + hwaddr paddr = vaddr; - paddr = vaddr = iaoq_f & -4; if (old_psw & PSW_C) { int prot, t; - vaddr = hppa_form_gva_psw(old_psw, iasq_f, vaddr); + vaddr = hppa_form_gva_psw(old_psw, env->iasq_f, vaddr); t = hppa_get_physical_address(env, vaddr, MMU_KERNEL_IDX, 0, &paddr, &prot, NULL); if (t >= 0) { @@ -191,14 +201,14 @@ void hppa_cpu_do_interrupt(CPUState *cs) /* step 7 */ if (i == EXCP_TOC) { - env->iaoq_f = FIRMWARE_START; + env->iaoq_f = hppa_form_gva(env, 0, FIRMWARE_START); /* help SeaBIOS and provide iaoq_b and iasq_back in shadow regs */ env->gr[24] = env->cr_back[0]; env->gr[25] = env->cr_back[1]; } else { - env->iaoq_f = env->cr[CR_IVA] + 32 * i; + env->iaoq_f = hppa_form_gva(env, 0, env->cr[CR_IVA] + 32 * i); } - env->iaoq_b = env->iaoq_f + 4; + env->iaoq_b = hppa_form_gva(env, 0, env->iaoq_f + 4); env->iasq_f = 0; env->iasq_b = 0; @@ -251,8 +261,8 @@ void hppa_cpu_do_interrupt(CPUState *cs) qemu_log("INT %6d: %s @ " TARGET_FMT_lx "," TARGET_FMT_lx " -> " TARGET_FMT_lx " " TARGET_FMT_lx "\n", ++count, name, - hppa_form_gva(env, iasq_f, iaoq_f), - hppa_form_gva(env, iasq_b, iaoq_b), + hppa_form_gva(env, env->iasq_f, env->iaoq_f), + hppa_form_gva(env, env->iasq_b, env->iaoq_b), env->iaoq_f, hppa_form_gva(env, (uint64_t)env->cr[CR_ISR] << 32, env->cr[CR_IOR])); diff --git a/target/hppa/sys_helper.c b/target/hppa/sys_helper.c index 8850576ac3..a59245eed3 100644 --- a/target/hppa/sys_helper.c +++ b/target/hppa/sys_helper.c @@ -80,6 +80,16 @@ void HELPER(rfi)(CPUHPPAState *env) env->iasq_b = (uint64_t)env->cr_back[0] << 32; env->iaoq_f = env->cr[CR_IIAOQ]; env->iaoq_b = env->cr_back[1]; + + /* + * For pa2.0, IIASQ is the top bits of the virtual address. + * To recreate the space identifier, remove the offset bits. + */ + if (hppa_is_pa20(env)) { + env->iasq_f &= ~env->iaoq_f; + env->iasq_b &= ~env->iaoq_b; + } + cpu_hppa_put_psw(env, env->cr[CR_IPSW]); } -- cgit 1.4.1 From 5dd5c003661c364d5c339675532c3d5c60207994 Mon Sep 17 00:00:00 2001 From: Richard Henderson Date: Wed, 1 Nov 2023 10:33:58 -0700 Subject: target/hppa: Improve interrupt logging Signed-off-by: Richard Henderson --- target/hppa/int_helper.c | 12 ++++-------- 1 file changed, 4 insertions(+), 8 deletions(-) (limited to 'target/hppa/int_helper.c') diff --git a/target/hppa/int_helper.c b/target/hppa/int_helper.c index 54875442e7..467ee7daf5 100644 --- a/target/hppa/int_helper.c +++ b/target/hppa/int_helper.c @@ -258,14 +258,10 @@ void hppa_cpu_do_interrupt(CPUState *cs) snprintf(unknown, sizeof(unknown), "unknown %d", i); name = unknown; } - qemu_log("INT %6d: %s @ " TARGET_FMT_lx "," TARGET_FMT_lx - " -> " TARGET_FMT_lx " " TARGET_FMT_lx "\n", - ++count, name, - hppa_form_gva(env, env->iasq_f, env->iaoq_f), - hppa_form_gva(env, env->iasq_b, env->iaoq_b), - env->iaoq_f, - hppa_form_gva(env, (uint64_t)env->cr[CR_ISR] << 32, - env->cr[CR_IOR])); + qemu_log("INT %6d: %s @ " TARGET_FMT_lx ":" TARGET_FMT_lx + " for " TARGET_FMT_lx ":" TARGET_FMT_lx "\n", + ++count, name, env->cr[CR_IIASQ], env->cr[CR_IIAOQ], + env->cr[CR_ISR], env->cr[CR_IOR]); } cs->exception_index = -1; } -- cgit 1.4.1