From fe636d3722bf266c7b1bd3ca12fa53fb78ceffa0 Mon Sep 17 00:00:00 2001 From: Richard Henderson Date: Sun, 25 Aug 2019 15:44:11 -0700 Subject: target/openrisc: Check CPUCFG_OF32S for float insns Make sure the OF32S insns are enabled before allowing execution. Include the missing bit for cpu "any". Reviewed-by: Stafford Horne Signed-off-by: Richard Henderson --- target/openrisc/cpu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'target/openrisc/cpu.c') diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c index 9f566ad883..f3c8134531 100644 --- a/target/openrisc/cpu.c +++ b/target/openrisc/cpu.c @@ -131,7 +131,7 @@ static void openrisc_any_initfn(Object *obj) cpu->env.avr = 0x01010000; /* Architecture v1.1 */ cpu->env.upr = UPR_UP | UPR_DMP | UPR_IMP | UPR_PICP | UPR_TTP | UPR_PMP; - cpu->env.cpucfgr = CPUCFGR_NSGF | CPUCFGR_OB32S | + cpu->env.cpucfgr = CPUCFGR_NSGF | CPUCFGR_OB32S | CPUCFGR_OF32S | CPUCFGR_AVRP | CPUCFGR_EVBARP; /* 1Way, TLB_SIZE entries. */ -- cgit 1.4.1