From 455d45d22cc3b2c29c7840f2478647a0a3d9d8b4 Mon Sep 17 00:00:00 2001 From: Richard Henderson Date: Tue, 22 May 2018 16:28:33 -0700 Subject: target/openrisc: Merge tlb allocation into CPUOpenRISCState There is no reason to allocate this separately. This was probably copied from target/mips which makes the same mistake. While doing so, move tlb into the clear-on-reset range. While not all of the TLB bits are guaranteed zero on reset, all of the valid bits are cleared, and the rest of the bits are unspecified. Therefore clearing the whole of the TLB is correct. Reviewed-by: Stafford Horne Signed-off-by: Richard Henderson Signed-off-by: Stafford Horne --- target/openrisc/machine.c | 15 ++++++--------- 1 file changed, 6 insertions(+), 9 deletions(-) (limited to 'target/openrisc/machine.c') diff --git a/target/openrisc/machine.c b/target/openrisc/machine.c index 0a793eb14d..c10d28b055 100644 --- a/target/openrisc/machine.c +++ b/target/openrisc/machine.c @@ -30,18 +30,18 @@ static int env_post_load(void *opaque, int version_id) /* Restore MMU handlers */ if (env->sr & SR_DME) { - env->tlb->cpu_openrisc_map_address_data = + env->tlb.cpu_openrisc_map_address_data = &cpu_openrisc_get_phys_data; } else { - env->tlb->cpu_openrisc_map_address_data = + env->tlb.cpu_openrisc_map_address_data = &cpu_openrisc_get_phys_nommu; } if (env->sr & SR_IME) { - env->tlb->cpu_openrisc_map_address_code = + env->tlb.cpu_openrisc_map_address_code = &cpu_openrisc_get_phys_code; } else { - env->tlb->cpu_openrisc_map_address_code = + env->tlb.cpu_openrisc_map_address_code = &cpu_openrisc_get_phys_nommu; } @@ -77,10 +77,6 @@ static const VMStateDescription vmstate_cpu_tlb = { } }; -#define VMSTATE_CPU_TLB(_f, _s) \ - VMSTATE_STRUCT_POINTER(_f, _s, vmstate_cpu_tlb, CPUOpenRISCTLBContext) - - static int get_sr(QEMUFile *f, void *opaque, size_t size, VMStateField *field) { CPUOpenRISCState *env = opaque; @@ -143,7 +139,8 @@ static const VMStateDescription vmstate_env = { VMSTATE_UINT32(fpcsr, CPUOpenRISCState), VMSTATE_UINT64(mac, CPUOpenRISCState), - VMSTATE_CPU_TLB(tlb, CPUOpenRISCState), + VMSTATE_STRUCT(tlb, CPUOpenRISCState, 1, + vmstate_cpu_tlb, CPUOpenRISCTLBContext), VMSTATE_TIMER_PTR(timer, CPUOpenRISCState), VMSTATE_UINT32(ttmr, CPUOpenRISCState), -- cgit 1.4.1 From 23d45ebdb198378ae580c98ac898aa4b615059fd Mon Sep 17 00:00:00 2001 From: Richard Henderson Date: Tue, 22 May 2018 16:51:19 -0700 Subject: target/openrisc: Remove indirect function calls for mmu There is no reason to use an indirect branch instead of simply testing the SR bits that control mmu state. Signed-off-by: Richard Henderson Signed-off-by: Stafford Horne --- target/openrisc/cpu.c | 4 --- target/openrisc/cpu.h | 11 ------ target/openrisc/interrupt.c | 2 -- target/openrisc/interrupt_helper.c | 25 ++------------ target/openrisc/machine.c | 26 --------------- target/openrisc/mmu.c | 68 ++++++++++++++++---------------------- target/openrisc/sys_helper.c | 15 --------- 7 files changed, 32 insertions(+), 119 deletions(-) (limited to 'target/openrisc/machine.c') diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c index fa8e342ff7..b92de51ecf 100644 --- a/target/openrisc/cpu.c +++ b/target/openrisc/cpu.c @@ -92,10 +92,6 @@ static void openrisc_cpu_initfn(Object *obj) OpenRISCCPU *cpu = OPENRISC_CPU(obj); cs->env_ptr = &cpu->env; - -#ifndef CONFIG_USER_ONLY - cpu_openrisc_mmu_init(cpu); -#endif } /* CPU models */ diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h index 96b7f58659..a27adad085 100644 --- a/target/openrisc/cpu.h +++ b/target/openrisc/cpu.h @@ -379,17 +379,6 @@ void cpu_openrisc_count_update(OpenRISCCPU *cpu); void cpu_openrisc_timer_update(OpenRISCCPU *cpu); void cpu_openrisc_count_start(OpenRISCCPU *cpu); void cpu_openrisc_count_stop(OpenRISCCPU *cpu); - -void cpu_openrisc_mmu_init(OpenRISCCPU *cpu); -int cpu_openrisc_get_phys_nommu(OpenRISCCPU *cpu, - hwaddr *physical, - int *prot, target_ulong address, int rw); -int cpu_openrisc_get_phys_code(OpenRISCCPU *cpu, - hwaddr *physical, - int *prot, target_ulong address, int rw); -int cpu_openrisc_get_phys_data(OpenRISCCPU *cpu, - hwaddr *physical, - int *prot, target_ulong address, int rw); #endif #define OPENRISC_CPU_TYPE_SUFFIX "-" TYPE_OPENRISC_CPU diff --git a/target/openrisc/interrupt.c b/target/openrisc/interrupt.c index 2d0b55afa9..23abcf29ed 100644 --- a/target/openrisc/interrupt.c +++ b/target/openrisc/interrupt.c @@ -63,8 +63,6 @@ void openrisc_cpu_do_interrupt(CPUState *cs) env->sr &= ~SR_TEE; env->pmr &= ~PMR_DME; env->pmr &= ~PMR_SME; - env->tlb.cpu_openrisc_map_address_data = &cpu_openrisc_get_phys_nommu; - env->tlb.cpu_openrisc_map_address_code = &cpu_openrisc_get_phys_nommu; env->lock_addr = -1; if (exception > 0 && exception < EXCP_NR) { diff --git a/target/openrisc/interrupt_helper.c b/target/openrisc/interrupt_helper.c index dc97b38704..a2e9003969 100644 --- a/target/openrisc/interrupt_helper.c +++ b/target/openrisc/interrupt_helper.c @@ -29,31 +29,12 @@ void HELPER(rfe)(CPUOpenRISCState *env) #ifndef CONFIG_USER_ONLY int need_flush_tlb = (cpu->env.sr & (SR_SM | SR_IME | SR_DME)) ^ (cpu->env.esr & (SR_SM | SR_IME | SR_DME)); -#endif - cpu->env.pc = cpu->env.epcr; - cpu_set_sr(&cpu->env, cpu->env.esr); - cpu->env.lock_addr = -1; - -#ifndef CONFIG_USER_ONLY - if (cpu->env.sr & SR_DME) { - cpu->env.tlb.cpu_openrisc_map_address_data = - &cpu_openrisc_get_phys_data; - } else { - cpu->env.tlb.cpu_openrisc_map_address_data = - &cpu_openrisc_get_phys_nommu; - } - - if (cpu->env.sr & SR_IME) { - cpu->env.tlb.cpu_openrisc_map_address_code = - &cpu_openrisc_get_phys_code; - } else { - cpu->env.tlb.cpu_openrisc_map_address_code = - &cpu_openrisc_get_phys_nommu; - } - if (need_flush_tlb) { CPUState *cs = CPU(cpu); tlb_flush(cs); } #endif + cpu->env.pc = cpu->env.epcr; + cpu->env.lock_addr = -1; + cpu_set_sr(&cpu->env, cpu->env.esr); } diff --git a/target/openrisc/machine.c b/target/openrisc/machine.c index c10d28b055..73e0abcfd7 100644 --- a/target/openrisc/machine.c +++ b/target/openrisc/machine.c @@ -24,31 +24,6 @@ #include "hw/boards.h" #include "migration/cpu.h" -static int env_post_load(void *opaque, int version_id) -{ - CPUOpenRISCState *env = opaque; - - /* Restore MMU handlers */ - if (env->sr & SR_DME) { - env->tlb.cpu_openrisc_map_address_data = - &cpu_openrisc_get_phys_data; - } else { - env->tlb.cpu_openrisc_map_address_data = - &cpu_openrisc_get_phys_nommu; - } - - if (env->sr & SR_IME) { - env->tlb.cpu_openrisc_map_address_code = - &cpu_openrisc_get_phys_code; - } else { - env->tlb.cpu_openrisc_map_address_code = - &cpu_openrisc_get_phys_nommu; - } - - - return 0; -} - static const VMStateDescription vmstate_tlb_entry = { .name = "tlb_entry", .version_id = 1, @@ -102,7 +77,6 @@ static const VMStateDescription vmstate_env = { .name = "env", .version_id = 6, .minimum_version_id = 6, - .post_load = env_post_load, .fields = (VMStateField[]) { VMSTATE_UINTTL_2DARRAY(shadow_gpr, CPUOpenRISCState, 16, 32), VMSTATE_UINTTL(pc, CPUOpenRISCState), diff --git a/target/openrisc/mmu.c b/target/openrisc/mmu.c index 5665bb7cc9..b2effaa6d7 100644 --- a/target/openrisc/mmu.c +++ b/target/openrisc/mmu.c @@ -29,18 +29,16 @@ #endif #ifndef CONFIG_USER_ONLY -int cpu_openrisc_get_phys_nommu(OpenRISCCPU *cpu, - hwaddr *physical, - int *prot, target_ulong address, int rw) +static inline int get_phys_nommu(hwaddr *physical, int *prot, + target_ulong address) { *physical = address; *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; return TLBRET_MATCH; } -int cpu_openrisc_get_phys_code(OpenRISCCPU *cpu, - hwaddr *physical, - int *prot, target_ulong address, int rw) +static int get_phys_code(OpenRISCCPU *cpu, hwaddr *physical, int *prot, + target_ulong address, int rw, bool supervisor) { int vpn = address >> TARGET_PAGE_BITS; int idx = vpn & ITLB_MASK; @@ -52,8 +50,7 @@ int cpu_openrisc_get_phys_code(OpenRISCCPU *cpu, if (!(cpu->env.tlb.itlb[0][idx].mr & 1)) { return TLBRET_INVALID; } - - if (cpu->env.sr & SR_SM) { /* supervisor mode */ + if (supervisor) { if (cpu->env.tlb.itlb[0][idx].tr & SXE) { right |= PAGE_EXEC; } @@ -62,7 +59,6 @@ int cpu_openrisc_get_phys_code(OpenRISCCPU *cpu, right |= PAGE_EXEC; } } - if ((rw & 2) && ((right & PAGE_EXEC) == 0)) { return TLBRET_BADADDR; } @@ -73,9 +69,8 @@ int cpu_openrisc_get_phys_code(OpenRISCCPU *cpu, return TLBRET_MATCH; } -int cpu_openrisc_get_phys_data(OpenRISCCPU *cpu, - hwaddr *physical, - int *prot, target_ulong address, int rw) +static int get_phys_data(OpenRISCCPU *cpu, hwaddr *physical, int *prot, + target_ulong address, int rw, bool supervisor) { int vpn = address >> TARGET_PAGE_BITS; int idx = vpn & DTLB_MASK; @@ -87,8 +82,7 @@ int cpu_openrisc_get_phys_data(OpenRISCCPU *cpu, if (!(cpu->env.tlb.dtlb[0][idx].mr & 1)) { return TLBRET_INVALID; } - - if (cpu->env.sr & SR_SM) { /* supervisor mode */ + if (supervisor) { if (cpu->env.tlb.dtlb[0][idx].tr & SRE) { right |= PAGE_READ; } @@ -117,20 +111,24 @@ int cpu_openrisc_get_phys_data(OpenRISCCPU *cpu, return TLBRET_MATCH; } -static int cpu_openrisc_get_phys_addr(OpenRISCCPU *cpu, - hwaddr *physical, - int *prot, target_ulong address, - int rw) +static int get_phys_addr(OpenRISCCPU *cpu, hwaddr *physical, + int *prot, target_ulong address, int rw) { - int ret = TLBRET_MATCH; - - if (rw == MMU_INST_FETCH) { /* ITLB */ - *physical = 0; - ret = cpu->env.tlb.cpu_openrisc_map_address_code(cpu, physical, - prot, address, rw); - } else { /* DTLB */ - ret = cpu->env.tlb.cpu_openrisc_map_address_data(cpu, physical, - prot, address, rw); + bool supervisor = (cpu->env.sr & SR_SM) != 0; + int ret; + + /* Assume nommu results for a moment. */ + ret = get_phys_nommu(physical, prot, address); + + /* Overwrite with TLB lookup if enabled. */ + if (rw == MMU_INST_FETCH) { + if (cpu->env.sr & SR_IME) { + ret = get_phys_code(cpu, physical, prot, address, rw, supervisor); + } + } else { + if (cpu->env.sr & SR_DME) { + ret = get_phys_data(cpu, physical, prot, address, rw, supervisor); + } } return ret; @@ -186,8 +184,7 @@ int openrisc_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int size, hwaddr physical = 0; int prot = 0; - ret = cpu_openrisc_get_phys_addr(cpu, &physical, &prot, - address, rw); + ret = get_phys_addr(cpu, &physical, &prot, address, rw); if (ret == TLBRET_MATCH) { tlb_set_page(cs, address & TARGET_PAGE_MASK, @@ -225,17 +222,16 @@ hwaddr openrisc_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) /* Check memory for any kind of address, since during debug the gdb can ask for anything, check data tlb for address */ - miss = cpu_openrisc_get_phys_addr(cpu, &phys_addr, &prot, addr, 0); + miss = get_phys_addr(cpu, &phys_addr, &prot, addr, 0); /* Check instruction tlb */ if (miss) { - miss = cpu_openrisc_get_phys_addr(cpu, &phys_addr, &prot, addr, - MMU_INST_FETCH); + miss = get_phys_addr(cpu, &phys_addr, &prot, addr, MMU_INST_FETCH); } /* Last, fall back to a plain address */ if (miss) { - miss = cpu_openrisc_get_phys_nommu(cpu, &phys_addr, &prot, addr, 0); + miss = get_phys_nommu(&phys_addr, &prot, addr); } if (miss) { @@ -244,10 +240,4 @@ hwaddr openrisc_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) return phys_addr; } } - -void cpu_openrisc_mmu_init(OpenRISCCPU *cpu) -{ - cpu->env.tlb.cpu_openrisc_map_address_code = &cpu_openrisc_get_phys_nommu; - cpu->env.tlb.cpu_openrisc_map_address_data = &cpu_openrisc_get_phys_nommu; -} #endif diff --git a/target/openrisc/sys_helper.c b/target/openrisc/sys_helper.c index ff315f6f1a..9b4339b34e 100644 --- a/target/openrisc/sys_helper.c +++ b/target/openrisc/sys_helper.c @@ -60,21 +60,6 @@ void HELPER(mtspr)(CPUOpenRISCState *env, target_ulong spr, target_ulong rb) tlb_flush(cs); } cpu_set_sr(env, rb); - if (env->sr & SR_DME) { - env->tlb.cpu_openrisc_map_address_data = - &cpu_openrisc_get_phys_data; - } else { - env->tlb.cpu_openrisc_map_address_data = - &cpu_openrisc_get_phys_nommu; - } - - if (env->sr & SR_IME) { - env->tlb.cpu_openrisc_map_address_code = - &cpu_openrisc_get_phys_code; - } else { - env->tlb.cpu_openrisc_map_address_code = - &cpu_openrisc_get_phys_nommu; - } break; case TO_SPR(0, 18): /* PPC */ -- cgit 1.4.1 From 2acaa2331b96ee92f0df213784f9b6454c3d5edc Mon Sep 17 00:00:00 2001 From: Richard Henderson Date: Tue, 22 May 2018 19:36:27 -0700 Subject: target/openrisc: Reduce tlb to a single dimension MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit While we had defines for *_WAYS, we didn't define more than 1. Reduce the complexity by eliminating this unused dimension. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson Signed-off-by: Stafford Horne --- target/openrisc/cpu.h | 6 ++---- target/openrisc/machine.c | 6 ++---- target/openrisc/mmu.c | 30 ++++++++++++++++-------------- target/openrisc/sys_helper.c | 20 ++++++++++---------- 4 files changed, 30 insertions(+), 32 deletions(-) (limited to 'target/openrisc/machine.c') diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h index a27adad085..eaf6cdd40e 100644 --- a/target/openrisc/cpu.h +++ b/target/openrisc/cpu.h @@ -222,10 +222,8 @@ enum { /* TLB size */ enum { - DTLB_WAYS = 1, DTLB_SIZE = 64, DTLB_MASK = (DTLB_SIZE-1), - ITLB_WAYS = 1, ITLB_SIZE = 64, ITLB_MASK = (ITLB_SIZE-1), }; @@ -256,8 +254,8 @@ typedef struct OpenRISCTLBEntry { #ifndef CONFIG_USER_ONLY typedef struct CPUOpenRISCTLBContext { - OpenRISCTLBEntry itlb[ITLB_WAYS][ITLB_SIZE]; - OpenRISCTLBEntry dtlb[DTLB_WAYS][DTLB_SIZE]; + OpenRISCTLBEntry itlb[ITLB_SIZE]; + OpenRISCTLBEntry dtlb[DTLB_SIZE]; int (*cpu_openrisc_map_address_code)(struct OpenRISCCPU *cpu, hwaddr *physical, diff --git a/target/openrisc/machine.c b/target/openrisc/machine.c index 73e0abcfd7..b795b56dc6 100644 --- a/target/openrisc/machine.c +++ b/target/openrisc/machine.c @@ -42,11 +42,9 @@ static const VMStateDescription vmstate_cpu_tlb = { .minimum_version_id = 1, .minimum_version_id_old = 1, .fields = (VMStateField[]) { - VMSTATE_STRUCT_2DARRAY(itlb, CPUOpenRISCTLBContext, - ITLB_WAYS, ITLB_SIZE, 0, + VMSTATE_STRUCT_ARRAY(itlb, CPUOpenRISCTLBContext, ITLB_SIZE, 0, vmstate_tlb_entry, OpenRISCTLBEntry), - VMSTATE_STRUCT_2DARRAY(dtlb, CPUOpenRISCTLBContext, - DTLB_WAYS, DTLB_SIZE, 0, + VMSTATE_STRUCT_ARRAY(dtlb, CPUOpenRISCTLBContext, DTLB_SIZE, 0, vmstate_tlb_entry, OpenRISCTLBEntry), VMSTATE_END_OF_LIST() } diff --git a/target/openrisc/mmu.c b/target/openrisc/mmu.c index 9b4b5cf04f..856969a7f2 100644 --- a/target/openrisc/mmu.c +++ b/target/openrisc/mmu.c @@ -43,19 +43,21 @@ static int get_phys_code(OpenRISCCPU *cpu, hwaddr *physical, int *prot, int vpn = address >> TARGET_PAGE_BITS; int idx = vpn & ITLB_MASK; int right = 0; + uint32_t mr = cpu->env.tlb.itlb[idx].mr; + uint32_t tr = cpu->env.tlb.itlb[idx].tr; - if ((cpu->env.tlb.itlb[0][idx].mr >> TARGET_PAGE_BITS) != vpn) { + if ((mr >> TARGET_PAGE_BITS) != vpn) { return TLBRET_NOMATCH; } - if (!(cpu->env.tlb.itlb[0][idx].mr & 1)) { + if (!(mr & 1)) { return TLBRET_INVALID; } if (supervisor) { - if (cpu->env.tlb.itlb[0][idx].tr & SXE) { + if (tr & SXE) { right |= PAGE_EXEC; } } else { - if (cpu->env.tlb.itlb[0][idx].tr & UXE) { + if (tr & UXE) { right |= PAGE_EXEC; } } @@ -63,8 +65,7 @@ static int get_phys_code(OpenRISCCPU *cpu, hwaddr *physical, int *prot, return TLBRET_BADADDR; } - *physical = (cpu->env.tlb.itlb[0][idx].tr & TARGET_PAGE_MASK) | - (address & (TARGET_PAGE_SIZE-1)); + *physical = (tr & TARGET_PAGE_MASK) | (address & ~TARGET_PAGE_MASK); *prot = right; return TLBRET_MATCH; } @@ -75,25 +76,27 @@ static int get_phys_data(OpenRISCCPU *cpu, hwaddr *physical, int *prot, int vpn = address >> TARGET_PAGE_BITS; int idx = vpn & DTLB_MASK; int right = 0; + uint32_t mr = cpu->env.tlb.dtlb[idx].mr; + uint32_t tr = cpu->env.tlb.dtlb[idx].tr; - if ((cpu->env.tlb.dtlb[0][idx].mr >> TARGET_PAGE_BITS) != vpn) { + if ((mr >> TARGET_PAGE_BITS) != vpn) { return TLBRET_NOMATCH; } - if (!(cpu->env.tlb.dtlb[0][idx].mr & 1)) { + if (!(mr & 1)) { return TLBRET_INVALID; } if (supervisor) { - if (cpu->env.tlb.dtlb[0][idx].tr & SRE) { + if (tr & SRE) { right |= PAGE_READ; } - if (cpu->env.tlb.dtlb[0][idx].tr & SWE) { + if (tr & SWE) { right |= PAGE_WRITE; } } else { - if (cpu->env.tlb.dtlb[0][idx].tr & URE) { + if (tr & URE) { right |= PAGE_READ; } - if (cpu->env.tlb.dtlb[0][idx].tr & UWE) { + if (tr & UWE) { right |= PAGE_WRITE; } } @@ -105,8 +108,7 @@ static int get_phys_data(OpenRISCCPU *cpu, hwaddr *physical, int *prot, return TLBRET_BADADDR; } - *physical = (cpu->env.tlb.dtlb[0][idx].tr & TARGET_PAGE_MASK) | - (address & (TARGET_PAGE_SIZE-1)); + *physical = (tr & TARGET_PAGE_MASK) | (address & ~TARGET_PAGE_MASK); *prot = right; return TLBRET_MATCH; } diff --git a/target/openrisc/sys_helper.c b/target/openrisc/sys_helper.c index 9b4339b34e..7f458b0d17 100644 --- a/target/openrisc/sys_helper.c +++ b/target/openrisc/sys_helper.c @@ -86,14 +86,14 @@ void HELPER(mtspr)(CPUOpenRISCState *env, target_ulong spr, target_ulong rb) case TO_SPR(1, 512) ... TO_SPR(1, 512+DTLB_SIZE-1): /* DTLBW0MR 0-127 */ idx = spr - TO_SPR(1, 512); if (!(rb & 1)) { - tlb_flush_page(cs, env->tlb.dtlb[0][idx].mr & TARGET_PAGE_MASK); + tlb_flush_page(cs, env->tlb.dtlb[idx].mr & TARGET_PAGE_MASK); } - env->tlb.dtlb[0][idx].mr = rb; + env->tlb.dtlb[idx].mr = rb; break; case TO_SPR(1, 640) ... TO_SPR(1, 640+DTLB_SIZE-1): /* DTLBW0TR 0-127 */ idx = spr - TO_SPR(1, 640); - env->tlb.dtlb[0][idx].tr = rb; + env->tlb.dtlb[idx].tr = rb; break; case TO_SPR(1, 768) ... TO_SPR(1, 895): /* DTLBW1MR 0-127 */ case TO_SPR(1, 896) ... TO_SPR(1, 1023): /* DTLBW1TR 0-127 */ @@ -105,14 +105,14 @@ void HELPER(mtspr)(CPUOpenRISCState *env, target_ulong spr, target_ulong rb) case TO_SPR(2, 512) ... TO_SPR(2, 512+ITLB_SIZE-1): /* ITLBW0MR 0-127 */ idx = spr - TO_SPR(2, 512); if (!(rb & 1)) { - tlb_flush_page(cs, env->tlb.itlb[0][idx].mr & TARGET_PAGE_MASK); + tlb_flush_page(cs, env->tlb.itlb[idx].mr & TARGET_PAGE_MASK); } - env->tlb.itlb[0][idx].mr = rb; + env->tlb.itlb[idx].mr = rb; break; case TO_SPR(2, 640) ... TO_SPR(2, 640+ITLB_SIZE-1): /* ITLBW0TR 0-127 */ idx = spr - TO_SPR(2, 640); - env->tlb.itlb[0][idx].tr = rb; + env->tlb.itlb[idx].tr = rb; break; case TO_SPR(2, 768) ... TO_SPR(2, 895): /* ITLBW1MR 0-127 */ case TO_SPR(2, 896) ... TO_SPR(2, 1023): /* ITLBW1TR 0-127 */ @@ -244,11 +244,11 @@ target_ulong HELPER(mfspr)(CPUOpenRISCState *env, target_ulong rd, case TO_SPR(1, 512) ... TO_SPR(1, 512+DTLB_SIZE-1): /* DTLBW0MR 0-127 */ idx = spr - TO_SPR(1, 512); - return env->tlb.dtlb[0][idx].mr; + return env->tlb.dtlb[idx].mr; case TO_SPR(1, 640) ... TO_SPR(1, 640+DTLB_SIZE-1): /* DTLBW0TR 0-127 */ idx = spr - TO_SPR(1, 640); - return env->tlb.dtlb[0][idx].tr; + return env->tlb.dtlb[idx].tr; case TO_SPR(1, 768) ... TO_SPR(1, 895): /* DTLBW1MR 0-127 */ case TO_SPR(1, 896) ... TO_SPR(1, 1023): /* DTLBW1TR 0-127 */ @@ -260,11 +260,11 @@ target_ulong HELPER(mfspr)(CPUOpenRISCState *env, target_ulong rd, case TO_SPR(2, 512) ... TO_SPR(2, 512+ITLB_SIZE-1): /* ITLBW0MR 0-127 */ idx = spr - TO_SPR(2, 512); - return env->tlb.itlb[0][idx].mr; + return env->tlb.itlb[idx].mr; case TO_SPR(2, 640) ... TO_SPR(2, 640+ITLB_SIZE-1): /* ITLBW0TR 0-127 */ idx = spr - TO_SPR(2, 640); - return env->tlb.itlb[0][idx].tr; + return env->tlb.itlb[idx].tr; case TO_SPR(2, 768) ... TO_SPR(2, 895): /* ITLBW1MR 0-127 */ case TO_SPR(2, 896) ... TO_SPR(2, 1023): /* ITLBW1TR 0-127 */ -- cgit 1.4.1 From 56c3a1415653bd485b06e718c6f14e32dcfe59b3 Mon Sep 17 00:00:00 2001 From: Richard Henderson Date: Tue, 22 May 2018 20:18:20 -0700 Subject: target/openrisc: Use identical sizes for ITLB and DTLB MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The sizes are already the same, however, we can improve things if they are identical by design. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson Signed-off-by: Stafford Horne --- target/openrisc/cpu.h | 10 ++++------ target/openrisc/machine.c | 4 ++-- target/openrisc/mmu.c | 4 ++-- target/openrisc/sys_helper.c | 16 ++++++++-------- 4 files changed, 16 insertions(+), 18 deletions(-) (limited to 'target/openrisc/machine.c') diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h index c3a968ec4d..47e94659e1 100644 --- a/target/openrisc/cpu.h +++ b/target/openrisc/cpu.h @@ -222,10 +222,8 @@ enum { /* TLB size */ enum { - DTLB_SIZE = 64, - DTLB_MASK = (DTLB_SIZE-1), - ITLB_SIZE = 64, - ITLB_MASK = (ITLB_SIZE-1), + TLB_SIZE = 64, + TLB_MASK = TLB_SIZE - 1, }; /* TLB prot */ @@ -254,8 +252,8 @@ typedef struct OpenRISCTLBEntry { #ifndef CONFIG_USER_ONLY typedef struct CPUOpenRISCTLBContext { - OpenRISCTLBEntry itlb[ITLB_SIZE]; - OpenRISCTLBEntry dtlb[DTLB_SIZE]; + OpenRISCTLBEntry itlb[TLB_SIZE]; + OpenRISCTLBEntry dtlb[TLB_SIZE]; int (*cpu_openrisc_map_address_code)(struct OpenRISCCPU *cpu, hwaddr *physical, diff --git a/target/openrisc/machine.c b/target/openrisc/machine.c index b795b56dc6..3fc837b925 100644 --- a/target/openrisc/machine.c +++ b/target/openrisc/machine.c @@ -42,9 +42,9 @@ static const VMStateDescription vmstate_cpu_tlb = { .minimum_version_id = 1, .minimum_version_id_old = 1, .fields = (VMStateField[]) { - VMSTATE_STRUCT_ARRAY(itlb, CPUOpenRISCTLBContext, ITLB_SIZE, 0, + VMSTATE_STRUCT_ARRAY(itlb, CPUOpenRISCTLBContext, TLB_SIZE, 0, vmstate_tlb_entry, OpenRISCTLBEntry), - VMSTATE_STRUCT_ARRAY(dtlb, CPUOpenRISCTLBContext, DTLB_SIZE, 0, + VMSTATE_STRUCT_ARRAY(dtlb, CPUOpenRISCTLBContext, TLB_SIZE, 0, vmstate_tlb_entry, OpenRISCTLBEntry), VMSTATE_END_OF_LIST() } diff --git a/target/openrisc/mmu.c b/target/openrisc/mmu.c index b293b64e98..a4613e9ae4 100644 --- a/target/openrisc/mmu.c +++ b/target/openrisc/mmu.c @@ -41,7 +41,7 @@ static int get_phys_code(OpenRISCCPU *cpu, hwaddr *physical, int *prot, target_ulong address, int rw, bool supervisor) { int vpn = address >> TARGET_PAGE_BITS; - int idx = vpn & ITLB_MASK; + int idx = vpn & TLB_MASK; int right = 0; uint32_t mr = cpu->env.tlb.itlb[idx].mr; uint32_t tr = cpu->env.tlb.itlb[idx].tr; @@ -74,7 +74,7 @@ static int get_phys_data(OpenRISCCPU *cpu, hwaddr *physical, int *prot, target_ulong address, int rw, bool supervisor) { int vpn = address >> TARGET_PAGE_BITS; - int idx = vpn & DTLB_MASK; + int idx = vpn & TLB_MASK; int right = 0; uint32_t mr = cpu->env.tlb.dtlb[idx].mr; uint32_t tr = cpu->env.tlb.dtlb[idx].tr; diff --git a/target/openrisc/sys_helper.c b/target/openrisc/sys_helper.c index 852b219f9b..541615bfb3 100644 --- a/target/openrisc/sys_helper.c +++ b/target/openrisc/sys_helper.c @@ -80,7 +80,7 @@ void HELPER(mtspr)(CPUOpenRISCState *env, target_ulong spr, target_ulong rb) env->shadow_gpr[idx / 32][idx % 32] = rb; break; - case TO_SPR(1, 512) ... TO_SPR(1, 512+DTLB_SIZE-1): /* DTLBW0MR 0-127 */ + case TO_SPR(1, 512) ... TO_SPR(1, 512 + TLB_SIZE - 1): /* DTLBW0MR 0-127 */ idx = spr - TO_SPR(1, 512); mr = env->tlb.dtlb[idx].mr; if (mr & 1) { @@ -91,7 +91,7 @@ void HELPER(mtspr)(CPUOpenRISCState *env, target_ulong spr, target_ulong rb) } env->tlb.dtlb[idx].mr = rb; break; - case TO_SPR(1, 640) ... TO_SPR(1, 640+DTLB_SIZE-1): /* DTLBW0TR 0-127 */ + case TO_SPR(1, 640) ... TO_SPR(1, 640 + TLB_SIZE - 1): /* DTLBW0TR 0-127 */ idx = spr - TO_SPR(1, 640); env->tlb.dtlb[idx].tr = rb; break; @@ -103,7 +103,7 @@ void HELPER(mtspr)(CPUOpenRISCState *env, target_ulong spr, target_ulong rb) case TO_SPR(1, 1408) ... TO_SPR(1, 1535): /* DTLBW3TR 0-127 */ break; - case TO_SPR(2, 512) ... TO_SPR(2, 512+ITLB_SIZE-1): /* ITLBW0MR 0-127 */ + case TO_SPR(2, 512) ... TO_SPR(2, 512 + TLB_SIZE - 1): /* ITLBW0MR 0-127 */ idx = spr - TO_SPR(2, 512); mr = env->tlb.itlb[idx].mr; if (mr & 1) { @@ -114,7 +114,7 @@ void HELPER(mtspr)(CPUOpenRISCState *env, target_ulong spr, target_ulong rb) } env->tlb.itlb[idx].mr = rb; break; - case TO_SPR(2, 640) ... TO_SPR(2, 640+ITLB_SIZE-1): /* ITLBW0TR 0-127 */ + case TO_SPR(2, 640) ... TO_SPR(2, 640 + TLB_SIZE - 1): /* ITLBW0TR 0-127 */ idx = spr - TO_SPR(2, 640); env->tlb.itlb[idx].tr = rb; break; @@ -247,11 +247,11 @@ target_ulong HELPER(mfspr)(CPUOpenRISCState *env, target_ulong rd, idx = (spr - 1024); return env->shadow_gpr[idx / 32][idx % 32]; - case TO_SPR(1, 512) ... TO_SPR(1, 512+DTLB_SIZE-1): /* DTLBW0MR 0-127 */ + case TO_SPR(1, 512) ... TO_SPR(1, 512 + TLB_SIZE - 1): /* DTLBW0MR 0-127 */ idx = spr - TO_SPR(1, 512); return env->tlb.dtlb[idx].mr; - case TO_SPR(1, 640) ... TO_SPR(1, 640+DTLB_SIZE-1): /* DTLBW0TR 0-127 */ + case TO_SPR(1, 640) ... TO_SPR(1, 640 + TLB_SIZE - 1): /* DTLBW0TR 0-127 */ idx = spr - TO_SPR(1, 640); return env->tlb.dtlb[idx].tr; @@ -263,11 +263,11 @@ target_ulong HELPER(mfspr)(CPUOpenRISCState *env, target_ulong rd, case TO_SPR(1, 1408) ... TO_SPR(1, 1535): /* DTLBW3TR 0-127 */ break; - case TO_SPR(2, 512) ... TO_SPR(2, 512+ITLB_SIZE-1): /* ITLBW0MR 0-127 */ + case TO_SPR(2, 512) ... TO_SPR(2, 512 + TLB_SIZE - 1): /* ITLBW0MR 0-127 */ idx = spr - TO_SPR(2, 512); return env->tlb.itlb[idx].mr; - case TO_SPR(2, 640) ... TO_SPR(2, 640+ITLB_SIZE-1): /* ITLBW0TR 0-127 */ + case TO_SPR(2, 640) ... TO_SPR(2, 640 + TLB_SIZE - 1): /* ITLBW0TR 0-127 */ idx = spr - TO_SPR(2, 640); return env->tlb.itlb[idx].tr; -- cgit 1.4.1 From 1cc9e5d896695091eeb126f5c578b02ddd0fc0e4 Mon Sep 17 00:00:00 2001 From: Richard Henderson Date: Tue, 22 May 2018 22:04:46 -0700 Subject: target/openrisc: Increase the TLB size The architecture supports 128 TLB entries. There is no reason not to provide all of them. In the process we need to fix a bug that failed to parameterize the configuration register that tells the operating system the number of entries. Signed-off-by: Richard Henderson Signed-off-by: Stafford Horne --- v2: - Change VMState version. --- target/openrisc/cpu.c | 6 ++++-- target/openrisc/cpu.h | 2 +- target/openrisc/machine.c | 5 ++--- 3 files changed, 7 insertions(+), 6 deletions(-) (limited to 'target/openrisc/machine.c') diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c index b92de51ecf..e01ce9ed1c 100644 --- a/target/openrisc/cpu.c +++ b/target/openrisc/cpu.c @@ -57,8 +57,10 @@ static void openrisc_cpu_reset(CPUState *s) cpu->env.upr = UPR_UP | UPR_DMP | UPR_IMP | UPR_PICP | UPR_TTP | UPR_PMP; - cpu->env.dmmucfgr = (DMMUCFGR_NTW & (0 << 2)) | (DMMUCFGR_NTS & (6 << 2)); - cpu->env.immucfgr = (IMMUCFGR_NTW & (0 << 2)) | (IMMUCFGR_NTS & (6 << 2)); + cpu->env.dmmucfgr = (DMMUCFGR_NTW & (0 << 2)) + | (DMMUCFGR_NTS & (ctz32(TLB_SIZE) << 2)); + cpu->env.immucfgr = (IMMUCFGR_NTW & (0 << 2)) + | (IMMUCFGR_NTS & (ctz32(TLB_SIZE) << 2)); #ifndef CONFIG_USER_ONLY cpu->env.picmr = 0x00000000; diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h index 47e94659e1..b180e30e9e 100644 --- a/target/openrisc/cpu.h +++ b/target/openrisc/cpu.h @@ -222,7 +222,7 @@ enum { /* TLB size */ enum { - TLB_SIZE = 64, + TLB_SIZE = 128, TLB_MASK = TLB_SIZE - 1, }; diff --git a/target/openrisc/machine.c b/target/openrisc/machine.c index 3fc837b925..1eedbf3dbe 100644 --- a/target/openrisc/machine.c +++ b/target/openrisc/machine.c @@ -38,9 +38,8 @@ static const VMStateDescription vmstate_tlb_entry = { static const VMStateDescription vmstate_cpu_tlb = { .name = "cpu_tlb", - .version_id = 1, - .minimum_version_id = 1, - .minimum_version_id_old = 1, + .version_id = 2, + .minimum_version_id = 2, .fields = (VMStateField[]) { VMSTATE_STRUCT_ARRAY(itlb, CPUOpenRISCTLBContext, TLB_SIZE, 0, vmstate_tlb_entry, OpenRISCTLBEntry), -- cgit 1.4.1