From 3b5ea01e98a5e26c1adb13d966f334cb58680cf8 Mon Sep 17 00:00:00 2001 From: Nicholas Piggin Date: Fri, 24 May 2024 15:02:46 +1000 Subject: ppc/pnv: Add an LPAR per core machine option MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Recent POWER CPUs can operate in "LPAR per core" or "LPAR per thread" modes. In per-core mode, some SPRs and IPI doorbells are shared between threads in a core. In per-thread mode, supervisor and user state is not shared between threads. OpenPOWER systems after POWER8 use LPAR per thread mode, and it is required for KVM. Enterprise systems use LPAR per core mode, as they partition the machine by core. Implement a lpar-per-core machine option for powernv machines. This is fixed true for POWER8 machines, and defaults off for P9 and P10. With this change, powernv8 SMT now works sufficiently to run Linux, with a single socket. Multi-threaded KVM guests still have problems, as does multi-socket Linux boot. Reviewed-by: Cédric Le Goater Signed-off-by: Nicholas Piggin --- target/ppc/cpu_init.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'target/ppc/cpu_init.c') diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c index 5ec87c56e4..23881d09e9 100644 --- a/target/ppc/cpu_init.c +++ b/target/ppc/cpu_init.c @@ -6786,7 +6786,8 @@ void cpu_ppc_set_1lpar(PowerPCCPU *cpu) /* * pseries SMT means "LPAR per core" mode, e.g., msgsndp is usable - * between threads. + * between threads. powernv be in either mode, and it mostly affects + * supervisor visible registers and instructions. */ if (env->flags & POWERPC_FLAG_SMT) { env->flags |= POWERPC_FLAG_SMT_1LPAR; -- cgit 1.4.1