From a6ba81424a7e751fbcee40dc1f5826ba29fddd30 Mon Sep 17 00:00:00 2001 From: Paolo Bonzini Date: Tue, 18 Feb 2025 11:31:30 +0100 Subject: target/riscv: add more RISCVCPUDef fields Allow using RISCVCPUDef to replicate all the logic of custom .instance_init functions. To simulate inheritance, merge the child's RISCVCPUDef with the parent and then finally move it to the CPUState at the end of TYPE_RISCV_CPU's own instance_init function. Reviewed-by: Alistair Francis Signed-off-by: Paolo Bonzini --- target/riscv/kvm/kvm-cpu.c | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'target/riscv/kvm/kvm-cpu.c') diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c index e77f612af3..efb41fac53 100644 --- a/target/riscv/kvm/kvm-cpu.c +++ b/target/riscv/kvm/kvm-cpu.c @@ -2093,10 +2093,16 @@ static const TypeInfo riscv_kvm_cpu_type_infos[] = { #if defined(TARGET_RISCV32) .class_data = &(const RISCVCPUDef) { .misa_mxl_max = MXL_RV32, + .priv_spec = RISCV_PROFILE_ATTR_UNUSED, + .vext_spec = RISCV_PROFILE_ATTR_UNUSED, + .cfg.max_satp_mode = -1, }, #elif defined(TARGET_RISCV64) .class_data = &(const RISCVCPUDef) { .misa_mxl_max = MXL_RV64, + .priv_spec = RISCV_PROFILE_ATTR_UNUSED, + .vext_spec = RISCV_PROFILE_ATTR_UNUSED, + .cfg.max_satp_mode = -1, }, #endif } -- cgit 1.4.1