From d70080c4e37fc533fa10904b286f29449decc6f8 Mon Sep 17 00:00:00 2001 From: Jia Liu Date: Wed, 24 Oct 2012 22:17:13 +0800 Subject: target-mips: Add ASE DSP testcases Add MIPS ASE DSP testcases. Signed-off-by: Jia Liu Signed-off-by: Aurelien Jarno --- tests/tcg/mips/mips64-dsp/extp.c | 50 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 50 insertions(+) create mode 100644 tests/tcg/mips/mips64-dsp/extp.c (limited to 'tests/tcg/mips/mips64-dsp/extp.c') diff --git a/tests/tcg/mips/mips64-dsp/extp.c b/tests/tcg/mips/mips64-dsp/extp.c new file mode 100644 index 0000000000..c72f54bace --- /dev/null +++ b/tests/tcg/mips/mips64-dsp/extp.c @@ -0,0 +1,50 @@ +#include "io.h" + +int main(void) +{ + long long rt, ach, acl, dsp; + long long result; + + ach = 0x05; + acl = 0xB4CB; + dsp = 0x07; + result = 0x000C; + + __asm + ("wrdsp %1, 0x01\n\t" + "mthi %2, $ac1\n\t" + "mtlo %3, $ac1\n\t" + "extp %0, $ac1, 0x03\n\t" + "rddsp %1\n\t" + : "=r"(rt), "+r"(dsp) + : "r"(ach), "r"(acl) + ); + dsp = (dsp >> 14) & 0x01; + if ((dsp != 0) || (result != rt)) { + printf("extp wrong\n"); + + return -1; + } + + ach = 0x05; + acl = 0xB4CB; + dsp = 0x01; + + __asm + ("wrdsp %1, 0x01\n\t" + "mthi %2, $ac1\n\t" + "mtlo %3, $ac1\n\t" + "extp %0, $ac1, 0x03\n\t" + "rddsp %1\n\t" + : "=r"(rt), "+r"(dsp) + : "r"(ach), "r"(acl) + ); + dsp = (dsp >> 14) & 0x01; + if (dsp != 1) { + printf("extp wrong\n"); + + return -1; + } + + return 0; +} -- cgit 1.4.1