From 424dc390ec68263b5fc82b88f0f81bc3f374ad44 Mon Sep 17 00:00:00 2001 From: Peter Maydell Date: Thu, 11 Sep 2025 13:14:15 +0100 Subject: tests, scripts: Don't import print_function from __future__ MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Some of our Python scripts still include the line from __future__ import print_function which is intended to allow a Python 2 to handle the Python 3 print() syntax. This particular part of the future arrived many years ago, and our minimum Python version is 3.9, so we don't need to keep this line around. NB: the scripts in tests/tcg/*/gdbstub/ are run with whatever Python gdb was built against, but we can safely assume that that was a Python 3 because our supported distros are all on Python 3. In any case these are only run as part of "make check-tcg", not by end-users. Commit created with: sed -i -e '/import print_function/d' $(git grep -l 'from __future__') Signed-off-by: Peter Maydell Reviewed-by: Daniel P. Berrangé Reviewed-by: John Snow Reviewed-by: Philippe Mathieu-Daudé Message-id: 20250819102409.2117969-1-peter.maydell@linaro.org --- tests/guest-debug/test_gdbstub.py | 1 - tests/tcg/aarch64/gdbstub/test-mte.py | 1 - tests/tcg/aarch64/gdbstub/test-sve-ioctl.py | 1 - tests/tcg/aarch64/gdbstub/test-sve.py | 1 - tests/tcg/multiarch/gdbstub/interrupt.py | 1 - tests/tcg/multiarch/gdbstub/memory.py | 1 - tests/tcg/multiarch/gdbstub/sha1.py | 1 - tests/tcg/multiarch/gdbstub/test-proc-mappings.py | 1 - tests/tcg/multiarch/gdbstub/test-qxfer-auxv-read.py | 1 - tests/tcg/multiarch/gdbstub/test-qxfer-siginfo-read.py | 1 - tests/tcg/multiarch/gdbstub/test-thread-breakpoint.py | 1 - tests/tcg/s390x/gdbstub/test-signals-s390x.py | 1 - tests/tcg/s390x/gdbstub/test-svc.py | 1 - 13 files changed, 13 deletions(-) (limited to 'tests') diff --git a/tests/guest-debug/test_gdbstub.py b/tests/guest-debug/test_gdbstub.py index 4f08089e6a..e017ccb55d 100644 --- a/tests/guest-debug/test_gdbstub.py +++ b/tests/guest-debug/test_gdbstub.py @@ -1,7 +1,6 @@ """Helper functions for gdbstub testing """ -from __future__ import print_function import argparse import gdb import os diff --git a/tests/tcg/aarch64/gdbstub/test-mte.py b/tests/tcg/aarch64/gdbstub/test-mte.py index 9ad98e7a54..f4a7d7b446 100644 --- a/tests/tcg/aarch64/gdbstub/test-mte.py +++ b/tests/tcg/aarch64/gdbstub/test-mte.py @@ -1,4 +1,3 @@ -from __future__ import print_function # # Test GDB memory-tag commands that exercise the stubs for the qIsAddressTagged, # qMemTag, and QMemTag packets, which are used for manipulating allocation tags. diff --git a/tests/tcg/aarch64/gdbstub/test-sve-ioctl.py b/tests/tcg/aarch64/gdbstub/test-sve-ioctl.py index a78a3a2514..2c5c218031 100644 --- a/tests/tcg/aarch64/gdbstub/test-sve-ioctl.py +++ b/tests/tcg/aarch64/gdbstub/test-sve-ioctl.py @@ -1,4 +1,3 @@ -from __future__ import print_function # # Test the SVE ZReg reports the right amount of data. It uses the # sve-ioctl test and examines the register data each time the diff --git a/tests/tcg/aarch64/gdbstub/test-sve.py b/tests/tcg/aarch64/gdbstub/test-sve.py index 84cdcd4a32..7b0489a622 100644 --- a/tests/tcg/aarch64/gdbstub/test-sve.py +++ b/tests/tcg/aarch64/gdbstub/test-sve.py @@ -1,4 +1,3 @@ -from __future__ import print_function # # Test the SVE registers are visible and changeable via gdbstub # diff --git a/tests/tcg/multiarch/gdbstub/interrupt.py b/tests/tcg/multiarch/gdbstub/interrupt.py index 2d5654d154..4eccdb41b9 100644 --- a/tests/tcg/multiarch/gdbstub/interrupt.py +++ b/tests/tcg/multiarch/gdbstub/interrupt.py @@ -1,4 +1,3 @@ -from __future__ import print_function # # Test some of the system debug features with the multiarch memory # test. It is a port of the original vmlinux focused test case but diff --git a/tests/tcg/multiarch/gdbstub/memory.py b/tests/tcg/multiarch/gdbstub/memory.py index 532b92e7fb..76d75e5251 100644 --- a/tests/tcg/multiarch/gdbstub/memory.py +++ b/tests/tcg/multiarch/gdbstub/memory.py @@ -1,4 +1,3 @@ -from __future__ import print_function # # Test some of the system debug features with the multiarch memory # test. It is a port of the original vmlinux focused test case but diff --git a/tests/tcg/multiarch/gdbstub/sha1.py b/tests/tcg/multiarch/gdbstub/sha1.py index 1ce711a402..3403b82fd4 100644 --- a/tests/tcg/multiarch/gdbstub/sha1.py +++ b/tests/tcg/multiarch/gdbstub/sha1.py @@ -1,4 +1,3 @@ -from __future__ import print_function # # A very simple smoke test for debugging the SHA1 userspace test on # each target. diff --git a/tests/tcg/multiarch/gdbstub/test-proc-mappings.py b/tests/tcg/multiarch/gdbstub/test-proc-mappings.py index 6eb6ebf7b1..796dca75f0 100644 --- a/tests/tcg/multiarch/gdbstub/test-proc-mappings.py +++ b/tests/tcg/multiarch/gdbstub/test-proc-mappings.py @@ -1,7 +1,6 @@ """Test that gdbstub has access to proc mappings. This runs as a sourced script (via -x, via run-test.py).""" -from __future__ import print_function import gdb from test_gdbstub import gdb_exit, main, report diff --git a/tests/tcg/multiarch/gdbstub/test-qxfer-auxv-read.py b/tests/tcg/multiarch/gdbstub/test-qxfer-auxv-read.py index 00c26ab4a9..fa36c943d6 100644 --- a/tests/tcg/multiarch/gdbstub/test-qxfer-auxv-read.py +++ b/tests/tcg/multiarch/gdbstub/test-qxfer-auxv-read.py @@ -1,4 +1,3 @@ -from __future__ import print_function # # Test auxiliary vector is loaded via gdbstub # diff --git a/tests/tcg/multiarch/gdbstub/test-qxfer-siginfo-read.py b/tests/tcg/multiarch/gdbstub/test-qxfer-siginfo-read.py index 862596b07a..b18fa1234f 100644 --- a/tests/tcg/multiarch/gdbstub/test-qxfer-siginfo-read.py +++ b/tests/tcg/multiarch/gdbstub/test-qxfer-siginfo-read.py @@ -1,4 +1,3 @@ -from __future__ import print_function # # Test gdbstub Xfer:siginfo:read stub. # diff --git a/tests/tcg/multiarch/gdbstub/test-thread-breakpoint.py b/tests/tcg/multiarch/gdbstub/test-thread-breakpoint.py index 4d6b6b9fbe..49cbc3548f 100644 --- a/tests/tcg/multiarch/gdbstub/test-thread-breakpoint.py +++ b/tests/tcg/multiarch/gdbstub/test-thread-breakpoint.py @@ -1,4 +1,3 @@ -from __future__ import print_function # # Test auxiliary vector is loaded via gdbstub # diff --git a/tests/tcg/s390x/gdbstub/test-signals-s390x.py b/tests/tcg/s390x/gdbstub/test-signals-s390x.py index b6b7b39fc4..398ad534eb 100644 --- a/tests/tcg/s390x/gdbstub/test-signals-s390x.py +++ b/tests/tcg/s390x/gdbstub/test-signals-s390x.py @@ -1,4 +1,3 @@ -from __future__ import print_function # # Test that signals and debugging mix well together on s390x. diff --git a/tests/tcg/s390x/gdbstub/test-svc.py b/tests/tcg/s390x/gdbstub/test-svc.py index 17210b4e02..29a0aa0ede 100644 --- a/tests/tcg/s390x/gdbstub/test-svc.py +++ b/tests/tcg/s390x/gdbstub/test-svc.py @@ -1,7 +1,6 @@ """Test single-stepping SVC. This runs as a sourced script (via -x, via run-test.py).""" -from __future__ import print_function import gdb from test_gdbstub import main, report -- cgit 1.4.1 From 904b8aae52a7b23fa00285decba535bd1e8f8d50 Mon Sep 17 00:00:00 2001 From: Vacha Bhavsar Date: Tue, 9 Sep 2025 16:10:12 +0000 Subject: target/arm: Added test case for SME register exposure to GDB This patch adds a test case to test SME register exposure to a remote gdb debugging session. This test simply sets and reads SME registers. Signed-off-by: Vacha Bhavsar Message-id: 20250909161012.2561593-4-vacha.bhavsar@oss.qualcomm.com [PMM: fixed various python formatting nits] Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- configure | 6 ++ tests/tcg/aarch64/Makefile.target | 29 +++++++++ tests/tcg/aarch64/gdbstub/test-sme.py | 117 ++++++++++++++++++++++++++++++++++ 3 files changed, 152 insertions(+) create mode 100644 tests/tcg/aarch64/gdbstub/test-sme.py (limited to 'tests') diff --git a/configure b/configure index 274a778764..9aea02cf6a 100755 --- a/configure +++ b/configure @@ -1839,6 +1839,12 @@ for target in $target_list; do echo "GDB=$gdb_bin" >> $config_target_mak fi + if test "${gdb_arches#*$arch}" != "$gdb_arches" && version_ge $gdb_version 14.1; then + echo "GDB_HAS_SME_TILES=y" >> $config_target_mak + else + echo "GDB_HAS_SME_TILES=n" >> $config_target_mak + fi + if test "${gdb_arches#*aarch64}" != "$gdb_arches" && version_ge $gdb_version 15.1; then echo "GDB_HAS_MTE=y" >> $config_target_mak fi diff --git a/tests/tcg/aarch64/Makefile.target b/tests/tcg/aarch64/Makefile.target index 16ddcf4f88..1755874bee 100644 --- a/tests/tcg/aarch64/Makefile.target +++ b/tests/tcg/aarch64/Makefile.target @@ -134,6 +134,35 @@ run-gdbstub-sve-ioctls: sve-ioctls EXTRA_RUNS += run-gdbstub-sysregs run-gdbstub-sve-ioctls +ifneq ($(CROSS_AS_HAS_ARMV9_SME),) +# SME gdbstub tests + +run-gdbstub-sysregs-sme: sysregs + $(call run-test, $@, $(GDB_SCRIPT) \ + --gdb $(GDB) \ + --qemu $(QEMU) --qargs "$(QEMU_OPTS)" \ + --bin $< --test $(AARCH64_SRC)/gdbstub/test-sme.py \ + -- test_sme --gdb_basic_za_test, \ + basic gdbstub SME support) + +ifeq ($(GDB_HAS_SME_TILES),y) +run-gdbstub-sysregs-sme-tile-slice: sysregs + $(call run-test, $@, $(GDB_SCRIPT) \ + --gdb $(GDB) \ + --qemu $(QEMU) --qargs "$(QEMU_OPTS)" \ + --bin $< --test $(AARCH64_SRC)/gdbstub/test-sme.py \ + -- test_sme --gdb_tile_slice_test, \ + gdbstub SME ZA tile slice support) +else +run-gdbstub-sysregs-sme-tile-slice: sysregs + $(call skip-test,"gdbstub SME ZA tile slice support", \ + "selected gdb ($(GDB)) does not support SME ZA tile slices") +endif + +EXTRA_RUNS += run-gdbstub-sysregs-sme run-gdbstub-sysregs-sme-tile-slice + +endif + ifeq ($(GDB_HAS_MTE),y) run-gdbstub-mte: mte-8 $(call run-test, $@, $(GDB_SCRIPT) \ diff --git a/tests/tcg/aarch64/gdbstub/test-sme.py b/tests/tcg/aarch64/gdbstub/test-sme.py new file mode 100644 index 0000000000..ec03189642 --- /dev/null +++ b/tests/tcg/aarch64/gdbstub/test-sme.py @@ -0,0 +1,117 @@ +# +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# Test the SME registers are visible and changeable via gdbstub +# +# This is launched via tests/guest-debug/run-test.py +# + +import argparse +import gdb +from test_gdbstub import main, report + +MAGIC = 0x01020304 +BASIC_ZA_TEST = 0 +TILE_SLICE_TEST = 0 + + +def run_test(): + """Run the requested test(s) for SME ZA gdbstub support""" + + if BASIC_ZA_TEST: + run_basic_sme_za_gdbstub_support_test() + if TILE_SLICE_TEST: + run_basic_sme_za_tile_slice_gdbstub_support_test() + + +def run_basic_sme_za_gdbstub_support_test(): + """Test reads and writes to the SME ZA register at the byte level""" + + frame = gdb.selected_frame() + rname = "za" + za = frame.read_register(rname) + report(True, "Reading %s" % rname) + + # Writing to the ZA register, byte by byte. + for i in range(0, 16): + for j in range(0, 16): + cmd = "set $za[%d][%d] = 0x01" % (i, j) + gdb.execute(cmd) + report(True, "%s" % cmd) + + # Reading from the ZA register, byte by byte. + for i in range(0, 16): + for j in range(0, 16): + reg = "$za[%d][%d]" % (i, j) + v = gdb.parse_and_eval(reg) + report(str(v.type) == "uint8_t", "size of %s" % (reg)) + report(v == 0x1, "%s is 0x%x" % (reg, 0x1)) + + +def run_basic_sme_za_tile_slice_gdbstub_support_test(): + """Test reads and writes of SME ZA horizontal and vertical tile slices + + Test if SME ZA tile slices, both horizontal and vertical, + can be correctly read and written to. The sizes to test + are quadwords and doublewords. + """ + + sizes = {} + sizes["q"] = "uint128_t" + sizes["d"] = "uint64_t" + + # Accessing requested sizes of elements of ZA + for size in sizes: + + # Accessing various ZA tiles + for i in range(0, 4): + + # Accessing various horizontal slices for each ZA tile + for j in range(0, 4): + # Writing to various elements in each tile slice + for k in range(0, 4): + cmd = "set $za%dh%c%d[%d] = 0x%x" % (i, size, j, k, MAGIC) + gdb.execute(cmd) + report(True, "%s" % cmd) + + # Reading from the written elements in each tile slice + for k in range(0, 4): + reg = "$za%dh%c%d[%d]" % (i, size, j, k) + v = gdb.parse_and_eval(reg) + report(str(v.type) == sizes[size], "size of %s" % (reg)) + report(v == MAGIC, "%s is 0x%x" % (reg, MAGIC)) + + # Accessing various vertical slices for each ZA tile + for j in range(0, 4): + # Writing to various elements in each tile slice + for k in range(0, 4): + cmd = "set $za%dv%c%d[%d] = 0x%x" % (i, size, j, k, MAGIC) + gdb.execute(cmd) + report(True, "%s" % cmd) + + # Reading from the written elements in each tile slice + for k in range(0, 4): + reg = "$za%dv%c%d[%d]" % (i, size, j, k) + v = gdb.parse_and_eval(reg) + report(str(v.type) == sizes[size], "size of %s" % (reg)) + report(v == MAGIC, "%s is 0x%x" % (reg, MAGIC)) + + +parser = argparse.ArgumentParser(description="A gdbstub test for SME support") +parser.add_argument("--gdb_basic_za_test", + help="Enable test for basic SME ZA support", + action="store_true") +parser.add_argument("--gdb_tile_slice_test", + help="Enable test for ZA tile slice support", + action="store_true") +args = parser.parse_args() + +if args.gdb_basic_za_test: + BASIC_ZA_TEST = 1 +if args.gdb_tile_slice_test: + TILE_SLICE_TEST = 1 + +main(run_test, expected_arch="aarch64") -- cgit 1.4.1 From c69520c13d6ea45a69a7a49361806fa05b19046d Mon Sep 17 00:00:00 2001 From: Shameer Kolothum Date: Fri, 29 Aug 2025 09:25:31 +0100 Subject: bios-tables-test: Allow for smmuv3 test data. The tests to be added exercise both legacy(iommu=smmuv3) and new -device arm-smmuv3,.. cases. Reviewed-by: Jonathan Cameron Reviewed-by: Eric Auger Tested-by: Eric Auger Tested-by: Nicolin Chen Signed-off-by: Shameer Kolothum Signed-off-by: Shameer Kolothum Reviewed-by: Donald Dutile Reviewed-by: Nicolin Chen Message-id: 20250829082543.7680-10-skolothumtho@nvidia.com Signed-off-by: Peter Maydell --- tests/data/acpi/aarch64/virt/DSDT.smmuv3-dev | 0 tests/data/acpi/aarch64/virt/DSDT.smmuv3-legacy | 0 tests/data/acpi/aarch64/virt/IORT.smmuv3-dev | 0 tests/data/acpi/aarch64/virt/IORT.smmuv3-legacy | 0 tests/qtest/bios-tables-test-allowed-diff.h | 4 ++++ 5 files changed, 4 insertions(+) create mode 100644 tests/data/acpi/aarch64/virt/DSDT.smmuv3-dev create mode 100644 tests/data/acpi/aarch64/virt/DSDT.smmuv3-legacy create mode 100644 tests/data/acpi/aarch64/virt/IORT.smmuv3-dev create mode 100644 tests/data/acpi/aarch64/virt/IORT.smmuv3-legacy (limited to 'tests') diff --git a/tests/data/acpi/aarch64/virt/DSDT.smmuv3-dev b/tests/data/acpi/aarch64/virt/DSDT.smmuv3-dev new file mode 100644 index 0000000000..e69de29bb2 diff --git a/tests/data/acpi/aarch64/virt/DSDT.smmuv3-legacy b/tests/data/acpi/aarch64/virt/DSDT.smmuv3-legacy new file mode 100644 index 0000000000..e69de29bb2 diff --git a/tests/data/acpi/aarch64/virt/IORT.smmuv3-dev b/tests/data/acpi/aarch64/virt/IORT.smmuv3-dev new file mode 100644 index 0000000000..e69de29bb2 diff --git a/tests/data/acpi/aarch64/virt/IORT.smmuv3-legacy b/tests/data/acpi/aarch64/virt/IORT.smmuv3-legacy new file mode 100644 index 0000000000..e69de29bb2 diff --git a/tests/qtest/bios-tables-test-allowed-diff.h b/tests/qtest/bios-tables-test-allowed-diff.h index dfb8523c8b..2e3e3ccdce 100644 --- a/tests/qtest/bios-tables-test-allowed-diff.h +++ b/tests/qtest/bios-tables-test-allowed-diff.h @@ -1 +1,5 @@ /* List of comma-separated changed AML files to ignore */ +"tests/data/acpi/aarch64/virt/DSDT.smmuv3-legacy", +"tests/data/acpi/aarch64/virt/DSDT.smmuv3-dev", +"tests/data/acpi/aarch64/virt/IORT.smmuv3-legacy", +"tests/data/acpi/aarch64/virt/IORT.smmuv3-dev", -- cgit 1.4.1 From 3f8cd046c151c471d9a34181320f4a7d3f72b32a Mon Sep 17 00:00:00 2001 From: Shameer Kolothum Date: Fri, 29 Aug 2025 09:25:32 +0100 Subject: qtest/bios-tables-test: Add tests for legacy smmuv3 and smmuv3 device For the legacy SMMUv3 test, the setup includes three PCIe Root Complexes, one of which has bypass_iommu enabled. The generated IORT table contains a single SMMUv3 node, a Root Complex(RC) node and 1 ITS node. RC node features 4 ID mappings, of which 2 points to SMMU node and the remaining ones points to ITS. pcie.0 -> {SMMU0} -> {ITS} {RC} pcie.1 -> {SMMU0} -> {ITS} pcie.2 -> {ITS} [all other ids] -> {ITS} For the -device arm-smmuv3,... test, the configuration also includes three Root Complexes, with two connected to separate SMMUv3 devices. The resulting IORT table contains 1 RC node, 2 SMMU nodes and 1 ITS node. RC node features 4 ID mappings. 2 of them target the 2 SMMU nodes while the others targets the ITS. pcie.0 -> {SMMU0} -> {ITS} {RC} pcie.1 -> {SMMU1} -> {ITS} pcie.2 -> {ITS} [all other ids] -> {ITS} Reviewed-by: Jonathan Cameron Reviewed-by: Eric Auger Tested-by: Eric Auger Tested-by: Nicolin Chen Signed-off-by: Shameer Kolothum Signed-off-by: Shameer Kolothum Reviewed-by: Donald Dutile Reviewed-by: Nicolin Chen Message-id: 20250829082543.7680-11-skolothumtho@nvidia.com Signed-off-by: Peter Maydell --- tests/qtest/bios-tables-test.c | 86 ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 86 insertions(+) (limited to 'tests') diff --git a/tests/qtest/bios-tables-test.c b/tests/qtest/bios-tables-test.c index e7e6926c81..4fa8ac5096 100644 --- a/tests/qtest/bios-tables-test.c +++ b/tests/qtest/bios-tables-test.c @@ -2337,6 +2337,86 @@ static void test_acpi_aarch64_virt_viot(void) free_test_data(&data); } +static void test_acpi_aarch64_virt_smmuv3_legacy(void) +{ + test_data data = { + .machine = "virt", + .arch = "aarch64", + .tcg_only = true, + .uefi_fl1 = "pc-bios/edk2-aarch64-code.fd", + .uefi_fl2 = "pc-bios/edk2-arm-vars.fd", + .ram_start = 0x40000000ULL, + .scan_len = 128ULL * MiB, + }; + + /* + * cdrom is plugged into scsi controller to avoid conflict + * with pxb-pcie. See comments in test_acpi_aarch64_virt_tcg_pxb() for + * details. + * + * The setup includes three PCIe root complexes, one of which has + * bypass_iommu enabled. The generated IORT table contains a single + * SMMUv3 node and a Root Complex node with three ID mappings. Two + * of the ID mappings have output references pointing to the SMMUv3 + * node and the remaining one points to ITS. + */ + data.variant = ".smmuv3-legacy"; + test_acpi_one(" -device pcie-root-port,chassis=1,id=pci.1" + " -device virtio-scsi-pci,id=scsi0,bus=pci.1" + " -drive file=" + "tests/data/uefi-boot-images/bios-tables-test.aarch64.iso.qcow2," + "if=none,media=cdrom,id=drive-scsi0-0-0-1,readonly=on" + " -device scsi-cd,bus=scsi0.0,scsi-id=0," + "drive=drive-scsi0-0-0-1,id=scsi0-0-0-1,bootindex=1" + " -cpu cortex-a57" + " -M iommu=smmuv3" + " -device pxb-pcie,id=pcie.1,bus=pcie.0,bus_nr=0x10" + " -device pxb-pcie,id=pcie.2,bus=pcie.0,bus_nr=0x20,bypass_iommu=on", + &data); + free_test_data(&data); +} + +static void test_acpi_aarch64_virt_smmuv3_dev(void) +{ + test_data data = { + .machine = "virt", + .arch = "aarch64", + .tcg_only = true, + .uefi_fl1 = "pc-bios/edk2-aarch64-code.fd", + .uefi_fl2 = "pc-bios/edk2-arm-vars.fd", + .ram_start = 0x40000000ULL, + .scan_len = 128ULL * MiB, + }; + + /* + * cdrom is plugged into scsi controller to avoid conflict + * with pxb-pcie. See comments in test_acpi_aarch64_virt_tcg_pxb() + * for details. + * + * The setup includes three PCie root complexes, two of which are + * connected to separate SMMUv3 devices. The resulting IORT table + * contains two SMMUv3 nodes and a Root Complex node with ID mappings + * of which two of the ID mappings have output references pointing + * to two different SMMUv3 nodes and the remaining ones pointing to + * ITS. + */ + data.variant = ".smmuv3-dev"; + test_acpi_one(" -device pcie-root-port,chassis=1,id=pci.1" + " -device virtio-scsi-pci,id=scsi0,bus=pci.1" + " -drive file=" + "tests/data/uefi-boot-images/bios-tables-test.aarch64.iso.qcow2," + "if=none,media=cdrom,id=drive-scsi0-0-0-1,readonly=on" + " -device scsi-cd,bus=scsi0.0,scsi-id=0," + "drive=drive-scsi0-0-0-1,id=scsi0-0-0-1,bootindex=1" + " -cpu cortex-a57" + " -device arm-smmuv3,primary-bus=pcie.0,id=smmuv3.0" + " -device pxb-pcie,id=pcie.1,bus=pcie.0,bus_nr=0x10" + " -device arm-smmuv3,primary-bus=pcie.1,id=smmuv3.1" + " -device pxb-pcie,id=pcie.2,bus=pcie.0,bus_nr=0x20", + &data); + free_test_data(&data); +} + #ifndef _WIN32 # define DEV_NULL "/dev/null" #else @@ -2768,6 +2848,12 @@ int main(int argc, char *argv[]) if (qtest_has_device("virtio-iommu-pci")) { qtest_add_func("acpi/virt/viot", test_acpi_aarch64_virt_viot); } + qtest_add_func("acpi/virt/smmuv3-legacy", + test_acpi_aarch64_virt_smmuv3_legacy); + if (qtest_has_device("arm-smmuv3")) { + qtest_add_func("acpi/virt/smmuv3-dev", + test_acpi_aarch64_virt_smmuv3_dev); + } } } else if (strcmp(arch, "riscv64") == 0) { if (has_tcg && qtest_has_device("virtio-blk-pci")) { -- cgit 1.4.1 From d35146a6606cf6ebb4e24bb97dfc0330f074f6e3 Mon Sep 17 00:00:00 2001 From: Shameer Kolothum Date: Fri, 29 Aug 2025 09:25:33 +0100 Subject: qtest/bios-tables-test: Update tables for smmuv3 tests For the legacy smmuv3 test case, generated IORT has a single SMMUv3 node, a Root Complex(RC) node and 1 ITS node. RC node features 4 ID mappings, of which 2 points to SMMU node and the remaining ones points to ITS. pcie.0 -> {SMMU0} -> {ITS} {RC} pcie.1 -> {SMMU0} -> {ITS} pcie.2 -> {ITS} [all other ids] -> {ITS} ... [030h 0048 1] Type : 00 [031h 0049 2] Length : 0018 [033h 0051 1] Revision : 01 [034h 0052 4] Identifier : 00000000 [038h 0056 4] Mapping Count : 00000000 [03Ch 0060 4] Mapping Offset : 00000000 [040h 0064 4] ItsCount : 00000001 [044h 0068 4] Identifiers : 00000000 [048h 0072 1] Type : 04 [049h 0073 2] Length : 0058 [04Bh 0075 1] Revision : 04 [04Ch 0076 4] Identifier : 00000001 [050h 0080 4] Mapping Count : 00000001 [054h 0084 4] Mapping Offset : 00000044 [058h 0088 8] Base Address : 0000000009050000 [060h 0096 4] Flags (decoded below) : 00000001 COHACC Override : 1 HTTU Override : 0 Proximity Domain Valid : 0 [064h 0100 4] Reserved : 00000000 [068h 0104 8] VATOS Address : 0000000000000000 [070h 0112 4] Model : 00000000 [074h 0116 4] Event GSIV : 0000006A [078h 0120 4] PRI GSIV : 0000006B [07Ch 0124 4] GERR GSIV : 0000006D [080h 0128 4] Sync GSIV : 0000006C [084h 0132 4] Proximity Domain : 00000000 [088h 0136 4] Device ID Mapping Index : 00000000 [08Ch 0140 4] Input base : 00000000 [090h 0144 4] ID Count : 0000FFFF [094h 0148 4] Output Base : 00000000 [098h 0152 4] Output Reference : 00000030 [09Ch 0156 4] Flags (decoded below) : 00000000 Single Mapping : 0 [0A0h 0160 1] Type : 02 [0A1h 0161 2] Length : 0074 [0A3h 0163 1] Revision : 03 [0A4h 0164 4] Identifier : 00000002 [0A8h 0168 4] Mapping Count : 00000004 [0ACh 0172 4] Mapping Offset : 00000024 [0B0h 0176 8] Memory Properties : [IORT Memory Access Properties] [0B0h 0176 4] Cache Coherency : 00000001 [0B4h 0180 1] Hints (decoded below) : 00 Transient : 0 Write Allocate : 0 Read Allocate : 0 Override : 0 [0B5h 0181 2] Reserved : 0000 [0B7h 0183 1] Memory Flags (decoded below) : 03 Coherency : 1 Device Attribute : 1 [0B8h 0184 4] ATS Attribute : 00000000 [0BCh 0188 4] PCI Segment Number : 00000000 [0C0h 0192 1] Memory Size Limit : 40 [0C1h 0193 2] PASID Capabilities : 0000 [0C3h 0195 1] Reserved : 00 [0C4h 0196 4] Input base : 00000000 [0C8h 0200 4] ID Count : 000001FF [0CCh 0204 4] Output Base : 00000000 [0D0h 0208 4] Output Reference : 00000048 [0D4h 0212 4] Flags (decoded below) : 00000000 Single Mapping : 0 [0D8h 0216 4] Input base : 00001000 [0DCh 0220 4] ID Count : 000000FF [0E0h 0224 4] Output Base : 00001000 [0E4h 0228 4] Output Reference : 00000048 [0E8h 0232 4] Flags (decoded below) : 00000000 Single Mapping : 0 [0ECh 0236 4] Input base : 00000200 [0F0h 0240 4] ID Count : 00000DFF [0F4h 0244 4] Output Base : 00000200 [0F8h 0248 4] Output Reference : 00000030 [0FCh 0252 4] Flags (decoded below) : 00000000 Single Mapping : 0 [100h 0256 4] Input base : 00001100 [104h 0260 4] ID Count : 0000EEFF [108h 0264 4] Output Base : 00001100 [10Ch 0268 4] Output Reference : 00000030 [110h 0272 4] Flags (decoded below) : 00000000 Single Mapping : 0 For the smmuv3-dev test case, IORT has 2 SMMUV3 nodes, 1 RC node and 1 ITS node. RC node features 4 ID mappings. 2 of them target the 2 SMMU nodes while the others targets the ITS. pcie.0 -> {SMMU0} -> {ITS} {RC} pcie.1 -> {SMMU1} -> {ITS} pcie.2 -> {ITS} [all other ids] -> {ITS} ... [030h 0048 1] Type : 00 [031h 0049 2] Length : 0018 [033h 0051 1] Revision : 01 [034h 0052 4] Identifier : 00000000 [038h 0056 4] Mapping Count : 00000000 [03Ch 0060 4] Mapping Offset : 00000000 [040h 0064 4] ItsCount : 00000001 [044h 0068 4] Identifiers : 00000000 [048h 0072 1] Type : 04 [049h 0073 2] Length : 0058 [04Bh 0075 1] Revision : 04 [04Ch 0076 4] Identifier : 00000001 [050h 0080 4] Mapping Count : 00000001 [054h 0084 4] Mapping Offset : 00000044 [058h 0088 8] Base Address : 000000000C000000 [060h 0096 4] Flags (decoded below) : 00000001 COHACC Override : 1 HTTU Override : 0 Proximity Domain Valid : 0 [064h 0100 4] Reserved : 00000000 [068h 0104 8] VATOS Address : 0000000000000000 [070h 0112 4] Model : 00000000 [074h 0116 4] Event GSIV : 00000090 [078h 0120 4] PRI GSIV : 00000091 [07Ch 0124 4] GERR GSIV : 00000093 [080h 0128 4] Sync GSIV : 00000092 [084h 0132 4] Proximity Domain : 00000000 [088h 0136 4] Device ID Mapping Index : 00000000 [08Ch 0140 4] Input base : 00000000 [090h 0144 4] ID Count : 0000FFFF [094h 0148 4] Output Base : 00000000 [098h 0152 4] Output Reference : 00000030 [09Ch 0156 4] Flags (decoded below) : 00000000 Single Mapping : 0 [0A0h 0160 1] Type : 04 [0A1h 0161 2] Length : 0058 [0A3h 0163 1] Revision : 04 [0A4h 0164 4] Identifier : 00000002 [0A8h 0168 4] Mapping Count : 00000001 [0ACh 0172 4] Mapping Offset : 00000044 [0B0h 0176 8] Base Address : 000000000C020000 [0B8h 0184 4] Flags (decoded below) : 00000001 COHACC Override : 1 HTTU Override : 0 Proximity Domain Valid : 0 [0BCh 0188 4] Reserved : 00000000 [0C0h 0192 8] VATOS Address : 0000000000000000 [0C8h 0200 4] Model : 00000000 [0CCh 0204 4] Event GSIV : 00000094 [0D0h 0208 4] PRI GSIV : 00000095 [0D4h 0212 4] GERR GSIV : 00000097 [0D8h 0216 4] Sync GSIV : 00000096 [0DCh 0220 4] Proximity Domain : 00000000 [0E0h 0224 4] Device ID Mapping Index : 00000000 [0E4h 0228 4] Input base : 00000000 [0E8h 0232 4] ID Count : 0000FFFF [0ECh 0236 4] Output Base : 00000000 [0F0h 0240 4] Output Reference : 00000030 [0F4h 0244 4] Flags (decoded below) : 00000000 Single Mapping : 0 [0F8h 0248 1] Type : 02 [0F9h 0249 2] Length : 0074 [0FBh 0251 1] Revision : 03 [0FCh 0252 4] Identifier : 00000003 [100h 0256 4] Mapping Count : 00000004 [104h 0260 4] Mapping Offset : 00000024 [108h 0264 8] Memory Properties : [IORT Memory Access Properties] [108h 0264 4] Cache Coherency : 00000001 [10Ch 0268 1] Hints (decoded below) : 00 Transient : 0 Write Allocate : 0 Read Allocate : 0 Override : 0 [10Dh 0269 2] Reserved : 0000 [10Fh 0271 1] Memory Flags (decoded below) : 03 Coherency : 1 Device Attribute : 1 [110h 0272 4] ATS Attribute : 00000000 [114h 0276 4] PCI Segment Number : 00000000 [118h 0280 1] Memory Size Limit : 40 [119h 0281 2] PASID Capabilities : 0000 [11Bh 0283 1] Reserved : 00 [11Ch 0284 4] Input base : 00000000 [120h 0288 4] ID Count : 000001FF [124h 0292 4] Output Base : 00000000 [128h 0296 4] Output Reference : 00000048 [12Ch 0300 4] Flags (decoded below) : 00000000 Single Mapping : 0 [130h 0304 4] Input base : 00001000 [134h 0308 4] ID Count : 000000FF [138h 0312 4] Output Base : 00001000 [13Ch 0316 4] Output Reference : 000000A0 [140h 0320 4] Flags (decoded below) : 00000000 Single Mapping : 0 [144h 0324 4] Input base : 00000200 [148h 0328 4] ID Count : 00000DFF [14Ch 0332 4] Output Base : 00000200 [150h 0336 4] Output Reference : 00000030 [154h 0340 4] Flags (decoded below) : 00000000 Single Mapping : 0 [158h 0344 4] Input base : 00001100 [15Ch 0348 4] ID Count : 0000EEFF [160h 0352 4] Output Base : 00001100 [164h 0356 4] Output Reference : 00000030 [168h 0360 4] Flags (decoded below) : 00000000 Single Mapping : 0 Note: DSDT changes are not described here as it is not impacted by the way the SMMUv3 is instantiated. Reviewed-by: Jonathan Cameron Reviewed-by: Eric Auger Tested-by: Eric Auger Tested-by: Nicolin Chen Signed-off-by: Shameer Kolothum Signed-off-by: Shameer Kolothum Reviewed-by: Donald Dutile Reviewed-by: Nicolin Chen Message-id: 20250829082543.7680-12-skolothumtho@nvidia.com Signed-off-by: Peter Maydell --- tests/data/acpi/aarch64/virt/DSDT.smmuv3-dev | Bin 0 -> 10230 bytes tests/data/acpi/aarch64/virt/DSDT.smmuv3-legacy | Bin 0 -> 10230 bytes tests/data/acpi/aarch64/virt/IORT.smmuv3-dev | Bin 0 -> 364 bytes tests/data/acpi/aarch64/virt/IORT.smmuv3-legacy | Bin 0 -> 276 bytes tests/qtest/bios-tables-test-allowed-diff.h | 4 ---- 5 files changed, 4 deletions(-) (limited to 'tests') diff --git a/tests/data/acpi/aarch64/virt/DSDT.smmuv3-dev b/tests/data/acpi/aarch64/virt/DSDT.smmuv3-dev index e69de29bb2..53d4c07f42 100644 Binary files a/tests/data/acpi/aarch64/virt/DSDT.smmuv3-dev and b/tests/data/acpi/aarch64/virt/DSDT.smmuv3-dev differ diff --git a/tests/data/acpi/aarch64/virt/DSDT.smmuv3-legacy b/tests/data/acpi/aarch64/virt/DSDT.smmuv3-legacy index e69de29bb2..53d4c07f42 100644 Binary files a/tests/data/acpi/aarch64/virt/DSDT.smmuv3-legacy and b/tests/data/acpi/aarch64/virt/DSDT.smmuv3-legacy differ diff --git a/tests/data/acpi/aarch64/virt/IORT.smmuv3-dev b/tests/data/acpi/aarch64/virt/IORT.smmuv3-dev index e69de29bb2..67be268f62 100644 Binary files a/tests/data/acpi/aarch64/virt/IORT.smmuv3-dev and b/tests/data/acpi/aarch64/virt/IORT.smmuv3-dev differ diff --git a/tests/data/acpi/aarch64/virt/IORT.smmuv3-legacy b/tests/data/acpi/aarch64/virt/IORT.smmuv3-legacy index e69de29bb2..41981a449f 100644 Binary files a/tests/data/acpi/aarch64/virt/IORT.smmuv3-legacy and b/tests/data/acpi/aarch64/virt/IORT.smmuv3-legacy differ diff --git a/tests/qtest/bios-tables-test-allowed-diff.h b/tests/qtest/bios-tables-test-allowed-diff.h index 2e3e3ccdce..dfb8523c8b 100644 --- a/tests/qtest/bios-tables-test-allowed-diff.h +++ b/tests/qtest/bios-tables-test-allowed-diff.h @@ -1,5 +1 @@ /* List of comma-separated changed AML files to ignore */ -"tests/data/acpi/aarch64/virt/DSDT.smmuv3-legacy", -"tests/data/acpi/aarch64/virt/DSDT.smmuv3-dev", -"tests/data/acpi/aarch64/virt/IORT.smmuv3-legacy", -"tests/data/acpi/aarch64/virt/IORT.smmuv3-dev", -- cgit 1.4.1