From d02d06f8f1299eb7a4422c283b9b9cbb4deb0cf9 Mon Sep 17 00:00:00 2001 From: Michael Tokarev Date: Wed, 23 Aug 2023 09:53:15 +0300 Subject: util: spelling fixes MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Michael Tokarev Reviewed-by: Philippe Mathieu-Daudé Message-ID: <20230823065335.1919380-3-mjt@tls.msk.ru> Signed-off-by: Philippe Mathieu-Daudé --- util/cpuinfo-i386.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'util/cpuinfo-i386.c') diff --git a/util/cpuinfo-i386.c b/util/cpuinfo-i386.c index 3a7b7e0ad1..b2ed65bb10 100644 --- a/util/cpuinfo-i386.c +++ b/util/cpuinfo-i386.c @@ -1,6 +1,6 @@ /* * SPDX-License-Identifier: GPL-2.0-or-later - * Host specific cpu indentification for x86. + * Host specific cpu identification for x86. */ #include "qemu/osdep.h" @@ -74,7 +74,7 @@ unsigned __attribute__((constructor)) cpuinfo_init(void) * of their memory operands to be 16-byte aligned. * * AMD has provided an even stronger guarantee that processors - * with AVX provide 16-byte atomicity for all cachable, + * with AVX provide 16-byte atomicity for all cacheable, * naturally aligned single loads and stores, e.g. MOVDQU. * * See https://gcc.gnu.org/bugzilla/show_bug.cgi?id=104688 -- cgit 1.4.1