Properly support TPIDR register

2 files changed, 4 insertions, 3 deletions

diff --git a/src/focaccia/arch/aarch64.py b/src/focaccia/arch/aarch64.py
index 5a3ff3e..1067495 100644
--- a/src/focaccia/arch/aarch64.py
+++ b/src/focaccia/arch/aarch64.py
@@ -90,6 +90,8 @@ registers = [
          ('F',    6, 7),
          ('M',    0, 4),
     ),
+
+    _Reg(('TPIDR', 0, 64)),
 ]
 
 # Names of registers in the architecture
@@ -128,6 +130,7 @@ regname_aliases = {
     'Q29': 'V29',
     'Q30': 'V30',
     'Q31': 'V31',
+    'TPIDR_EL0': 'TPIDR',
 }
 
 def decompose_cpsr(cpsr: int) -> dict[str, int]:
diff --git a/src/focaccia/symbolic.py b/src/focaccia/symbolic.py
index 321b39d..6510de5 100644
--- a/src/focaccia/symbolic.py
+++ b/src/focaccia/symbolic.py
@@ -594,14 +594,12 @@ class _LLDBConcreteState(ReadableProgramState):
 
     def read_register(self, reg: str) -> int:
         regname = self.arch.to_regname(reg)
-        if regname is None and reg != "DCZID_EL0" and reg != "TPIDR_EL0":
+        if regname is None and reg != "DCZID_EL0":
             raise RegisterAccessError(reg, f'Not a register name: {reg}')
 
         try:
             if reg == "DCZID_EL0":
                 return 4
-            if reg == "TPIDR_EL0":
-                return 0x4206c8
             return self._target.read_register(regname)
         except ConcreteRegisterError:
             raise RegisterAccessError(regname, '')